include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8555cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_BOOKE            1       /* BOOKE */
  18 #define CONFIG_E500             1       /* BOOKE e500 family */
  19 #define CONFIG_CPM2             1       /* has CPM2 */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  22
  23 #define CONFIG_PCI_INDIRECT_BRIDGE
  24 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  25 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  26 #define CONFIG_ENV_OVERWRITE
  27
  28 #define CONFIG_FSL_VIA
  29
  30 #ifndef __ASSEMBLY__
  31 extern unsigned long get_clock_freq(void);
  32 #endif
  33 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  34
  35 /*
  36  * These can be toggled for performance analysis, otherwise use default.
  37  */
  38 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  39 #define CONFIG_BTB                          /* toggle branch predition */
  40
  41 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  42 #define CONFIG_SYS_MEMTEST_END          0x00400000
  43
  44 #define CONFIG_SYS_CCSRBAR              0xe0000000
  45 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  46
  47 /* DDR Setup */
  48 #define CONFIG_SYS_FSL_DDR1
  49 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  50 #define CONFIG_DDR_SPD
  51 #undef CONFIG_FSL_DDR_INTERACTIVE
  52
  53 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  54
  55 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  56 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  57
  58 #define CONFIG_NUM_DDR_CONTROLLERS      1
  59 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  60 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  61
  62 /* I2C addresses of SPD EEPROMs */
  63 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  64
  65 /* Make sure required options are set */
  66 #ifndef CONFIG_SPD_EEPROM
  67 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  68 #endif
  69
  70 #undef CONFIG_CLOCKS_IN_MHZ
  71
  72 /*
  73  * Local Bus Definitions
  74  */
  75
  76 /*
  77  * FLASH on the Local Bus
  78  * Two banks, 8M each, using the CFI driver.
  79  * Boot from BR0/OR0 bank at 0xff00_0000
  80  * Alternate BR1/OR1 bank at 0xff80_0000
  81  *
  82  * BR0, BR1:
  83  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  84  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  85  *    Port Size = 16 bits = BRx[19:20] = 10
  86  *    Use GPCM = BRx[24:26] = 000
  87  *    Valid = BRx[31] = 1
  88  *
  89  * 0    4    8    12   16   20   24   28
  90  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
  91  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
  92  *
  93  * OR0, OR1:
  94  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  95  *    Reserved ORx[17:18] = 11, confusion here?
  96  *    CSNT = ORx[20] = 1
  97  *    ACS = half cycle delay = ORx[21:22] = 11
  98  *    SCY = 6 = ORx[24:27] = 0110
  99  *    TRLX = use relaxed timing = ORx[29] = 1
 100  *    EAD = use external address latch delay = OR[31] = 1
 101  *
 102  * 0    4    8    12   16   20   24   28
 103  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 104  */
 105
 106 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 107
 108 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 109 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 110
 111 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 112 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 113
 114 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 117 #undef  CONFIG_SYS_FLASH_CHECKSUM
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 120
 121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 122
 123 #define CONFIG_FLASH_CFI_DRIVER
 124 #define CONFIG_SYS_FLASH_CFI
 125 #define CONFIG_SYS_FLASH_EMPTY_INFO
 126
 127 /*
 128  * SDRAM on the Local Bus
 129  */
 130 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 131 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 132
 133 /*
 134  * Base Register 2 and Option Register 2 configure SDRAM.
 135  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 136  *
 137  * For BR2, need:
 138  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 139  *    port-size = 32-bits = BR2[19:20] = 11
 140  *    no parity checking = BR2[21:22] = 00
 141  *    SDRAM for MSEL = BR2[24:26] = 011
 142  *    Valid = BR[31] = 1
 143  *
 144  * 0    4    8    12   16   20   24   28
 145  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 146  *
 147  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 148  * FIXME: the top 17 bits of BR2.
 149  */
 150
 151 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 152
 153 /*
 154  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 155  *
 156  * For OR2, need:
 157  *    64MB mask for AM, OR2[0:7] = 1111 1100
 158  *                 XAM, OR2[17:18] = 11
 159  *    9 columns OR2[19-21] = 010
 160  *    13 rows   OR2[23-25] = 100
 161  *    EAD set for extra time OR[31] = 1
 162  *
 163  * 0    4    8    12   16   20   24   28
 164  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 165  */
 166
 167 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 168
 169 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 170 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 171 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 172 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 173
 174 /*
 175  * Common settings for all Local Bus SDRAM commands.
 176  * At run time, either BSMA1516 (for CPU 1.1)
 177  *                  or BSMA1617 (for CPU 1.0) (old)
 178  * is OR'ed in too.
 179  */
 180 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 181                                 | LSDMR_PRETOACT7       \
 182                                 | LSDMR_ACTTORW7        \
 183                                 | LSDMR_BL8             \
 184                                 | LSDMR_WRC4            \
 185                                 | LSDMR_CL3             \
 186                                 | LSDMR_RFEN            \
 187                                 )
 188
 189 /*
 190  * The CADMUS registers are connected to CS3 on CDS.
 191  * The new memory map places CADMUS at 0xf8000000.
 192  *
 193  * For BR3, need:
 194  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 195  *    port-size = 8-bits  = BR[19:20] = 01
 196  *    no parity checking  = BR[21:22] = 00
 197  *    GPMC for MSEL       = BR[24:26] = 000
 198  *    Valid               = BR[31]    = 1
 199  *
 200  * 0    4    8    12   16   20   24   28
 201  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 202  *
 203  * For OR3, need:
 204  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 205  *    disable buffer ctrl OR[19]    = 0
 206  *    CSNT                OR[20]    = 1
 207  *    ACS                 OR[21:22] = 11
 208  *    XACS                OR[23]    = 1
 209  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 210  *    SETA                OR[28]    = 0
 211  *    TRLX                OR[29]    = 1
 212  *    EHTR                OR[30]    = 1
 213  *    EAD extra time      OR[31]    = 1
 214  *
 215  * 0    4    8    12   16   20   24   28
 216  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 217  */
 218
 219 #define CONFIG_FSL_CADMUS
 220
 221 #define CADMUS_BASE_ADDR 0xf8000000
 222 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 223 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 224
 225 #define CONFIG_SYS_INIT_RAM_LOCK        1
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 227 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 228
 229 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 230 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 231
 232 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 233 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 234
 235 /* Serial Port */
 236 #define CONFIG_CONS_INDEX     2
 237 #define CONFIG_SYS_NS16550_SERIAL
 238 #define CONFIG_SYS_NS16550_REG_SIZE    1
 239 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 240
 241 #define CONFIG_SYS_BAUDRATE_TABLE  \
 242         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 243
 244 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 245 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 246
 247 /*
 248  * I2C
 249  */
 250 #define CONFIG_SYS_I2C
 251 #define CONFIG_SYS_I2C_FSL
 252 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 253 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 254 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 255 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 256
 257 /* EEPROM */
 258 #define CONFIG_ID_EEPROM
 259 #define CONFIG_SYS_I2C_EEPROM_CCID
 260 #define CONFIG_SYS_ID_EEPROM
 261 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 262 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 263
 264 /*
 265  * General PCI
 266  * Addresses are mapped 1-1.
 267  */
 268 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 269 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 270 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 271 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 272 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 273 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 274 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 275 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 276
 277 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 278 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 279 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 280 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 281 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 282 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 283 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 284 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 285
 286 #ifdef CONFIG_LEGACY
 287 #define BRIDGE_ID 17
 288 #define VIA_ID 2
 289 #else
 290 #define BRIDGE_ID 28
 291 #define VIA_ID 4
 292 #endif
 293
 294 #if defined(CONFIG_PCI)
 295
 296 #define CONFIG_MPC85XX_PCI2
 297
 298 #undef CONFIG_EEPRO100
 299 #undef CONFIG_TULIP
 300
 301 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 302 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 303
 304 #endif  /* CONFIG_PCI */
 305
 306 #if defined(CONFIG_TSEC_ENET)
 307
 308 #define CONFIG_MII              1       /* MII PHY management */
 309 #define CONFIG_TSEC1    1
 310 #define CONFIG_TSEC1_NAME       "TSEC0"
 311 #define CONFIG_TSEC2    1
 312 #define CONFIG_TSEC2_NAME       "TSEC1"
 313 #define TSEC1_PHY_ADDR          0
 314 #define TSEC2_PHY_ADDR          1
 315 #define TSEC1_PHYIDX            0
 316 #define TSEC2_PHYIDX            0
 317 #define TSEC1_FLAGS             TSEC_GIGABIT
 318 #define TSEC2_FLAGS             TSEC_GIGABIT
 319
 320 /* Options are: TSEC[0-1] */
 321 #define CONFIG_ETHPRIME         "TSEC0"
 322
 323 #endif  /* CONFIG_TSEC_ENET */
 324
 325 /*
 326  * Environment
 327  */
 328 #define CONFIG_ENV_IS_IN_FLASH  1
 329 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 330 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 331 #define CONFIG_ENV_SIZE         0x2000
 332
 333 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 334 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 335
 336 /*
 337  * BOOTP options
 338  */
 339 #define CONFIG_BOOTP_BOOTFILESIZE
 340 #define CONFIG_BOOTP_BOOTPATH
 341 #define CONFIG_BOOTP_GATEWAY
 342 #define CONFIG_BOOTP_HOSTNAME
 343
 344 /*
 345  * Command line configuration.
 346  */
 347 #define CONFIG_CMD_IRQ
 348 #define CONFIG_CMD_REGINFO
 349
 350 #if defined(CONFIG_PCI)
 351     #define CONFIG_CMD_PCI
 352 #endif
 353
 354 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 355
 356 /*
 357  * Miscellaneous configurable options
 358  */
 359 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 360 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 361 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 362 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 363 #if defined(CONFIG_CMD_KGDB)
 364 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 365 #else
 366 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 367 #endif
 368 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 369 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 370 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 371
 372 /*
 373  * For booting Linux, the board info and command line data
 374  * have to be in the first 64 MB of memory, since this is
 375  * the maximum mapped by the Linux kernel during initialization.
 376  */
 377 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 378 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 379
 380 #if defined(CONFIG_CMD_KGDB)
 381 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 382 #endif
 383
 384 /*
 385  * Environment Configuration
 386  */
 387 #if defined(CONFIG_TSEC_ENET)
 388 #define CONFIG_HAS_ETH0
 389 #define CONFIG_HAS_ETH1
 390 #define CONFIG_HAS_ETH2
 391 #endif
 392
 393 #define CONFIG_IPADDR    192.168.1.253
 394
 395 #define CONFIG_HOSTNAME  unknown
 396 #define CONFIG_ROOTPATH  "/nfsroot"
 397 #define CONFIG_BOOTFILE  "your.uImage"
 398
 399 #define CONFIG_SERVERIP  192.168.1.1
 400 #define CONFIG_GATEWAYIP 192.168.1.1
 401 #define CONFIG_NETMASK   255.255.255.0
 402
 403 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 404
 405 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 406
 407 #define CONFIG_BAUDRATE 115200
 408
 409 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 410    "netdev=eth0\0"                                                      \
 411    "consoledev=ttyS1\0"                                                 \
 412    "ramdiskaddr=600000\0"                                               \
 413    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 414    "fdtaddr=400000\0"                                                   \
 415    "fdtfile=your.fdt.dtb\0"
 416
 417 #define CONFIG_NFSBOOTCOMMAND                                           \
 418    "setenv bootargs root=/dev/nfs rw "                                  \
 419       "nfsroot=$serverip:$rootpath "                                    \
 420       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 421       "console=$consoledev,$baudrate $othbootargs;"                     \
 422    "tftp $loadaddr $bootfile;"                                          \
 423    "tftp $fdtaddr $fdtfile;"                                            \
 424    "bootm $loadaddr - $fdtaddr"
 425
 426 #define CONFIG_RAMBOOTCOMMAND \
 427    "setenv bootargs root=/dev/ram rw "                                  \
 428       "console=$consoledev,$baudrate $othbootargs;"                     \
 429    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 430    "tftp $loadaddr $bootfile;"                                          \
 431    "bootm $loadaddr $ramdiskaddr"
 432
 433 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 434
 435 #endif  /* __CONFIG_H */