include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8555cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41 */
  36 #define CONFIG_CPM2             1       /* has CPM2 */
  37 #define CONFIG_MPC8555          1       /* MPC8555 specific */
  38 #define CONFIG_MPC8555CDS       1       /* MPC8555CDS board specific */
  39
  40 #define CONFIG_PCI
  41 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  42 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  43 #define CONFIG_ENV_OVERWRITE
  44 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  45
  46 #define CONFIG_FSL_VIA
  47
  48
  49 /*
  50  * When initializing flash, if we cannot find the manufacturer ID,
  51  * assume this is the AMD flash associated with the CDS board.
  52  * This allows booting from a promjet.
  53  */
  54 #define CONFIG_ASSUME_AMD_FLASH
  55
  56 #ifndef __ASSEMBLY__
  57 extern unsigned long get_clock_freq(void);
  58 #endif
  59 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  60
  61 /*
  62  * These can be toggled for performance analysis, otherwise use default.
  63  */
  64 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  65 #define CONFIG_BTB                          /* toggle branch predition */
  66 #define CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
  67
  68 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  69 #define CONFIG_SYS_MEMTEST_END          0x00400000
  70
  71 /*
  72  * Base addresses -- Note these are effective addresses where the
  73  * actual resources get mapped (not physical addresses)
  74  */
  75 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  76 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  77 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  78 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  79
  80 /* DDR Setup */
  81 #define CONFIG_FSL_DDR1
  82 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  83 #define CONFIG_DDR_SPD
  84 #undef CONFIG_FSL_DDR_INTERACTIVE
  85
  86 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  87
  88 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  89 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  90
  91 #define CONFIG_NUM_DDR_CONTROLLERS      1
  92 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  93 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  94
  95 /* I2C addresses of SPD EEPROMs */
  96 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  97
  98 /* Make sure required options are set */
  99 #ifndef CONFIG_SPD_EEPROM
 100 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 101 #endif
 102
 103 #undef CONFIG_CLOCKS_IN_MHZ
 104
 105 /*
 106  * Local Bus Definitions
 107  */
 108
 109 /*
 110  * FLASH on the Local Bus
 111  * Two banks, 8M each, using the CFI driver.
 112  * Boot from BR0/OR0 bank at 0xff00_0000
 113  * Alternate BR1/OR1 bank at 0xff80_0000
 114  *
 115  * BR0, BR1:
 116  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 117  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 118  *    Port Size = 16 bits = BRx[19:20] = 10
 119  *    Use GPCM = BRx[24:26] = 000
 120  *    Valid = BRx[31] = 1
 121  *
 122  * 0    4    8    12   16   20   24   28
 123  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 124  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 125  *
 126  * OR0, OR1:
 127  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 128  *    Reserved ORx[17:18] = 11, confusion here?
 129  *    CSNT = ORx[20] = 1
 130  *    ACS = half cycle delay = ORx[21:22] = 11
 131  *    SCY = 6 = ORx[24:27] = 0110
 132  *    TRLX = use relaxed timing = ORx[29] = 1
 133  *    EAD = use external address latch delay = OR[31] = 1
 134  *
 135  * 0    4    8    12   16   20   24   28
 136  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 137  */
 138
 139 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 140
 141 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 142 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 143
 144 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 145 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 146
 147 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 149 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 150 #undef  CONFIG_SYS_FLASH_CHECKSUM
 151 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 152 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 153
 154 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 155
 156 #define CONFIG_FLASH_CFI_DRIVER
 157 #define CONFIG_SYS_FLASH_CFI
 158 #define CONFIG_SYS_FLASH_EMPTY_INFO
 159
 160
 161 /*
 162  * SDRAM on the Local Bus
 163  */
 164 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 165 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 166
 167 /*
 168  * Base Register 2 and Option Register 2 configure SDRAM.
 169  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 170  *
 171  * For BR2, need:
 172  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 173  *    port-size = 32-bits = BR2[19:20] = 11
 174  *    no parity checking = BR2[21:22] = 00
 175  *    SDRAM for MSEL = BR2[24:26] = 011
 176  *    Valid = BR[31] = 1
 177  *
 178  * 0    4    8    12   16   20   24   28
 179  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 180  *
 181  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 182  * FIXME: the top 17 bits of BR2.
 183  */
 184
 185 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 186
 187 /*
 188  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 189  *
 190  * For OR2, need:
 191  *    64MB mask for AM, OR2[0:7] = 1111 1100
 192  *                 XAM, OR2[17:18] = 11
 193  *    9 columns OR2[19-21] = 010
 194  *    13 rows   OR2[23-25] = 100
 195  *    EAD set for extra time OR[31] = 1
 196  *
 197  * 0    4    8    12   16   20   24   28
 198  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 199  */
 200
 201 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 202
 203 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 204 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 205 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 206 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 207
 208 /*
 209  * LSDMR masks
 210  */
 211 #define CONFIG_SYS_LBC_LSDMR_RFEN       (1 << (31 -  1))
 212 #define CONFIG_SYS_LBC_LSDMR_BSMA1516   (3 << (31 - 10))
 213 #define CONFIG_SYS_LBC_LSDMR_BSMA1617   (4 << (31 - 10))
 214 #define CONFIG_SYS_LBC_LSDMR_RFCR16     (7 << (31 - 16))
 215 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7  (7 << (31 - 19))
 216 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7   (7 << (31 - 22))
 217 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6   (6 << (31 - 22))
 218 #define CONFIG_SYS_LBC_LSDMR_BL8        (1 << (31 - 23))
 219 #define CONFIG_SYS_LBC_LSDMR_WRC4       (0 << (31 - 27))
 220 #define CONFIG_SYS_LBC_LSDMR_CL3        (3 << (31 - 31))
 221
 222 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL  (0 << (31 - 4))
 223 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH  (1 << (31 - 4))
 224 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH  (2 << (31 - 4))
 225 #define CONFIG_SYS_LBC_LSDMR_OP_MRW     (3 << (31 - 4))
 226 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH   (4 << (31 - 4))
 227 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL  (5 << (31 - 4))
 228 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK  (6 << (31 - 4))
 229 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV   (7 << (31 - 4))
 230
 231 /*
 232  * Common settings for all Local Bus SDRAM commands.
 233  * At run time, either BSMA1516 (for CPU 1.1)
 234  *                  or BSMA1617 (for CPU 1.0) (old)
 235  * is OR'ed in too.
 236  */
 237 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( CONFIG_SYS_LBC_LSDMR_RFCR16           \
 238                                 | CONFIG_SYS_LBC_LSDMR_PRETOACT7        \
 239                                 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
 240                                 | CONFIG_SYS_LBC_LSDMR_BL8              \
 241                                 | CONFIG_SYS_LBC_LSDMR_WRC4             \
 242                                 | CONFIG_SYS_LBC_LSDMR_CL3              \
 243                                 | CONFIG_SYS_LBC_LSDMR_RFEN             \
 244                                 )
 245
 246 /*
 247  * The CADMUS registers are connected to CS3 on CDS.
 248  * The new memory map places CADMUS at 0xf8000000.
 249  *
 250  * For BR3, need:
 251  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 252  *    port-size = 8-bits  = BR[19:20] = 01
 253  *    no parity checking  = BR[21:22] = 00
 254  *    GPMC for MSEL       = BR[24:26] = 000
 255  *    Valid               = BR[31]    = 1
 256  *
 257  * 0    4    8    12   16   20   24   28
 258  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 259  *
 260  * For OR3, need:
 261  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 262  *    disable buffer ctrl OR[19]    = 0
 263  *    CSNT                OR[20]    = 1
 264  *    ACS                 OR[21:22] = 11
 265  *    XACS                OR[23]    = 1
 266  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 267  *    SETA                OR[28]    = 0
 268  *    TRLX                OR[29]    = 1
 269  *    EHTR                OR[30]    = 1
 270  *    EAD extra time      OR[31]    = 1
 271  *
 272  * 0    4    8    12   16   20   24   28
 273  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 274  */
 275
 276 #define CONFIG_FSL_CADMUS
 277
 278 #define CADMUS_BASE_ADDR 0xf8000000
 279 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 280 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 281
 282 #define CONFIG_L1_INIT_RAM
 283 #define CONFIG_SYS_INIT_RAM_LOCK        1
 284 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 285 #define CONFIG_SYS_INIT_RAM_END 0x4000      /* End of used area in RAM */
 286
 287 #define CONFIG_SYS_GBL_DATA_SIZE        128         /* num bytes initial data */
 288 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 289 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 290
 291 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 292 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 293
 294 /* Serial Port */
 295 #define CONFIG_CONS_INDEX     2
 296 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 297 #define CONFIG_SYS_NS16550
 298 #define CONFIG_SYS_NS16550_SERIAL
 299 #define CONFIG_SYS_NS16550_REG_SIZE    1
 300 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 301
 302 #define CONFIG_SYS_BAUDRATE_TABLE  \
 303         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 304
 305 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 306 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 307
 308 /* Use the HUSH parser */
 309 #define CONFIG_SYS_HUSH_PARSER
 310 #ifdef  CONFIG_SYS_HUSH_PARSER
 311 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 312 #endif
 313
 314 /* pass open firmware flat tree */
 315 #define CONFIG_OF_LIBFDT                1
 316 #define CONFIG_OF_BOARD_SETUP           1
 317 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 318
 319 #define CONFIG_SYS_64BIT_VSPRINTF       1
 320 #define CONFIG_SYS_64BIT_STRTOUL        1
 321
 322 /*
 323  * I2C
 324  */
 325 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 326 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 327 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 328 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 329 #define CONFIG_SYS_I2C_SLAVE            0x7F
 330 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 331 #define CONFIG_SYS_I2C_OFFSET           0x3000
 332
 333 /* EEPROM */
 334 #define CONFIG_ID_EEPROM
 335 #define CONFIG_SYS_I2C_EEPROM_CCID
 336 #define CONFIG_SYS_ID_EEPROM
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 339
 340 /*
 341  * General PCI
 342  * Addresses are mapped 1-1.
 343  */
 344 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 345 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 346 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 347 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 348 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 349 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 350
 351 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 352 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 353 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 354 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 355 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 356 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 357
 358 #ifdef CONFIG_LEGACY
 359 #define BRIDGE_ID 17
 360 #define VIA_ID 2
 361 #else
 362 #define BRIDGE_ID 28
 363 #define VIA_ID 4
 364 #endif
 365
 366 #if defined(CONFIG_PCI)
 367
 368 #define CONFIG_NET_MULTI
 369 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 370 #define CONFIG_MPC85XX_PCI2
 371
 372 #undef CONFIG_EEPRO100
 373 #undef CONFIG_TULIP
 374
 375 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 376 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 377
 378 #endif  /* CONFIG_PCI */
 379
 380
 381 #if defined(CONFIG_TSEC_ENET)
 382
 383 #ifndef CONFIG_NET_MULTI
 384 #define CONFIG_NET_MULTI        1
 385 #endif
 386
 387 #define CONFIG_MII              1       /* MII PHY management */
 388 #define CONFIG_TSEC1    1
 389 #define CONFIG_TSEC1_NAME       "TSEC0"
 390 #define CONFIG_TSEC2    1
 391 #define CONFIG_TSEC2_NAME       "TSEC1"
 392 #define TSEC1_PHY_ADDR          0
 393 #define TSEC2_PHY_ADDR          1
 394 #define TSEC1_PHYIDX            0
 395 #define TSEC2_PHYIDX            0
 396 #define TSEC1_FLAGS             TSEC_GIGABIT
 397 #define TSEC2_FLAGS             TSEC_GIGABIT
 398
 399 /* Options are: TSEC[0-1] */
 400 #define CONFIG_ETHPRIME         "TSEC0"
 401
 402 #endif  /* CONFIG_TSEC_ENET */
 403
 404 /*
 405  * Environment
 406  */
 407 #define CONFIG_ENV_IS_IN_FLASH  1
 408 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 409 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 410 #define CONFIG_ENV_SIZE         0x2000
 411
 412 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 413 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 414
 415 /*
 416  * BOOTP options
 417  */
 418 #define CONFIG_BOOTP_BOOTFILESIZE
 419 #define CONFIG_BOOTP_BOOTPATH
 420 #define CONFIG_BOOTP_GATEWAY
 421 #define CONFIG_BOOTP_HOSTNAME
 422
 423
 424 /*
 425  * Command line configuration.
 426  */
 427 #include <config_cmd_default.h>
 428
 429 #define CONFIG_CMD_PING
 430 #define CONFIG_CMD_I2C
 431 #define CONFIG_CMD_MII
 432 #define CONFIG_CMD_ELF
 433 #define CONFIG_CMD_IRQ
 434 #define CONFIG_CMD_SETEXPR
 435
 436 #if defined(CONFIG_PCI)
 437     #define CONFIG_CMD_PCI
 438 #endif
 439
 440
 441 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 442
 443 /*
 444  * Miscellaneous configurable options
 445  */
 446 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 447 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 448 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 449 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 450 #if defined(CONFIG_CMD_KGDB)
 451 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 452 #else
 453 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 454 #endif
 455 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 456 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 457 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 458 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 459
 460 /*
 461  * For booting Linux, the board info and command line data
 462  * have to be in the first 8 MB of memory, since this is
 463  * the maximum mapped by the Linux kernel during initialization.
 464  */
 465 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 466
 467 /*
 468  * Internal Definitions
 469  *
 470  * Boot Flags
 471  */
 472 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 473 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 474
 475 #if defined(CONFIG_CMD_KGDB)
 476 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 477 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 478 #endif
 479
 480 /*
 481  * Environment Configuration
 482  */
 483
 484 /* The mac addresses for all ethernet interface */
 485 #if defined(CONFIG_TSEC_ENET)
 486 #define CONFIG_HAS_ETH0
 487 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 488 #define CONFIG_HAS_ETH1
 489 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 490 #define CONFIG_HAS_ETH2
 491 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 492 #endif
 493
 494 #define CONFIG_IPADDR    192.168.1.253
 495
 496 #define CONFIG_HOSTNAME  unknown
 497 #define CONFIG_ROOTPATH  /nfsroot
 498 #define CONFIG_BOOTFILE  your.uImage
 499
 500 #define CONFIG_SERVERIP  192.168.1.1
 501 #define CONFIG_GATEWAYIP 192.168.1.1
 502 #define CONFIG_NETMASK   255.255.255.0
 503
 504 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 505
 506 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 507 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 508
 509 #define CONFIG_BAUDRATE 115200
 510
 511 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 512    "netdev=eth0\0"                                                      \
 513    "consoledev=ttyS1\0"                                                 \
 514    "ramdiskaddr=600000\0"                                               \
 515    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 516    "fdtaddr=400000\0"                                                   \
 517    "fdtfile=your.fdt.dtb\0"
 518
 519 #define CONFIG_NFSBOOTCOMMAND                                           \
 520    "setenv bootargs root=/dev/nfs rw "                                  \
 521       "nfsroot=$serverip:$rootpath "                                    \
 522       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 523       "console=$consoledev,$baudrate $othbootargs;"                     \
 524    "tftp $loadaddr $bootfile;"                                          \
 525    "tftp $fdtaddr $fdtfile;"                                            \
 526    "bootm $loadaddr - $fdtaddr"
 527
 528 #define CONFIG_RAMBOOTCOMMAND \
 529    "setenv bootargs root=/dev/ram rw "                                  \
 530       "console=$consoledev,$baudrate $othbootargs;"                     \
 531    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 532    "tftp $loadaddr $bootfile;"                                          \
 533    "bootm $loadaddr $ramdiskaddr"
 534
 535 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 536
 537 #endif  /* __CONFIG_H */