include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8555cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41 */
  36 #define CONFIG_CPM2             1       /* has CPM2 */
  37 #define CONFIG_MPC8555          1       /* MPC8555 specific */
  38 #define CONFIG_MPC8555CDS       1       /* MPC8555CDS board specific */
  39
  40 #define CONFIG_PCI
  41 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  42 #define CONFIG_ENV_OVERWRITE
  43 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  44 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  45 #undef CONFIG_DDR_2T_TIMING             /* Sets the 2T timing bit */
  46
  47 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  48 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  49
  50 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  51
  52 /*
  53  * When initializing flash, if we cannot find the manufacturer ID,
  54  * assume this is the AMD flash associated with the CDS board.
  55  * This allows booting from a promjet.
  56  */
  57 #define CONFIG_ASSUME_AMD_FLASH
  58
  59 #define MPC85xx_DDR_SDRAM_CLK_CNTL      /* 85xx has clock control reg */
  60
  61 #ifndef __ASSEMBLY__
  62 extern unsigned long get_clock_freq(void);
  63 #endif
  64 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  65
  66 /*
  67  * These can be toggled for performance analysis, otherwise use default.
  68  */
  69 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  70 #define CONFIG_BTB                          /* toggle branch predition */
  71 #define CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  74
  75 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  76 #define CFG_MEMTEST_START       0x00200000      /* memtest works on */
  77 #define CFG_MEMTEST_END         0x00400000
  78
  79 /*
  80  * Base addresses -- Note these are effective addresses where the
  81  * actual resources get mapped (not physical addresses)
  82  */
  83 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  84 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  85 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
  91 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
  92
  93 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  94
  95 /*
  96  * Make sure required options are set
  97  */
  98 #ifndef CONFIG_SPD_EEPROM
  99 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 100 #endif
 101
 102 #undef CONFIG_CLOCKS_IN_MHZ
 103
 104
 105 /*
 106  * Local Bus Definitions
 107  */
 108
 109 /*
 110  * FLASH on the Local Bus
 111  * Two banks, 8M each, using the CFI driver.
 112  * Boot from BR0/OR0 bank at 0xff00_0000
 113  * Alternate BR1/OR1 bank at 0xff80_0000
 114  *
 115  * BR0, BR1:
 116  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 117  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 118  *    Port Size = 16 bits = BRx[19:20] = 10
 119  *    Use GPCM = BRx[24:26] = 000
 120  *    Valid = BRx[31] = 1
 121  *
 122  * 0    4    8    12   16   20   24   28
 123  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 124  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 125  *
 126  * OR0, OR1:
 127  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 128  *    Reserved ORx[17:18] = 11, confusion here?
 129  *    CSNT = ORx[20] = 1
 130  *    ACS = half cycle delay = ORx[21:22] = 11
 131  *    SCY = 6 = ORx[24:27] = 0110
 132  *    TRLX = use relaxed timing = ORx[29] = 1
 133  *    EAD = use external address latch delay = OR[31] = 1
 134  *
 135  * 0    4    8    12   16   20   24   28
 136  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 137  */
 138
 139 #define CFG_FLASH_BASE          0xff000000      /* start of FLASH 8M */
 140
 141 #define CFG_BR0_PRELIM          0xff801001
 142 #define CFG_BR1_PRELIM          0xff001001
 143
 144 #define CFG_OR0_PRELIM          0xff806e65
 145 #define CFG_OR1_PRELIM          0xff806e65
 146
 147 #define CFG_FLASH_BANKS_LIST    {0xff800000, CFG_FLASH_BASE}
 148 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 149 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 150 #undef  CFG_FLASH_CHECKSUM
 151 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 152 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 153
 154 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 155
 156 #define CFG_FLASH_CFI_DRIVER
 157 #define CFG_FLASH_CFI
 158 #define CFG_FLASH_EMPTY_INFO
 159
 160
 161 /*
 162  * SDRAM on the Local Bus
 163  */
 164 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
 165 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 166
 167 /*
 168  * Base Register 2 and Option Register 2 configure SDRAM.
 169  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 170  *
 171  * For BR2, need:
 172  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 173  *    port-size = 32-bits = BR2[19:20] = 11
 174  *    no parity checking = BR2[21:22] = 00
 175  *    SDRAM for MSEL = BR2[24:26] = 011
 176  *    Valid = BR[31] = 1
 177  *
 178  * 0    4    8    12   16   20   24   28
 179  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 180  *
 181  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 182  * FIXME: the top 17 bits of BR2.
 183  */
 184
 185 #define CFG_BR2_PRELIM          0xf0001861
 186
 187 /*
 188  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 189  *
 190  * For OR2, need:
 191  *    64MB mask for AM, OR2[0:7] = 1111 1100
 192  *                 XAM, OR2[17:18] = 11
 193  *    9 columns OR2[19-21] = 010
 194  *    13 rows   OR2[23-25] = 100
 195  *    EAD set for extra time OR[31] = 1
 196  *
 197  * 0    4    8    12   16   20   24   28
 198  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 199  */
 200
 201 #define CFG_OR2_PRELIM          0xfc006901
 202
 203 #define CFG_LBC_LCRR            0x00030004    /* LB clock ratio reg */
 204 #define CFG_LBC_LBCR            0x00000000    /* LB config reg */
 205 #define CFG_LBC_LSRT            0x20000000  /* LB sdram refresh timer */
 206 #define CFG_LBC_MRTPR           0x00000000  /* LB refresh timer prescal*/
 207
 208 /*
 209  * LSDMR masks
 210  */
 211 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 212 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 213 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 214 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 215 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 216 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 217 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 218 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 219 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 220 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 221
 222 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 223 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 224 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 225 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 226 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 227 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 228 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 229 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 230
 231 /*
 232  * Common settings for all Local Bus SDRAM commands.
 233  * At run time, either BSMA1516 (for CPU 1.1)
 234  *                  or BSMA1617 (for CPU 1.0) (old)
 235  * is OR'ed in too.
 236  */
 237 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFCR16          \
 238                                 | CFG_LBC_LSDMR_PRETOACT7       \
 239                                 | CFG_LBC_LSDMR_ACTTORW7        \
 240                                 | CFG_LBC_LSDMR_BL8             \
 241                                 | CFG_LBC_LSDMR_WRC4            \
 242                                 | CFG_LBC_LSDMR_CL3             \
 243                                 | CFG_LBC_LSDMR_RFEN            \
 244                                 )
 245
 246 /*
 247  * The CADMUS registers are connected to CS3 on CDS.
 248  * The new memory map places CADMUS at 0xf8000000.
 249  *
 250  * For BR3, need:
 251  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 252  *    port-size = 8-bits  = BR[19:20] = 01
 253  *    no parity checking  = BR[21:22] = 00
 254  *    GPMC for MSEL       = BR[24:26] = 000
 255  *    Valid               = BR[31]    = 1
 256  *
 257  * 0    4    8    12   16   20   24   28
 258  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 259  *
 260  * For OR3, need:
 261  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 262  *    disable buffer ctrl OR[19]    = 0
 263  *    CSNT                OR[20]    = 1
 264  *    ACS                 OR[21:22] = 11
 265  *    XACS                OR[23]    = 1
 266  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 267  *    SETA                OR[28]    = 0
 268  *    TRLX                OR[29]    = 1
 269  *    EHTR                OR[30]    = 1
 270  *    EAD extra time      OR[31]    = 1
 271  *
 272  * 0    4    8    12   16   20   24   28
 273  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 274  */
 275
 276 #define CADMUS_BASE_ADDR 0xf8000000
 277 #define CFG_BR3_PRELIM   0xf8000801
 278 #define CFG_OR3_PRELIM   0xfff00ff7
 279
 280 #define CONFIG_L1_INIT_RAM
 281 #define CFG_INIT_RAM_LOCK       1
 282 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 283 #define CFG_INIT_RAM_END        0x4000      /* End of used area in RAM */
 284
 285 #define CFG_GBL_DATA_SIZE       128         /* num bytes initial data */
 286 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 287 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 288
 289 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 290 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 291
 292 /* Serial Port */
 293 #define CONFIG_CONS_INDEX     2
 294 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 295 #define CFG_NS16550
 296 #define CFG_NS16550_SERIAL
 297 #define CFG_NS16550_REG_SIZE    1
 298 #define CFG_NS16550_CLK         get_bus_freq(0)
 299
 300 #define CFG_BAUDRATE_TABLE  \
 301         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 302
 303 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 304 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 305
 306 /* Use the HUSH parser */
 307 #define CFG_HUSH_PARSER
 308 #ifdef  CFG_HUSH_PARSER
 309 #define CFG_PROMPT_HUSH_PS2 "> "
 310 #endif
 311
 312 /* pass open firmware flat tree */
 313 #define CONFIG_OF_LIBFDT                1
 314 #define CONFIG_OF_BOARD_SETUP           1
 315 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 316
 317 /*
 318  * I2C
 319  */
 320 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 321 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 322 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 323 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 324 #define CFG_I2C_EEPROM_ADDR     0x57
 325 #define CFG_I2C_SLAVE           0x7F
 326 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 327 #define CFG_I2C_OFFSET          0x3000
 328
 329 /*
 330  * General PCI
 331  * Addresses are mapped 1-1.
 332  */
 333 #define CFG_PCI1_MEM_BASE       0x80000000
 334 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 335 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 336 #define CFG_PCI1_IO_BASE        0x00000000
 337 #define CFG_PCI1_IO_PHYS        0xe2000000
 338 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 339
 340 #define CFG_PCI2_MEM_BASE       0xa0000000
 341 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 342 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 343 #define CFG_PCI2_IO_BASE        0x00000000
 344 #define CFG_PCI2_IO_PHYS        0xe2100000
 345 #define CFG_PCI2_IO_SIZE        0x00100000      /* 1M */
 346
 347 #ifdef CONFIG_LEGACY
 348 #define BRIDGE_ID 17
 349 #define VIA_ID 2
 350 #else
 351 #define BRIDGE_ID 28
 352 #define VIA_ID 4
 353 #endif
 354
 355 #if defined(CONFIG_PCI)
 356
 357 #define CONFIG_NET_MULTI
 358 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 359 #define CONFIG_MPC85XX_PCI2
 360
 361 #undef CONFIG_EEPRO100
 362 #undef CONFIG_TULIP
 363
 364 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 365 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 366
 367 #endif  /* CONFIG_PCI */
 368
 369
 370 #if defined(CONFIG_TSEC_ENET)
 371
 372 #ifndef CONFIG_NET_MULTI
 373 #define CONFIG_NET_MULTI        1
 374 #endif
 375
 376 #define CONFIG_MII              1       /* MII PHY management */
 377 #define CONFIG_TSEC1    1
 378 #define CONFIG_TSEC1_NAME       "TSEC0"
 379 #define CONFIG_TSEC2    1
 380 #define CONFIG_TSEC2_NAME       "TSEC1"
 381 #define TSEC1_PHY_ADDR          0
 382 #define TSEC2_PHY_ADDR          1
 383 #define TSEC1_PHYIDX            0
 384 #define TSEC2_PHYIDX            0
 385 #define TSEC1_FLAGS             TSEC_GIGABIT
 386 #define TSEC2_FLAGS             TSEC_GIGABIT
 387
 388 /* Options are: TSEC[0-1] */
 389 #define CONFIG_ETHPRIME         "TSEC0"
 390
 391 #endif  /* CONFIG_TSEC_ENET */
 392
 393 /*
 394  * Environment
 395  */
 396 #define CFG_ENV_IS_IN_FLASH     1
 397 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 398 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 399 #define CFG_ENV_SIZE            0x2000
 400
 401 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 402 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 403
 404 /*
 405  * BOOTP options
 406  */
 407 #define CONFIG_BOOTP_BOOTFILESIZE
 408 #define CONFIG_BOOTP_BOOTPATH
 409 #define CONFIG_BOOTP_GATEWAY
 410 #define CONFIG_BOOTP_HOSTNAME
 411
 412
 413 /*
 414  * Command line configuration.
 415  */
 416 #include <config_cmd_default.h>
 417
 418 #define CONFIG_CMD_PING
 419 #define CONFIG_CMD_I2C
 420 #define CONFIG_CMD_MII
 421 #define CONFIG_CMD_ELF
 422
 423 #if defined(CONFIG_PCI)
 424     #define CONFIG_CMD_PCI
 425 #endif
 426
 427
 428 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 429
 430 /*
 431  * Miscellaneous configurable options
 432  */
 433 #define CFG_LONGHELP                    /* undef to save memory */
 434 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 435 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 436 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 437 #if defined(CONFIG_CMD_KGDB)
 438 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 439 #else
 440 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 441 #endif
 442 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 443 #define CFG_MAXARGS     16              /* max number of command args */
 444 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 445 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 446
 447 /*
 448  * For booting Linux, the board info and command line data
 449  * have to be in the first 8 MB of memory, since this is
 450  * the maximum mapped by the Linux kernel during initialization.
 451  */
 452 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 453
 454 /*
 455  * Internal Definitions
 456  *
 457  * Boot Flags
 458  */
 459 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 460 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 461
 462 #if defined(CONFIG_CMD_KGDB)
 463 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 464 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 465 #endif
 466
 467 /*
 468  * Environment Configuration
 469  */
 470
 471 /* The mac addresses for all ethernet interface */
 472 #if defined(CONFIG_TSEC_ENET)
 473 #define CONFIG_HAS_ETH0
 474 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 475 #define CONFIG_HAS_ETH1
 476 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 477 #define CONFIG_HAS_ETH2
 478 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 479 #endif
 480
 481 #define CONFIG_IPADDR    192.168.1.253
 482
 483 #define CONFIG_HOSTNAME  unknown
 484 #define CONFIG_ROOTPATH  /nfsroot
 485 #define CONFIG_BOOTFILE  your.uImage
 486
 487 #define CONFIG_SERVERIP  192.168.1.1
 488 #define CONFIG_GATEWAYIP 192.168.1.1
 489 #define CONFIG_NETMASK   255.255.255.0
 490
 491 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 492
 493 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 494 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 495
 496 #define CONFIG_BAUDRATE 115200
 497
 498 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 499    "netdev=eth0\0"                                                      \
 500    "consoledev=ttyS1\0"                                                 \
 501    "ramdiskaddr=600000\0"                                               \
 502    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 503    "fdtaddr=400000\0"                                                   \
 504    "fdtfile=your.fdt.dtb\0"
 505
 506 #define CONFIG_NFSBOOTCOMMAND                                           \
 507    "setenv bootargs root=/dev/nfs rw "                                  \
 508       "nfsroot=$serverip:$rootpath "                                    \
 509       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 510       "console=$consoledev,$baudrate $othbootargs;"                     \
 511    "tftp $loadaddr $bootfile;"                                          \
 512    "tftp $fdtaddr $fdtfile;"                                            \
 513    "bootm $loadaddr - $fdtaddr"
 514
 515 #define CONFIG_RAMBOOTCOMMAND \
 516    "setenv bootargs root=/dev/ram rw "                                  \
 517       "console=$consoledev,$baudrate $othbootargs;"                     \
 518    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 519    "tftp $loadaddr $bootfile;"                                          \
 520    "bootm $loadaddr $ramdiskaddr"
 521
 522 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 523
 524 #endif  /* __CONFIG_H */