include/configs/MPC8560ADS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2004, 2011 Freescale Semiconductor.
   4  * (C) Copyright 2002,2003 Motorola,Inc.
   5  * Xianghua Xiao <X.Xiao@motorola.com>
   6  */
   7
   8 /*
   9  * mpc8560ads board configuration file
  10  *
  11  * Please refer to doc/README.mpc85xx for more info.
  12  *
  13  * Make sure you change the MAC address and other network params first,
  14  * search for CONFIG_SERVERIP, etc. in this file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /* High Level Configuration Options */
  21 #define CONFIG_CPM2             1       /* has CPM2 */
  22
  23 /*
  24  * default CCARBAR is at 0xff700000
  25  * assume U-Boot is less than 0.5MB
  26  */
  27
  28 #define CONFIG_PCI_INDIRECT_BRIDGE
  29 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  30 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  31 #define CONFIG_ENV_OVERWRITE
  32 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  33
  34 /*
  35  * sysclk for MPC85xx
  36  *
  37  * Two valid values are:
  38  *    33000000
  39  *    66000000
  40  *
  41  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  42  * is likely the desired value here, so that is now the default.
  43  * The board, however, can run at 66MHz.  In any event, this value
  44  * must match the settings of some switches.  Details can be found
  45  * in the README.mpc85xxads.
  46  */
  47
  48 #ifndef CONFIG_SYS_CLK_FREQ
  49 #define CONFIG_SYS_CLK_FREQ     33000000
  50 #endif
  51
  52 /*
  53  * These can be toggled for performance analysis, otherwise use default.
  54  */
  55 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  56 #define CONFIG_BTB                      /* toggle branch predition */
  57
  58 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  59
  60 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  61 #define CONFIG_SYS_MEMTEST_END          0x00400000
  62
  63 #define CONFIG_SYS_CCSRBAR              0xe0000000
  64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  65
  66 /* DDR Setup */
  67 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  68 #define CONFIG_DDR_SPD
  69
  70 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  71
  72 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  73 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  74
  75 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  76 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  77
  78 /* I2C addresses of SPD EEPROMs */
  79 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  80
  81 /* These are used when DDR doesn't use SPD.  */
  82 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
  83 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
  84 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
  85 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  86 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  87 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
  88 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
  89 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
  90
  91 /*
  92  * SDRAM on the Local Bus
  93  */
  94 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
  95 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
  96
  97 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
  98 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
  99
 100 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 103 #undef  CONFIG_SYS_FLASH_CHECKSUM
 104 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 105 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 106
 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 108
 109 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 110 #define CONFIG_SYS_RAMBOOT
 111 #else
 112 #undef  CONFIG_SYS_RAMBOOT
 113 #endif
 114
 115 #define CONFIG_SYS_FLASH_EMPTY_INFO
 116
 117 #undef CONFIG_CLOCKS_IN_MHZ
 118
 119 /*
 120  * Local Bus Definitions
 121  */
 122
 123 /*
 124  * Base Register 2 and Option Register 2 configure SDRAM.
 125  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 126  *
 127  * For BR2, need:
 128  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 129  *    port-size = 32-bits = BR2[19:20] = 11
 130  *    no parity checking = BR2[21:22] = 00
 131  *    SDRAM for MSEL = BR2[24:26] = 011
 132  *    Valid = BR[31] = 1
 133  *
 134  * 0    4    8    12   16   20   24   28
 135  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 136  *
 137  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 138  * FIXME: the top 17 bits of BR2.
 139  */
 140
 141 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 142
 143 /*
 144  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 145  *
 146  * For OR2, need:
 147  *    64MB mask for AM, OR2[0:7] = 1111 1100
 148  *                 XAM, OR2[17:18] = 11
 149  *    9 columns OR2[19-21] = 010
 150  *    13 rows   OR2[23-25] = 100
 151  *    EAD set for extra time OR[31] = 1
 152  *
 153  * 0    4    8    12   16   20   24   28
 154  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 155  */
 156
 157 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 158
 159 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 160 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 161 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 162 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 163
 164 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 165                                 | LSDMR_RFCR5           \
 166                                 | LSDMR_PRETOACT3       \
 167                                 | LSDMR_ACTTORW3        \
 168                                 | LSDMR_BL8             \
 169                                 | LSDMR_WRC2            \
 170                                 | LSDMR_CL3             \
 171                                 | LSDMR_RFEN            \
 172                                 )
 173
 174 /*
 175  * SDRAM Controller configuration sequence.
 176  */
 177 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 178 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 179 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 180 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 181 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 182
 183 /*
 184  * 32KB, 8-bit wide for ADS config reg
 185  */
 186 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 187 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 188 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 189
 190 #define CONFIG_SYS_INIT_RAM_LOCK        1
 191 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 192 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 193
 194 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 195 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 196
 197 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 198 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 199
 200 /* Serial Port */
 201 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 202 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 203
 204 #define CONFIG_SYS_BAUDRATE_TABLE  \
 205         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 206
 207 /*
 208  * I2C
 209  */
 210 #define CONFIG_SYS_I2C
 211 #define CONFIG_SYS_I2C_FSL
 212 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 213 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 214 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 215 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 216
 217 /* RapidIO MMU */
 218 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 219 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 220 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 221 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 222
 223 /*
 224  * General PCI
 225  * Memory space is mapped 1-1, but I/O space must start from 0.
 226  */
 227 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 228 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 229 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 230 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 231 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 232 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 233 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 234 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 235
 236 #if defined(CONFIG_PCI)
 237 #undef CONFIG_EEPRO100
 238 #undef CONFIG_TULIP
 239
 240 #if !defined(CONFIG_PCI_PNP)
 241     #define PCI_ENET0_IOADDR    0xe0000000
 242     #define PCI_ENET0_MEMADDR   0xe0000000
 243     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 244 #endif
 245
 246 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 247 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 248
 249 #endif  /* CONFIG_PCI */
 250
 251 #ifdef CONFIG_TSEC_ENET
 252
 253 #define CONFIG_TSEC1    1
 254 #define CONFIG_TSEC1_NAME       "TSEC0"
 255 #define CONFIG_TSEC2    1
 256 #define CONFIG_TSEC2_NAME       "TSEC1"
 257 #define TSEC1_PHY_ADDR          0
 258 #define TSEC2_PHY_ADDR          1
 259 #define TSEC1_PHYIDX            0
 260 #define TSEC2_PHYIDX            0
 261 #define TSEC1_FLAGS             TSEC_GIGABIT
 262 #define TSEC2_FLAGS             TSEC_GIGABIT
 263
 264 /* Options are: TSEC[0-1] */
 265 #define CONFIG_ETHPRIME         "TSEC0"
 266
 267 #endif /* CONFIG_TSEC_ENET */
 268
 269 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 270
 271 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 272 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 273
 274 #if (CONFIG_ETHER_INDEX == 2)
 275   /*
 276    * - Rx-CLK is CLK13
 277    * - Tx-CLK is CLK14
 278    * - Select bus for bd/buffers
 279    * - Full duplex
 280    */
 281   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 282   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 283   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 284   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 285   #define FETH2_RST             0x01
 286 #elif (CONFIG_ETHER_INDEX == 3)
 287   /* need more definitions here for FE3 */
 288   #define FETH3_RST             0x80
 289 #endif                                  /* CONFIG_ETHER_INDEX */
 290
 291 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 292
 293 /*
 294  * GPIO pins used for bit-banged MII communications
 295  */
 296 #define MDIO_PORT       2               /* Port C */
 297 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 298                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 299 #define MDC_DECLARE     MDIO_DECLARE
 300
 301 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 302 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 303 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 304
 305 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 306                         else    iop->pdat &= ~0x00400000
 307
 308 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 309                         else    iop->pdat &= ~0x00200000
 310
 311 #define MIIDELAY        udelay(1)
 312
 313 #endif
 314
 315 /*
 316  * Environment
 317  */
 318
 319 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 320 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 321
 322 /*
 323  * BOOTP options
 324  */
 325 #define CONFIG_BOOTP_BOOTFILESIZE
 326
 327 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 328
 329 /*
 330  * Miscellaneous configurable options
 331  */
 332 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 333
 334 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 335
 336 /*
 337  * For booting Linux, the board info and command line data
 338  * have to be in the first 64 MB of memory, since this is
 339  * the maximum mapped by the Linux kernel during initialization.
 340  */
 341 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 342 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 343
 344 #if defined(CONFIG_CMD_KGDB)
 345 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 346 #endif
 347
 348 /*
 349  * Environment Configuration
 350  */
 351 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 352 #define CONFIG_HAS_ETH0
 353 #define CONFIG_HAS_ETH1
 354 #define CONFIG_HAS_ETH2
 355 #define CONFIG_HAS_ETH3
 356 #endif
 357
 358 #define CONFIG_IPADDR    192.168.1.253
 359
 360 #define CONFIG_HOSTNAME         "unknown"
 361 #define CONFIG_ROOTPATH         "/nfsroot"
 362 #define CONFIG_BOOTFILE         "your.uImage"
 363
 364 #define CONFIG_SERVERIP  192.168.1.1
 365 #define CONFIG_GATEWAYIP 192.168.1.1
 366 #define CONFIG_NETMASK   255.255.255.0
 367
 368 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 369
 370 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 371         "netdev=eth0\0"                                                 \
 372         "consoledev=ttyCPM\0"                                           \
 373         "ramdiskaddr=1000000\0"                                         \
 374         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 375         "fdtaddr=400000\0"                                              \
 376         "fdtfile=mpc8560ads.dtb\0"
 377
 378 #define CONFIG_NFSBOOTCOMMAND                                           \
 379         "setenv bootargs root=/dev/nfs rw "                             \
 380                 "nfsroot=$serverip:$rootpath "                          \
 381                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 382                 "console=$consoledev,$baudrate $othbootargs;"           \
 383         "tftp $loadaddr $bootfile;"                                     \
 384         "tftp $fdtaddr $fdtfile;"                                       \
 385         "bootm $loadaddr - $fdtaddr"
 386
 387 #define CONFIG_RAMBOOTCOMMAND \
 388         "setenv bootargs root=/dev/ram rw "                             \
 389                 "console=$consoledev,$baudrate $othbootargs;"           \
 390         "tftp $ramdiskaddr $ramdiskfile;"                               \
 391         "tftp $loadaddr $bootfile;"                                     \
 392         "tftp $fdtaddr $fdtfile;"                                       \
 393         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 394
 395 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 396
 397 #endif  /* __CONFIG_H */