include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * mpc8560ads board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_CPM2             1       /* has CPM2 */
  42 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  46 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  47 #define CONFIG_ENV_OVERWRITE
  48 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  49 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  50 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  51
  52 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  53 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  54
  55
  56 /*
  57  * sysclk for MPC85xx
  58  *
  59  * Two valid values are:
  60  *    33000000
  61  *    66000000
  62  *
  63  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  64  * is likely the desired value here, so that is now the default.
  65  * The board, however, can run at 66MHz.  In any event, this value
  66  * must match the settings of some switches.  Details can be found
  67  * in the README.mpc85xxads.
  68  */
  69
  70 #ifndef CONFIG_SYS_CLK_FREQ
  71 #define CONFIG_SYS_CLK_FREQ     33000000
  72 #endif
  73
  74
  75 /*
  76  * These can be toggled for performance analysis, otherwise use default.
  77  */
  78 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  79 #define CONFIG_BTB                      /* toggle branch predition */
  80 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  81
  82 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  83
  84 #define CFG_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions */
  85
  86 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  87 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  88 #define CFG_MEMTEST_END         0x00400000
  89
  90
  91 /*
  92  * Base addresses -- Note these are effective addresses where the
  93  * actual resources get mapped (not physical addresses)
  94  */
  95 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  96 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  97 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  98
  99
 100 /*
 101  * DDR Setup
 102  */
 103 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 104 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 105
 106 #if defined(CONFIG_SPD_EEPROM)
 107     /*
 108      * Determine DDR configuration from I2C interface.
 109      */
 110     #define SPD_EEPROM_ADDRESS  0x51            /* DDR DIMM */
 111
 112 #else
 113     /*
 114      * Manually set up DDR parameters
 115      */
 116     #define CFG_SDRAM_SIZE      128             /* DDR is 128MB */
 117     #define CFG_DDR_CS0_BNDS    0x00000007      /* 0-128MB */
 118     #define CFG_DDR_CS0_CONFIG  0x80000002
 119     #define CFG_DDR_TIMING_1    0x37344321
 120     #define CFG_DDR_TIMING_2    0x00000800      /* P9-45,may need tuning */
 121     #define CFG_DDR_CONTROL     0xc2000000      /* unbuffered,no DYN_PWR */
 122     #define CFG_DDR_MODE        0x00000062      /* DLL,normal,seq,4/2.5 */
 123     #define CFG_DDR_INTERVAL    0x05200100      /* autocharge,no open page */
 124 #endif
 125
 126
 127 /*
 128  * SDRAM on the Local Bus
 129  */
 130 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
 131 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 132
 133 #define CFG_FLASH_BASE          0xff000000      /* start of FLASH 16M */
 134 #define CFG_BR0_PRELIM          0xff001801      /* port size 32bit */
 135
 136 #define CFG_OR0_PRELIM          0xff006ff7      /* 16MB Flash */
 137 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 138 #define CFG_MAX_FLASH_SECT      64              /* sectors per device */
 139 #undef  CFG_FLASH_CHECKSUM
 140 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 141 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 142
 143 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 144
 145 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 146 #define CFG_RAMBOOT
 147 #else
 148 #undef  CFG_RAMBOOT
 149 #endif
 150
 151 #define CFG_FLASH_CFI_DRIVER
 152 #define CFG_FLASH_CFI
 153 #define CFG_FLASH_EMPTY_INFO
 154
 155 #undef CONFIG_CLOCKS_IN_MHZ
 156
 157
 158 /*
 159  * Local Bus Definitions
 160  */
 161
 162 /*
 163  * Base Register 2 and Option Register 2 configure SDRAM.
 164  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 165  *
 166  * For BR2, need:
 167  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 168  *    port-size = 32-bits = BR2[19:20] = 11
 169  *    no parity checking = BR2[21:22] = 00
 170  *    SDRAM for MSEL = BR2[24:26] = 011
 171  *    Valid = BR[31] = 1
 172  *
 173  * 0    4    8    12   16   20   24   28
 174  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 175  *
 176  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 177  * FIXME: the top 17 bits of BR2.
 178  */
 179
 180 #define CFG_BR2_PRELIM          0xf0001861
 181
 182 /*
 183  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 184  *
 185  * For OR2, need:
 186  *    64MB mask for AM, OR2[0:7] = 1111 1100
 187  *                 XAM, OR2[17:18] = 11
 188  *    9 columns OR2[19-21] = 010
 189  *    13 rows   OR2[23-25] = 100
 190  *    EAD set for extra time OR[31] = 1
 191  *
 192  * 0    4    8    12   16   20   24   28
 193  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 194  */
 195
 196 #define CFG_OR2_PRELIM          0xfc006901
 197
 198 #define CFG_LBC_LCRR            0x00030004    /* LB clock ratio reg */
 199 #define CFG_LBC_LBCR            0x00000000    /* LB config reg */
 200 #define CFG_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
 201 #define CFG_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
 202
 203 /*
 204  * LSDMR masks
 205  */
 206 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 207 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 208 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 209 #define CFG_LBC_LSDMR_RFCR5     (3 << (31 - 16))
 210 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 211 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
 212 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 213 #define CFG_LBC_LSDMR_ACTTORW3  (3 << (31 - 22))
 214 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 215 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 216 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 217 #define CFG_LBC_LSDMR_WRC2      (2 << (31 - 27))
 218 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 219 #define CFG_LBC_LSDMR_BUFCMD    (1 << (31 - 29))
 220 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 221
 222 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 223 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 224 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 225 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 226 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 227 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 228 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 229 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 230
 231 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_BSMA1516        \
 232                                 | CFG_LBC_LSDMR_RFCR5           \
 233                                 | CFG_LBC_LSDMR_PRETOACT3       \
 234                                 | CFG_LBC_LSDMR_ACTTORW3        \
 235                                 | CFG_LBC_LSDMR_BL8             \
 236                                 | CFG_LBC_LSDMR_WRC2            \
 237                                 | CFG_LBC_LSDMR_CL3             \
 238                                 | CFG_LBC_LSDMR_RFEN            \
 239                                 )
 240
 241 /*
 242  * SDRAM Controller configuration sequence.
 243  */
 244 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 245                                 | CFG_LBC_LSDMR_OP_PCHALL)
 246 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 247                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 248 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 249                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 250 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 251                                 | CFG_LBC_LSDMR_OP_MRW)
 252 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 253                                 | CFG_LBC_LSDMR_OP_NORMAL)
 254
 255
 256 /*
 257  * 32KB, 8-bit wide for ADS config reg
 258  */
 259 #define CFG_BR4_PRELIM          0xf8000801
 260 #define CFG_OR4_PRELIM          0xffffe1f1
 261 #define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
 262
 263 #define CONFIG_L1_INIT_RAM
 264 #define CFG_INIT_RAM_LOCK       1
 265 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 266 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 267
 268 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 269 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 270 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 271
 272 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 273 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 274
 275 /* Serial Port */
 276 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 277 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 278 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 279
 280 #define CONFIG_BAUDRATE         115200
 281
 282 #define CFG_BAUDRATE_TABLE  \
 283         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 284
 285 /* Use the HUSH parser */
 286 #define CFG_HUSH_PARSER
 287 #ifdef  CFG_HUSH_PARSER
 288 #define CFG_PROMPT_HUSH_PS2 "> "
 289 #endif
 290
 291 /* pass open firmware flat tree */
 292 #define CONFIG_OF_FLAT_TREE     1
 293 #define CONFIG_OF_BOARD_SETUP   1
 294
 295 /* maximum size of the flat tree (8K) */
 296 #define OF_FLAT_TREE_MAX_SIZE   8192
 297
 298 #define OF_CPU                  "PowerPC,8560@0"
 299 #define OF_SOC                  "soc8560@e0000000"
 300 #define OF_TBCLK                (bd->bi_busfreq / 8)
 301 #define OF_STDOUT_PATH          "/soc8560@e0000000/serial@4500"
 302
 303 /*
 304  * I2C
 305  */
 306 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 307 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 308 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 309 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 310 #define CFG_I2C_SLAVE           0x7F
 311 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 312 #define CFG_I2C_OFFSET          0x3000
 313
 314 /* RapidIO MMU */
 315 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 316 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 317 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 318
 319 /*
 320  * General PCI
 321  * Memory space is mapped 1-1, but I/O space must start from 0.
 322  */
 323 #define CFG_PCI1_MEM_BASE       0x80000000
 324 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 325 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 326 #define CFG_PCI1_IO_BASE        0x00000000
 327 #define CFG_PCI1_IO_PHYS        0xe2000000
 328 #define CFG_PCI1_IO_SIZE        0x100000        /* 1M */
 329
 330 #if defined(CONFIG_PCI)
 331
 332 #define CONFIG_NET_MULTI
 333 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 334
 335 #undef CONFIG_EEPRO100
 336 #undef CONFIG_TULIP
 337
 338 #if !defined(CONFIG_PCI_PNP)
 339     #define PCI_ENET0_IOADDR    0xe0000000
 340     #define PCI_ENET0_MEMADDR   0xe0000000
 341     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 342 #endif
 343
 344 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 345 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 346
 347 #endif  /* CONFIG_PCI */
 348
 349
 350 #ifdef CONFIG_TSEC_ENET
 351
 352 #ifndef CONFIG_NET_MULTI
 353 #define CONFIG_NET_MULTI        1
 354 #endif
 355
 356 #ifndef CONFIG_MII
 357 #define CONFIG_MII              1       /* MII PHY management */
 358 #endif
 359 #define CONFIG_TSEC1    1
 360 #define CONFIG_TSEC1_NAME       "TSEC0"
 361 #define CONFIG_TSEC2    1
 362 #define CONFIG_TSEC2_NAME       "TSEC1"
 363 #undef CONFIG_MPC85XX_FEC
 364 #define TSEC1_PHY_ADDR          0
 365 #define TSEC2_PHY_ADDR          1
 366 #define TSEC1_PHYIDX            0
 367 #define TSEC2_PHYIDX            0
 368
 369 /* Options are: TSEC[0-1] */
 370 #define CONFIG_ETHPRIME         "TSEC0"
 371
 372 #endif /* CONFIG_TSEC_ENET */
 373
 374 #ifdef CONFIG_ETHER_ON_FCC      /* CPM FCC Ethernet */
 375
 376 #undef  CONFIG_ETHER_NONE       /* define if ether on something else */
 377 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 378
 379 #if (CONFIG_ETHER_INDEX == 2)
 380   /*
 381    * - Rx-CLK is CLK13
 382    * - Tx-CLK is CLK14
 383    * - Select bus for bd/buffers
 384    * - Full duplex
 385    */
 386   #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 387   #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 388   #define CFG_CPMFCR_RAMTYPE    0
 389   #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
 390   #define FETH2_RST             0x01
 391 #elif (CONFIG_ETHER_INDEX == 3)
 392   /* need more definitions here for FE3 */
 393   #define FETH3_RST             0x80
 394 #endif                                  /* CONFIG_ETHER_INDEX */
 395
 396 #ifndef CONFIG_MII
 397 #define CONFIG_MII              1       /* MII PHY management */
 398 #endif
 399
 400 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 401
 402 /*
 403  * GPIO pins used for bit-banged MII communications
 404  */
 405 #define MDIO_PORT       2               /* Port C */
 406 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 407 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 408 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 409
 410 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 411                         else    iop->pdat &= ~0x00400000
 412
 413 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 414                         else    iop->pdat &= ~0x00200000
 415
 416 #define MIIDELAY        udelay(1)
 417
 418 #endif
 419
 420
 421 /*
 422  * Environment
 423  */
 424 #ifndef CFG_RAMBOOT
 425   #define CFG_ENV_IS_IN_FLASH   1
 426   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE + 0x40000)
 427   #define CFG_ENV_SECT_SIZE     0x40000 /* 256K(one sector) for env */
 428   #define CFG_ENV_SIZE          0x2000
 429 #else
 430   #define CFG_NO_FLASH          1       /* Flash is not usable now */
 431   #define CFG_ENV_IS_NOWHERE    1       /* Store ENV in memory only */
 432   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 433   #define CFG_ENV_SIZE          0x2000
 434 #endif
 435
 436 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 437 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 438
 439 /*
 440  * BOOTP options
 441  */
 442 #define CONFIG_BOOTP_BOOTFILESIZE
 443 #define CONFIG_BOOTP_BOOTPATH
 444 #define CONFIG_BOOTP_GATEWAY
 445 #define CONFIG_BOOTP_HOSTNAME
 446
 447
 448 /*
 449  * Command line configuration.
 450  */
 451 #include <config_cmd_default.h>
 452
 453 #define CONFIG_CMD_PING
 454 #define CONFIG_CMD_I2C
 455
 456 #if defined(CONFIG_PCI)
 457     #define CONFIG_CMD_PCI
 458 #endif
 459
 460 #if defined(CONFIG_ETHER_ON_FCC)
 461     #define CONFIG_CMD_MII
 462 #endif
 463
 464 #if defined(CFG_RAMBOOT)
 465     #undef CONFIG_CMD_ENV
 466     #undef CONFIG_CMD_LOADS
 467 #endif
 468
 469
 470 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 471
 472 /*
 473  * Miscellaneous configurable options
 474  */
 475 #define CFG_LONGHELP                    /* undef to save memory */
 476 #define CFG_LOAD_ADDR   0x1000000       /* default load address */
 477 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 478
 479 #if defined(CONFIG_CMD_KGDB)
 480     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 481 #else
 482     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 483 #endif
 484
 485 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 486 #define CFG_MAXARGS     16              /* max number of command args */
 487 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 488 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 489
 490 /*
 491  * For booting Linux, the board info and command line data
 492  * have to be in the first 8 MB of memory, since this is
 493  * the maximum mapped by the Linux kernel during initialization.
 494  */
 495 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 496
 497 /* Cache Configuration */
 498 #define CFG_DCACHE_SIZE         32768
 499 #define CFG_CACHELINE_SIZE      32
 500 #if defined(CONFIG_CMD_KGDB)
 501 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 502 #endif
 503
 504 /*
 505  * Internal Definitions
 506  *
 507  * Boot Flags
 508  */
 509 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 510 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 511
 512 #if defined(CONFIG_CMD_KGDB)
 513 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 514 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 515 #endif
 516
 517
 518 /*
 519  * Environment Configuration
 520  */
 521
 522 /* The mac addresses for all ethernet interface */
 523 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 524 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 525 #define CONFIG_HAS_ETH1
 526 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 527 #define CONFIG_HAS_ETH2
 528 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 529 #endif
 530
 531 #define CONFIG_IPADDR    192.168.1.253
 532
 533 #define CONFIG_HOSTNAME         unknown
 534 #define CONFIG_ROOTPATH         /nfsroot
 535 #define CONFIG_BOOTFILE         your.uImage
 536
 537 #define CONFIG_SERVERIP  192.168.1.1
 538 #define CONFIG_GATEWAYIP 192.168.1.1
 539 #define CONFIG_NETMASK   255.255.255.0
 540
 541 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 542
 543 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 544 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 545
 546 #define CONFIG_BAUDRATE 115200
 547
 548 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 549    "netdev=eth0\0"                                                      \
 550    "consoledev=ttyCPM\0"                                                \
 551    "ramdiskaddr=1000000\0"                                              \
 552    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 553    "fdtaddr=400000\0"                                                   \
 554    "fdtfile=mpc8560ads.dtb\0"
 555
 556 #define CONFIG_NFSBOOTCOMMAND                                           \
 557    "setenv bootargs root=/dev/nfs rw "                                  \
 558       "nfsroot=$serverip:$rootpath "                                    \
 559       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 560       "console=$consoledev,$baudrate $othbootargs;"                     \
 561    "tftp $loadaddr $bootfile;"                                          \
 562    "tftp $fdtaddr $fdtfile;"                                            \
 563    "bootm $loadaddr - $fdtaddr"
 564
 565 #define CONFIG_RAMBOOTCOMMAND \
 566    "setenv bootargs root=/dev/ram rw "                                  \
 567       "console=$consoledev,$baudrate $othbootargs;"                     \
 568    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 569    "tftp $loadaddr $bootfile;"                                          \
 570    "tftp $fdtaddr $fdtfile;"                                            \
 571    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 572
 573 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 574
 575 #endif  /* __CONFIG_H */