include/configs/MPC8568MDS.h

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8568mds board configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_BOOKE            1       /* BOOKE */
  31 #define CONFIG_E500             1       /* BOOKE e500 family */
  32 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/68 */
  33 #define CONFIG_MPC8568          1       /* MPC8568 specific */
  34 #define CONFIG_MPC8568MDS       1       /* MPC8568MDS board specific */
  35
  36 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  37 #define CONFIG_PCI1             1       /* PCI controller */
  38 #define CONFIG_PCIE1            1       /* PCIE controller */
  39 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  40 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  41 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  42 #define CONFIG_QE                       /* Enable QE */
  43 #define CONFIG_ENV_OVERWRITE
  44 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  45 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  46 /*#define CONFIG_DDR_2T_TIMING           Sets the 2T timing bit */
  47
  48 /*#define CONFIG_DDR_ECC*/                      /* only for ECC DDR module */
  49 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/   /* DDR controller or DMA? */
  50 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  51
  52
  53 /*
  54  * When initializing flash, if we cannot find the manufacturer ID,
  55  * assume this is the AMD flash associated with the MDS board.
  56  * This allows booting from a promjet.
  57  */
  58 #define CONFIG_ASSUME_AMD_FLASH
  59
  60 #define MPC85xx_DDR_SDRAM_CLK_CNTL      /* 85xx has clock control reg */
  61
  62 #ifndef __ASSEMBLY__
  63 extern unsigned long get_clock_freq(void);
  64 #endif                                            /*Replace a call to get_clock_freq (after it is implemented)*/
  65 #define CONFIG_SYS_CLK_FREQ     66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
  66
  67 /*
  68  * These can be toggled for performance analysis, otherwise use default.
  69  */
  70 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  71 #define CONFIG_BTB                              /* toggle branch predition */
  72 #define CONFIG_ADDR_STREAMING                   /* toggle addr streaming   */
  73
  74 /*
  75  * Only possible on E500 Version 2 or newer cores.
  76  */
  77 #define CONFIG_ENABLE_36BIT_PHYS        1
  78
  79
  80 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  81
  82 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  83 #define CFG_MEMTEST_START       0x00200000      /* memtest works on */
  84 #define CFG_MEMTEST_END         0x00400000
  85
  86 /*
  87  * Base addresses -- Note these are effective addresses where the
  88  * actual resources get mapped (not physical addresses)
  89  */
  90 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  91 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  92 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  93
  94 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
  95 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
  96
  97 /*
  98  * DDR Setup
  99  */
 100 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 101 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 102
 103 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 104
 105 /*
 106  * Make sure required options are set
 107  */
 108 #ifndef CONFIG_SPD_EEPROM
 109 #error ("CONFIG_SPD_EEPROM is required")
 110 #endif
 111
 112 #undef CONFIG_CLOCKS_IN_MHZ
 113
 114
 115 /*
 116  * Local Bus Definitions
 117  */
 118
 119 /*
 120  * FLASH on the Local Bus
 121  * Two banks, 8M each, using the CFI driver.
 122  * Boot from BR0/OR0 bank at 0xff00_0000
 123  * Alternate BR1/OR1 bank at 0xff80_0000
 124  *
 125  * BR0, BR1:
 126  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 127  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 128  *    Port Size = 16 bits = BRx[19:20] = 10
 129  *    Use GPCM = BRx[24:26] = 000
 130  *    Valid = BRx[31] = 1
 131  *
 132  * 0    4    8    12   16   20   24   28
 133  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 134  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 135  *
 136  * OR0, OR1:
 137  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 138  *    Reserved ORx[17:18] = 11, confusion here?
 139  *    CSNT = ORx[20] = 1
 140  *    ACS = half cycle delay = ORx[21:22] = 11
 141  *    SCY = 6 = ORx[24:27] = 0110
 142  *    TRLX = use relaxed timing = ORx[29] = 1
 143  *    EAD = use external address latch delay = OR[31] = 1
 144  *
 145  * 0    4    8    12   16   20   24   28
 146  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 147  */
 148 #define CFG_BCSR_BASE           0xf8000000
 149
 150 #define CFG_FLASH_BASE          0xfe000000      /* start of FLASH 32M */
 151
 152 /*Chip select 0 - Flash*/
 153 #define CFG_BR0_PRELIM          0xfe001001
 154 #define CFG_OR0_PRELIM          0xfe006ff7
 155
 156 /*Chip slelect 1 - BCSR*/
 157 #define CFG_BR1_PRELIM          0xf8000801
 158 #define CFG_OR1_PRELIM          0xffffe9f7
 159
 160 /*#define CFG_FLASH_BANKS_LIST  {0xff800000, CFG_FLASH_BASE} */
 161 #define CFG_MAX_FLASH_BANKS             1               /* number of banks */
 162 #define CFG_MAX_FLASH_SECT              512             /* sectors per device */
 163 #undef  CFG_FLASH_CHECKSUM
 164 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 165 #define CFG_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
 166
 167 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 168
 169 #define CFG_FLASH_CFI_DRIVER
 170 #define CFG_FLASH_CFI
 171 #define CFG_FLASH_EMPTY_INFO
 172
 173
 174 /*
 175  * SDRAM on the LocalBus
 176  */
 177 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM        */
 178 #define CFG_LBC_SDRAM_SIZE      64                      /* LBC SDRAM is 64MB */
 179
 180
 181 /*Chip select 2 - SDRAM*/
 182 #define CFG_BR2_PRELIM      0xf0001861
 183 #define CFG_OR2_PRELIM          0xfc006901
 184
 185 #define CFG_LBC_LCRR            0x00030004      /* LB clock ratio reg */
 186 #define CFG_LBC_LBCR            0x00000000      /* LB config reg */
 187 #define CFG_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 188 #define CFG_LBC_MRTPR           0x00000000      /* LB refresh timer prescal*/
 189
 190 /*
 191  * LSDMR masks
 192  */
 193 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 194 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 195 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 196 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 197 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 198 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 199 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 200 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 201 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 202 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 203
 204 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 205 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 206 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 207 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 208 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 209 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 210 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 211 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 212
 213 /*
 214  * Common settings for all Local Bus SDRAM commands.
 215  * At run time, either BSMA1516 (for CPU 1.1)
 216  *                  or BSMA1617 (for CPU 1.0) (old)
 217  * is OR'ed in too.
 218  */
 219 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFCR16          \
 220                                 | CFG_LBC_LSDMR_PRETOACT7       \
 221                                 | CFG_LBC_LSDMR_ACTTORW7        \
 222                                 | CFG_LBC_LSDMR_BL8             \
 223                                 | CFG_LBC_LSDMR_WRC4            \
 224                                 | CFG_LBC_LSDMR_CL3             \
 225                                 | CFG_LBC_LSDMR_RFEN            \
 226                                 )
 227
 228 /*
 229  * The bcsr registers are connected to CS3 on MDS.
 230  * The new memory map places bcsr at 0xf8000000.
 231  *
 232  * For BR3, need:
 233  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 234  *    port-size = 8-bits  = BR[19:20] = 01
 235  *    no parity checking  = BR[21:22] = 00
 236  *    GPMC for MSEL       = BR[24:26] = 000
 237  *    Valid               = BR[31]    = 1
 238  *
 239  * 0    4    8    12   16   20   24   28
 240  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 241  *
 242  * For OR3, need:
 243  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 244  *    disable buffer ctrl OR[19]    = 0
 245  *    CSNT                OR[20]    = 1
 246  *    ACS                 OR[21:22] = 11
 247  *    XACS                OR[23]    = 1
 248  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 249  *    SETA                OR[28]    = 0
 250  *    TRLX                OR[29]    = 1
 251  *    EHTR                OR[30]    = 1
 252  *    EAD extra time      OR[31]    = 1
 253  *
 254  * 0    4    8    12   16   20   24   28
 255  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 256  */
 257 #define CFG_BCSR (0xf8000000)
 258
 259 /*Chip slelect 4 - PIB*/
 260 #define CFG_BR4_PRELIM   0xf8008801
 261 #define CFG_OR4_PRELIM   0xffffe9f7
 262
 263 /*Chip select 5 - PIB*/
 264 #define CFG_BR5_PRELIM   0xf8010801
 265 #define CFG_OR5_PRELIM   0xffff69f7
 266
 267 #define CONFIG_L1_INIT_RAM
 268 #define CFG_INIT_RAM_LOCK       1
 269 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 270 #define CFG_INIT_RAM_END        0x4000      /* End of used area in RAM */
 271
 272 #define CFG_GBL_DATA_SIZE       128         /* num bytes initial data */
 273 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 274 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 275
 276 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 277 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 278
 279 /* Serial Port */
 280 #define CONFIG_CONS_INDEX               1
 281 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 282 #define CFG_NS16550
 283 #define CFG_NS16550_SERIAL
 284 #define CFG_NS16550_REG_SIZE    1
 285 #define CFG_NS16550_CLK         get_bus_freq(0)
 286
 287 #define CFG_BAUDRATE_TABLE  \
 288         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 289
 290 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 291 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 292
 293 /* Use the HUSH parser*/
 294 #define CFG_HUSH_PARSER
 295 #ifdef  CFG_HUSH_PARSER
 296 #define CFG_PROMPT_HUSH_PS2 "> "
 297 #endif
 298
 299 /* pass open firmware flat tree */
 300 #define CONFIG_OF_LIBFDT                1
 301 #define CONFIG_OF_BOARD_SETUP           1
 302 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 303
 304 /*
 305  * I2C
 306  */
 307 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 308 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 309 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 310 #define CONFIG_I2C_MULTI_BUS
 311 #define CONFIG_I2C_CMD_TREE
 312 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 313 #define CFG_I2C_EEPROM_ADDR     0x52
 314 #define CFG_I2C_SLAVE           0x7F
 315 #define CFG_I2C_NOPROBES        {{0,0x69}}      /* Don't probe these addrs */
 316 #define CFG_I2C_OFFSET          0x3000
 317 #define CFG_I2C2_OFFSET         0x3100
 318
 319 /*
 320  * General PCI
 321  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 322  */
 323 #define CFG_PCI1_MEM_BASE       0x80000000
 324 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 325 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 326 #define CFG_PCI1_IO_BASE        0x00000000
 327 #define CFG_PCI1_IO_PHYS        0xe2000000
 328 #define CFG_PCI1_IO_SIZE        0x00800000      /* 8M */
 329
 330 #define CFG_PCIE1_MEM_BASE      0xa0000000
 331 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 332 #define CFG_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 333 #define CFG_PCIE1_IO_BASE       0x00000000
 334 #define CFG_PCIE1_IO_PHYS       0xe2800000
 335 #define CFG_PCIE1_IO_SIZE       0x00800000      /* 8M */
 336
 337 #define CFG_SRIO_MEM_BASE       0xc0000000
 338
 339 #ifdef CONFIG_QE
 340 /*
 341  * QE UEC ethernet configuration
 342  */
 343 #define CONFIG_UEC_ETH
 344 #ifndef CONFIG_TSEC_ENET
 345 #define CONFIG_ETHPRIME         "FSL UEC0"
 346 #endif
 347 #define CONFIG_PHY_MODE_NEED_CHANGE
 348 #define CONFIG_eTSEC_MDIO_BUS
 349
 350 #ifdef CONFIG_eTSEC_MDIO_BUS
 351 #define CONFIG_MIIM_ADDRESS     0xE0024520
 352 #endif
 353
 354 #define CONFIG_UEC_ETH1         /* GETH1 */
 355
 356 #ifdef CONFIG_UEC_ETH1
 357 #define CFG_UEC1_UCC_NUM        0       /* UCC1 */
 358 #define CFG_UEC1_RX_CLK         QE_CLK_NONE
 359 #define CFG_UEC1_TX_CLK         QE_CLK16
 360 #define CFG_UEC1_ETH_TYPE       GIGA_ETH
 361 #define CFG_UEC1_PHY_ADDR       7
 362 #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
 363 #endif
 364
 365 #define CONFIG_UEC_ETH2         /* GETH2 */
 366
 367 #ifdef CONFIG_UEC_ETH2
 368 #define CFG_UEC2_UCC_NUM        1       /* UCC2 */
 369 #define CFG_UEC2_RX_CLK         QE_CLK_NONE
 370 #define CFG_UEC2_TX_CLK         QE_CLK16
 371 #define CFG_UEC2_ETH_TYPE       GIGA_ETH
 372 #define CFG_UEC2_PHY_ADDR       1
 373 #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
 374 #endif
 375 #endif /* CONFIG_QE */
 376
 377 #if defined(CONFIG_PCI)
 378
 379 #define CONFIG_NET_MULTI
 380 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 381
 382 #undef CONFIG_EEPRO100
 383 #undef CONFIG_TULIP
 384
 385 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 386 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 387
 388 /* PCI view of System Memory */
 389 #define CFG_PCI_MEMORY_BUS      0x00000000
 390 #define CFG_PCI_MEMORY_PHYS     0x00000000
 391 #define CFG_PCI_MEMORY_SIZE     0x80000000
 392
 393 #endif  /* CONFIG_PCI */
 394
 395 #ifndef CONFIG_NET_MULTI
 396 #define CONFIG_NET_MULTI        1
 397 #endif
 398
 399 #if defined(CONFIG_TSEC_ENET)
 400
 401 #define CONFIG_MII              1       /* MII PHY management */
 402 #define CONFIG_TSEC1    1
 403 #define CONFIG_TSEC1_NAME       "eTSEC0"
 404 #define CONFIG_TSEC2    1
 405 #define CONFIG_TSEC2_NAME       "eTSEC1"
 406
 407 #define TSEC1_PHY_ADDR          2
 408 #define TSEC2_PHY_ADDR          3
 409
 410 #define TSEC1_PHYIDX            0
 411 #define TSEC2_PHYIDX            0
 412
 413 #define TSEC1_FLAGS             TSEC_GIGABIT
 414 #define TSEC2_FLAGS             TSEC_GIGABIT
 415
 416 /* Options are: eTSEC[0-1] */
 417 #define CONFIG_ETHPRIME         "eTSEC0"
 418
 419 #endif  /* CONFIG_TSEC_ENET */
 420
 421 /*
 422  * Environment
 423  */
 424 #define CFG_ENV_IS_IN_FLASH     1
 425 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 426 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 427 #define CFG_ENV_SIZE            0x2000
 428
 429 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 430 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 431
 432
 433 /*
 434  * BOOTP options
 435  */
 436 #define CONFIG_BOOTP_BOOTFILESIZE
 437 #define CONFIG_BOOTP_BOOTPATH
 438 #define CONFIG_BOOTP_GATEWAY
 439 #define CONFIG_BOOTP_HOSTNAME
 440
 441
 442 /*
 443  * Command line configuration.
 444  */
 445 #include <config_cmd_default.h>
 446
 447 #define CONFIG_CMD_PING
 448 #define CONFIG_CMD_I2C
 449 #define CONFIG_CMD_MII
 450 #define CONFIG_CMD_ELF
 451
 452 #if defined(CONFIG_PCI)
 453     #define CONFIG_CMD_PCI
 454 #endif
 455
 456
 457 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 458
 459 /*
 460  * Miscellaneous configurable options
 461  */
 462 #define CFG_LONGHELP                    /* undef to save memory */
 463 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 464 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 465 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 466 #if defined(CONFIG_CMD_KGDB)
 467 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 468 #else
 469 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size */
 470 #endif
 471 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 472 #define CFG_MAXARGS     16              /* max number of command args */
 473 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 474 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 475
 476 /*
 477  * For booting Linux, the board info and command line data
 478  * have to be in the first 8 MB of memory, since this is
 479  * the maximum mapped by the Linux kernel during initialization.
 480  */
 481 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 482
 483 /*
 484  * Internal Definitions
 485  *
 486  * Boot Flags
 487  */
 488 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 489 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 490
 491 #if defined(CONFIG_CMD_KGDB)
 492 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 493 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 494 #endif
 495
 496 /*
 497  * Environment Configuration
 498  */
 499
 500 /* The mac addresses for all ethernet interface */
 501 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
 502 #define CONFIG_HAS_ETH0
 503 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 504 #define CONFIG_HAS_ETH1
 505 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 506 #define CONFIG_HAS_ETH2
 507 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 508 #define CONFIG_HAS_ETH3
 509 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 510 #endif
 511
 512 #define CONFIG_IPADDR    192.168.1.253
 513
 514 #define CONFIG_HOSTNAME  unknown
 515 #define CONFIG_ROOTPATH  /nfsroot
 516 #define CONFIG_BOOTFILE  your.uImage
 517
 518 #define CONFIG_SERVERIP  192.168.1.1
 519 #define CONFIG_GATEWAYIP 192.168.1.1
 520 #define CONFIG_NETMASK   255.255.255.0
 521
 522 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 523
 524 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 525 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 526
 527 #define CONFIG_BAUDRATE 115200
 528
 529 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 530    "netdev=eth0\0"                                                      \
 531    "consoledev=ttyS0\0"                                                 \
 532    "ramdiskaddr=600000\0"                                               \
 533    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 534    "fdtaddr=400000\0"                                                   \
 535    "fdtfile=your.fdt.dtb\0"                                             \
 536    "nfsargs=setenv bootargs root=/dev/nfs rw "                          \
 537       "nfsroot=$serverip:$rootpath "                                    \
 538       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 539       "console=$consoledev,$baudrate $othbootargs\0"                    \
 540    "ramargs=setenv bootargs root=/dev/ram rw "                          \
 541       "console=$consoledev,$baudrate $othbootargs\0"                    \
 542
 543
 544 #define CONFIG_NFSBOOTCOMMAND                                           \
 545    "run nfsargs;"                                                       \
 546    "tftp $loadaddr $bootfile;"                                          \
 547    "tftp $fdtaddr $fdtfile;"                                            \
 548    "bootm $loadaddr - $fdtaddr"
 549
 550
 551 #define CONFIG_RAMBOOTCOMMAND \
 552    "run ramargs;"                                                       \
 553    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 554    "tftp $loadaddr $bootfile;"                                          \
 555    "bootm $loadaddr $ramdiskaddr"
 556
 557 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 558
 559 #endif  /* __CONFIG_H */