include/configs/MPC8569MDS.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8569mds board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_SYS_SRIO
  14 #define CONFIG_SRIO1                    /* SRIO port 1 */
  15
  16 #define CONFIG_PCIE1            1       /* PCIE controller */
  17 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  18 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  19 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  20 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  21 #define CONFIG_QE                       /* Enable QE */
  22 #define CONFIG_ENV_OVERWRITE
  23
  24 #ifndef __ASSEMBLY__
  25 extern unsigned long get_clock_freq(void);
  26 #endif
  27 /* Replace a call to get_clock_freq (after it is implemented)*/
  28 #define CONFIG_SYS_CLK_FREQ     66666666
  29 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  30
  31 #ifdef CONFIG_ATM
  32 #define CONFIG_PQ_MDS_PIB
  33 #define CONFIG_PQ_MDS_PIB_ATM
  34 #endif
  35
  36 /*
  37  * These can be toggled for performance analysis, otherwise use default.
  38  */
  39 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  40 #define CONFIG_BTB                              /* toggle branch predition */
  41
  42 #ifndef CONFIG_SYS_MONITOR_BASE
  43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  44 #endif
  45
  46 /*
  47  * Only possible on E500 Version 2 or newer cores.
  48  */
  49 #define CONFIG_ENABLE_36BIT_PHYS        1
  50
  51 #define CONFIG_HWCONFIG
  52
  53 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  54 #define CONFIG_SYS_MEMTEST_END          0x00400000
  55
  56 /*
  57  * Config the L2 Cache as L2 SRAM
  58  */
  59 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  60 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  61 #define CONFIG_SYS_L2_SIZE              (512 << 10)
  62 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  63
  64 #define CONFIG_SYS_CCSRBAR              0xe0000000
  65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  66
  67 #if defined(CONFIG_NAND_SPL)
  68 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  69 #endif
  70
  71 /* DDR Setup */
  72 #undef CONFIG_FSL_DDR_INTERACTIVE
  73 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  74 #define CONFIG_DDR_SPD
  75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  76
  77 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  78
  79 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  80                                         /* DDR is system memory*/
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82
  83 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  84 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  85
  86 /* I2C addresses of SPD EEPROMs */
  87 #define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
  88
  89 /* These are used when DDR doesn't use SPD.  */
  90 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1024MB */
  91 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
  92 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
  93 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
  94 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
  95 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
  96 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
  97 #define CONFIG_SYS_DDR_SDRAM_CFG        0x47000000
  98 #define CONFIG_SYS_DDR_SDRAM_CFG_2      0x04401040
  99 #define CONFIG_SYS_DDR_SDRAM_MODE       0x40401521
 100 #define CONFIG_SYS_DDR_SDRAM_MODE_2     0x8000C000
 101 #define CONFIG_SYS_DDR_SDRAM_INTERVAL   0x03E00000
 102 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 103 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x01000000
 104 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 105 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 106 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 107 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x0655A604
 108 #define CONFIG_SYS_DDR_CDR_1            0x80040000
 109 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 110 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 111 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 112 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
 113 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 114
 115 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 116 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 117 #define CONFIG_SYS_DDR_SBE              0x00010000
 118
 119 #undef CONFIG_CLOCKS_IN_MHZ
 120
 121 /*
 122  * Local Bus Definitions
 123  */
 124
 125 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 126 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 127
 128 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 129 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 130
 131 /*Chip select 0 - Flash*/
 132 #define CONFIG_FLASH_BR_PRELIM          0xfe000801
 133 #define CONFIG_FLASH_OR_PRELIM          0xfe000ff7
 134
 135 /*Chip select 1 - BCSR*/
 136 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 137 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 138
 139 /*Chip select 4 - PIB*/
 140 #define CONFIG_SYS_BR4_PRELIM           0xf8008801
 141 #define CONFIG_SYS_OR4_PRELIM           0xffffe9f7
 142
 143 /*Chip select 5 - PIB*/
 144 #define CONFIG_SYS_BR5_PRELIM           0xf8010801
 145 #define CONFIG_SYS_OR5_PRELIM           0xffffe9f7
 146
 147 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 148 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 149 #undef  CONFIG_SYS_FLASH_CHECKSUM
 150 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 151 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 152
 153 #undef CONFIG_SYS_RAMBOOT
 154
 155 #define CONFIG_FLASH_CFI_DRIVER
 156 #define CONFIG_SYS_FLASH_CFI
 157 #define CONFIG_SYS_FLASH_EMPTY_INFO
 158
 159 /* Chip select 3 - NAND */
 160 #ifndef CONFIG_NAND_SPL
 161 #define CONFIG_SYS_NAND_BASE            0xFC000000
 162 #else
 163 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 164 #endif
 165
 166 /* NAND boot: 4K NAND loader config */
 167 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 168 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 169 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 170 #define CONFIG_SYS_NAND_U_BOOT_START \
 171         (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 172 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 173 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 174 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 175
 176 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 177 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, }
 178 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 179 #define CONFIG_NAND_FSL_ELBC            1
 180 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 181 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE_PHYS \
 182                                 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
 183                                 | BR_PS_8            /* Port Size = 8 bit */ \
 184                                 | BR_MS_FCM          /* MSEL = FCM */ \
 185                                 | BR_V)              /* valid */
 186 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000          /* length 256K */ \
 187                                 | OR_FCM_CSCT \
 188                                 | OR_FCM_CST \
 189                                 | OR_FCM_CHT \
 190                                 | OR_FCM_SCY_1 \
 191                                 | OR_FCM_TRLX \
 192                                 | OR_FCM_EHTR)
 193
 194 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 195 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 196 #define CONFIG_SYS_BR3_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 197 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 198
 199 #define CONFIG_SYS_LBC_LCRR     0x00000004      /* LB clock ratio reg */
 200 #define CONFIG_SYS_LBC_LBCR     0x00040000      /* LB config reg */
 201 #define CONFIG_SYS_LBC_LSRT     0x20000000      /* LB sdram refresh timer */
 202 #define CONFIG_SYS_LBC_MRTPR    0x00000000      /* LB refresh timer prescal*/
 203
 204 #define CONFIG_SYS_INIT_RAM_LOCK        1
 205 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000  /* Initial RAM address */
 206 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 207
 208 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 209                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 210 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 211
 212 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 213 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 214
 215 /* Serial Port */
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE    1
 218 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 219 #ifdef CONFIG_NAND_SPL
 220 #define CONFIG_NS16550_MIN_FUNCTIONS
 221 #endif
 222
 223 #define CONFIG_SYS_BAUDRATE_TABLE  \
 224         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 225
 226 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 227 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 228
 229 /*
 230  * I2C
 231  */
 232 #define CONFIG_SYS_I2C
 233 #define CONFIG_SYS_I2C_FSL
 234 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 235 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 236 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 237 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 238 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 239 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 240 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 241
 242 /*
 243  * I2C2 EEPROM
 244  */
 245 #define CONFIG_ID_EEPROM
 246 #ifdef CONFIG_ID_EEPROM
 247 #define CONFIG_SYS_I2C_EEPROM_NXID
 248 #endif
 249 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 251 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 252
 253 #define PLPPAR1_I2C_BIT_MASK            0x0000000F
 254 #define PLPPAR1_I2C2_VAL                0x00000000
 255 #define PLPPAR1_ESDHC_VAL               0x0000000A
 256 #define PLPDIR1_I2C_BIT_MASK            0x0000000F
 257 #define PLPDIR1_I2C2_VAL                0x0000000F
 258 #define PLPDIR1_ESDHC_VAL               0x00000006
 259 #define PLPPAR1_UART0_BIT_MASK          0x00000fc0
 260 #define PLPPAR1_ESDHC_4BITS_VAL         0x00000a80
 261 #define PLPDIR1_UART0_BIT_MASK          0x00000fc0
 262 #define PLPDIR1_ESDHC_4BITS_VAL         0x00000a80
 263
 264 /*
 265  * General PCI
 266  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 267  */
 268 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 269 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 270 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 271 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 272 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 273 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 274 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 275 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 276 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 277
 278 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xC0000000
 279 #define CONFIG_SYS_SRIO1_MEM_BUS        0xC0000000
 280 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BUS
 281 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 282
 283 #ifdef CONFIG_QE
 284 /*
 285  * QE UEC ethernet configuration
 286  */
 287 #define CONFIG_SYS_UCC_RGMII_MODE       /* Set UCC work at RGMII by default */
 288 #undef CONFIG_SYS_UCC_RMII_MODE         /* Set UCC work at RMII mode */
 289
 290 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 291 #define CONFIG_UEC_ETH
 292 #define CONFIG_ETHPRIME         "UEC0"
 293 #define CONFIG_PHY_MODE_NEED_CHANGE
 294
 295 #define CONFIG_UEC_ETH1         /* GETH1 */
 296 #define CONFIG_HAS_ETH0
 297
 298 #ifdef CONFIG_UEC_ETH1
 299 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 300 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 301 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 302 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 303 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 304 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 305 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 306 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 307 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 308 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16 /* CLK16 for RMII */
 309 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 310 #define CONFIG_SYS_UEC1_PHY_ADDR       8        /* 0x8 for RMII */
 311 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 312 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 313 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 314 #endif /* CONFIG_UEC_ETH1 */
 315
 316 #define CONFIG_UEC_ETH2         /* GETH2 */
 317 #define CONFIG_HAS_ETH1
 318
 319 #ifdef CONFIG_UEC_ETH2
 320 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 321 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 322 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 323 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 324 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 325 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 326 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 327 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 328 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 329 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16 /* CLK 16 for RMII */
 330 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 331 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9      /* 0x9 for RMII */
 332 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 333 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 334 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 335 #endif /* CONFIG_UEC_ETH2 */
 336
 337 #define CONFIG_UEC_ETH3         /* GETH3 */
 338 #define CONFIG_HAS_ETH2
 339
 340 #ifdef CONFIG_UEC_ETH3
 341 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
 342 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
 343 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 344 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 345 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 346 #define CONFIG_SYS_UEC3_PHY_ADDR       2
 347 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 348 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 349 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 350 #define CONFIG_SYS_UEC3_TX_CLK          QE_CLK16 /* CLK_16 for RMII */
 351 #define CONFIG_SYS_UEC3_ETH_TYPE        FAST_ETH
 352 #define CONFIG_SYS_UEC3_PHY_ADDR        0xA     /* 0xA for RMII */
 353 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 354 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 355 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 356 #endif /* CONFIG_UEC_ETH3 */
 357
 358 #define CONFIG_UEC_ETH4         /* GETH4 */
 359 #define CONFIG_HAS_ETH3
 360
 361 #ifdef CONFIG_UEC_ETH4
 362 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
 363 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
 364 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 365 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 366 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 367 #define CONFIG_SYS_UEC4_PHY_ADDR       3
 368 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 369 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 370 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 371 #define CONFIG_SYS_UEC4_TX_CLK          QE_CLK16 /* CLK16 for RMII */
 372 #define CONFIG_SYS_UEC4_ETH_TYPE        FAST_ETH
 373 #define CONFIG_SYS_UEC4_PHY_ADDR        0xB     /* 0xB for RMII */
 374 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 375 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 376 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 377 #endif /* CONFIG_UEC_ETH4 */
 378
 379 #undef CONFIG_UEC_ETH6         /* GETH6 */
 380 #define CONFIG_HAS_ETH5
 381
 382 #ifdef CONFIG_UEC_ETH6
 383 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
 384 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
 385 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 386 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 387 #define CONFIG_SYS_UEC6_PHY_ADDR       4
 388 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 389 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 390 #endif /* CONFIG_UEC_ETH6 */
 391
 392 #undef CONFIG_UEC_ETH8         /* GETH8 */
 393 #define CONFIG_HAS_ETH7
 394
 395 #ifdef CONFIG_UEC_ETH8
 396 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
 397 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
 398 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 399 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 400 #define CONFIG_SYS_UEC8_PHY_ADDR       6
 401 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 402 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 403 #endif /* CONFIG_UEC_ETH8 */
 404
 405 #endif /* CONFIG_QE */
 406
 407 #if defined(CONFIG_PCI)
 408 #undef CONFIG_EEPRO100
 409 #undef CONFIG_TULIP
 410
 411 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 412
 413 #endif  /* CONFIG_PCI */
 414
 415 /*
 416  * Environment
 417  */
 418 #if defined(CONFIG_SYS_RAMBOOT)
 419 #else
 420 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 421 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 422 #define CONFIG_ENV_SIZE         0x2000
 423 #endif
 424
 425 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 426 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 427
 428 /* QE microcode/firmware address */
 429 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 430 #define CONFIG_SYS_QE_FW_ADDR   0xfff00000
 431
 432 /*
 433  * BOOTP options
 434  */
 435 #define CONFIG_BOOTP_BOOTFILESIZE
 436
 437 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 438
 439 #ifdef CONFIG_MMC
 440 #define CONFIG_FSL_ESDHC
 441 #define CONFIG_FSL_ESDHC_PIN_MUX
 442 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 443 #endif
 444
 445 /*
 446  * Miscellaneous configurable options
 447  */
 448 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 449 #if defined(CONFIG_CMD_KGDB)
 450 #define CONFIG_SYS_CBSIZE       2048            /* Console I/O Buffer Size */
 451 #else
 452 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 453 #endif
 454 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
 455 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 456                                                 /* Boot Argument Buffer Size */
 457
 458 /*
 459  * For booting Linux, the board info and command line data
 460  * have to be in the first 64 MB of memory, since this is
 461  * the maximum mapped by the Linux kernel during initialization.
 462  */
 463 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux*/
 464 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 465
 466 #if defined(CONFIG_CMD_KGDB)
 467 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 468 #endif
 469
 470 /*
 471  * Environment Configuration
 472  */
 473 #define CONFIG_HOSTNAME mpc8569mds
 474 #define CONFIG_ROOTPATH  "/nfsroot"
 475 #define CONFIG_BOOTFILE  "your.uImage"
 476
 477 #define CONFIG_SERVERIP  192.168.1.1
 478 #define CONFIG_GATEWAYIP 192.168.1.1
 479 #define CONFIG_NETMASK   255.255.255.0
 480
 481 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 482
 483 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 484         "netdev=eth0\0"                                                 \
 485         "consoledev=ttyS0\0"                                            \
 486         "ramdiskaddr=600000\0"                                          \
 487         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 488         "fdtaddr=400000\0"                                              \
 489         "fdtfile=your.fdt.dtb\0"                                        \
 490         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 491         "nfsroot=$serverip:$rootpath "                                  \
 492         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 493         "console=$consoledev,$baudrate $othbootargs\0"                  \
 494         "ramargs=setenv bootargs root=/dev/ram rw "                     \
 495         "console=$consoledev,$baudrate $othbootargs\0"                  \
 496
 497 #define CONFIG_NFSBOOTCOMMAND                                           \
 498         "run nfsargs;"                                                  \
 499         "tftp $loadaddr $bootfile;"                                     \
 500         "tftp $fdtaddr $fdtfile;"                                       \
 501         "bootm $loadaddr - $fdtaddr"
 502
 503 #define CONFIG_RAMBOOTCOMMAND                                           \
 504         "run ramargs;"                                                  \
 505         "tftp $ramdiskaddr $ramdiskfile;"                               \
 506         "tftp $loadaddr $bootfile;"                                     \
 507         "bootm $loadaddr $ramdiskaddr"
 508
 509 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 510
 511 #endif  /* __CONFIG_H */