include/configs/MPC8569MDS.h

   1 /*
   2  * Copyright (C) 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8569mds board configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_BOOKE            1       /* BOOKE */
  31 #define CONFIG_E500             1       /* BOOKE e500 family */
  32 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/68 */
  33 #define CONFIG_MPC8569          1       /* MPC8569 specific */
  34 #define CONFIG_MPC8569MDS       1       /* MPC8569MDS board specific */
  35
  36 #define CONFIG_FSL_ELBC         1       /* Has Enhance localbus controller */
  37
  38 #define CONFIG_PCI              1       /* Disable PCI/PCIE */
  39 #define CONFIG_PCIE1            1       /* PCIE controller */
  40 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  41 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  42 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  43 #define CONFIG_QE                       /* Enable QE */
  44 #define CONFIG_ENV_OVERWRITE
  45 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  46
  47 /*
  48  * When initializing flash, if we cannot find the manufacturer ID,
  49  * assume this is the AMD flash associated with the MDS board.
  50  * This allows booting from a promjet.
  51  */
  52 #define CONFIG_ASSUME_AMD_FLASH
  53
  54 #ifndef __ASSEMBLY__
  55 extern unsigned long get_clock_freq(void);
  56 #endif
  57 /* Replace a call to get_clock_freq (after it is implemented)*/
  58 #define CONFIG_SYS_CLK_FREQ     66666666
  59 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  60
  61 /*
  62  * These can be toggled for performance analysis, otherwise use default.
  63  */
  64 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  65 #define CONFIG_BTB                              /* toggle branch predition */
  66
  67 /*
  68  * Only possible on E500 Version 2 or newer cores.
  69  */
  70 #define CONFIG_ENABLE_36BIT_PHYS        1
  71
  72 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  73 #define CONFIG_HWCONFIG
  74
  75 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  76 #define CONFIG_SYS_MEMTEST_END          0x00400000
  77
  78 /*
  79  * Base addresses -- Note these are effective addresses where the
  80  * actual resources get mapped (not physical addresses)
  81  */
  82 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  83 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  84 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  85                                                 /* physical addr of CCSRBAR */
  86 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
  87                                                 /* PQII uses CONFIG_SYS_IMMR */
  88
  89 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
  90 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
  91
  92 /* DDR Setup */
  93 #define CONFIG_FSL_DDR3
  94 #undef CONFIG_FSL_DDR_INTERACTIVE
  95 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  96 #define CONFIG_DDR_SPD
  97 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  99
 100 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 101
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 103                                         /* DDR is system memory*/
 104 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 105
 106 #define CONFIG_NUM_DDR_CONTROLLERS      1
 107 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 108 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 109
 110 /* I2C addresses of SPD EEPROMs */
 111 #define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
 112 #define SPD_EEPROM_ADDRESS2    0x52    /* CTLR 1 DIMM 0 */
 113
 114 /* These are used when DDR doesn't use SPD.  */
 115 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1024MB */
 116 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 117 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 118 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 119 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 120 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
 121 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
 122 #define CONFIG_SYS_DDR_SDRAM_CFG        0x47000000
 123 #define CONFIG_SYS_DDR_SDRAM_CFG_2      0x04401040
 124 #define CONFIG_SYS_DDR_SDRAM_MODE       0x40401521
 125 #define CONFIG_SYS_DDR_SDRAM_MODE_2     0x8000C000
 126 #define CONFIG_SYS_DDR_SDRAM_INTERVAL   0x03E00000
 127 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 128 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x01000000
 129 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 130 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 131 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 132 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x0655A604
 133 #define CONFIG_SYS_DDR_CDR_1            0x80040000
 134 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 135 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 136 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 137 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
 138 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 139
 140 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 141 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 142 #define CONFIG_SYS_DDR_SBE              0x00010000
 143
 144 #undef CONFIG_CLOCKS_IN_MHZ
 145
 146 /*
 147  * Local Bus Definitions
 148  */
 149
 150 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 151 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 152
 153 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 154 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 155
 156 /*Chip select 0 - Flash*/
 157 #define CONFIG_SYS_BR0_PRELIM           0xfe000801
 158 #define CONFIG_SYS_OR0_PRELIM           0xfe000ff7
 159
 160 /*Chip select 1 - BCSR*/
 161 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 162 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 163
 164 /*Chip select 4 - PIB*/
 165 #define CONFIG_SYS_BR4_PRELIM           0xf8008801
 166 #define CONFIG_SYS_OR4_PRELIM           0xffffe9f7
 167
 168 /*Chip select 5 - PIB*/
 169 #define CONFIG_SYS_BR5_PRELIM           0xf8010801
 170 #define CONFIG_SYS_OR5_PRELIM           0xffffe9f7
 171
 172 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 173 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 174 #undef  CONFIG_SYS_FLASH_CHECKSUM
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177
 178 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 179
 180 #define CONFIG_FLASH_CFI_DRIVER
 181 #define CONFIG_SYS_FLASH_CFI
 182 #define CONFIG_SYS_FLASH_EMPTY_INFO
 183
 184
 185 /*
 186  * SDRAM on the LocalBus
 187  */
 188 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM        */
 189 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 190
 191 #define CONFIG_SYS_LBC_LCRR     0x00000004      /* LB clock ratio reg */
 192 #define CONFIG_SYS_LBC_LBCR     0x00040000      /* LB config reg */
 193 #define CONFIG_SYS_LBC_LSRT     0x20000000      /* LB sdram refresh timer */
 194 #define CONFIG_SYS_LBC_MRTPR    0x00000000      /* LB refresh timer prescal*/
 195
 196 #define CONFIG_SYS_INIT_RAM_LOCK        1
 197 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000  /* Initial RAM address */
 198 #define CONFIG_SYS_INIT_RAM_END 0x4000      /* End of used area in RAM */
 199
 200 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 201 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 202                         (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 203 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 204
 205 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 206 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 207
 208 /* Serial Port */
 209 #define CONFIG_CONS_INDEX               1
 210 #define CONFIG_SERIAL_MULTI             1
 211 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 212 #define CONFIG_SYS_NS16550
 213 #define CONFIG_SYS_NS16550_SERIAL
 214 #define CONFIG_SYS_NS16550_REG_SIZE    1
 215 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 216
 217 #define CONFIG_SYS_BAUDRATE_TABLE  \
 218         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 219
 220 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 221 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 222
 223 /* Use the HUSH parser*/
 224 #define CONFIG_SYS_HUSH_PARSER
 225 #ifdef  CONFIG_SYS_HUSH_PARSER
 226 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 227 #endif
 228
 229 /* pass open firmware flat tree */
 230 #define CONFIG_OF_LIBFDT                1
 231 #define CONFIG_OF_BOARD_SETUP           1
 232 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 233
 234 #define CONFIG_SYS_64BIT_VSPRINTF       1
 235 #define CONFIG_SYS_64BIT_STRTOUL        1
 236
 237 /*
 238  * I2C
 239  */
 240 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 241 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 242 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 243 #define CONFIG_I2C_MULTI_BUS
 244 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 245 #define CONFIG_SYS_I2C_SLAVE    0x7F
 246 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 247 #define CONFIG_SYS_I2C_OFFSET   0x3000
 248 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 249
 250 /*
 251  * I2C2 EEPROM
 252  */
 253 #define CONFIG_ID_EEPROM
 254 #ifdef CONFIG_ID_EEPROM
 255 #define CONFIG_SYS_I2C_EEPROM_NXID
 256 #endif
 257 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 259 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 260
 261 #define PLPPAR1_I2C_BIT_MASK            0x0000000F
 262 #define PLPPAR1_I2C2_VAL                0x00000000
 263 #define PLPPAR1_ESDHC_VAL               0x0000000A
 264 #define PLPDIR1_I2C_BIT_MASK            0x0000000F
 265 #define PLPDIR1_I2C2_VAL                0x0000000F
 266 #define PLPDIR1_ESDHC_VAL               0x00000006
 267
 268 /*
 269  * General PCI
 270  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 271  */
 272 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 273 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 274 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 275 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 276 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 277 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 278 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 279 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 280
 281 #define CONFIG_SYS_SRIO_MEM_VIRT        0xc0000000
 282 #define CONFIG_SYS_SRIO_MEM_BUS         0xc0000000
 283 #define CONFIG_SYS_SRIO_MEM_PHYS        0xc0000000
 284
 285 #ifdef CONFIG_QE
 286 /*
 287  * QE UEC ethernet configuration
 288  */
 289 #define CONFIG_SYS_UCC_RGMII_MODE       /* Set UCC work at RGMII by default */
 290 #undef CONFIG_SYS_UCC_RMII_MODE         /* Set UCC work at RMII mode */
 291
 292 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 293 #define CONFIG_UEC_ETH
 294 #define CONFIG_ETHPRIME         "FSL UEC0"
 295 #define CONFIG_PHY_MODE_NEED_CHANGE
 296
 297 #define CONFIG_UEC_ETH1         /* GETH1 */
 298 #define CONFIG_HAS_ETH0
 299
 300 #ifdef CONFIG_UEC_ETH1
 301 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 302 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 303 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 304 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 305 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 306 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 307 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
 308 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 309 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16 /* CLK16 for RMII */
 310 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 311 #define CONFIG_SYS_UEC1_PHY_ADDR       8        /* 0x8 for RMII */
 312 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 313 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 314 #endif /* CONFIG_UEC_ETH1 */
 315
 316 #define CONFIG_UEC_ETH2         /* GETH2 */
 317 #define CONFIG_HAS_ETH1
 318
 319 #ifdef CONFIG_UEC_ETH2
 320 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 321 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 322 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 323 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 324 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 325 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 326 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 327 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 328 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16 /* CLK 16 for RMII */
 329 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 330 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9      /* 0x9 for RMII */
 331 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
 332 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 333 #endif /* CONFIG_UEC_ETH2 */
 334
 335 #define CONFIG_UEC_ETH3         /* GETH3 */
 336 #define CONFIG_HAS_ETH2
 337
 338 #ifdef CONFIG_UEC_ETH3
 339 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
 340 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
 341 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 342 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 343 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 344 #define CONFIG_SYS_UEC3_PHY_ADDR       2
 345 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
 346 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 347 #define CONFIG_SYS_UEC3_TX_CLK          QE_CLK16 /* CLK_16 for RMII */
 348 #define CONFIG_SYS_UEC3_ETH_TYPE        FAST_ETH
 349 #define CONFIG_SYS_UEC3_PHY_ADDR        0xA     /* 0xA for RMII */
 350 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
 351 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 352 #endif /* CONFIG_UEC_ETH3 */
 353
 354 #define CONFIG_UEC_ETH4         /* GETH4 */
 355 #define CONFIG_HAS_ETH3
 356
 357 #ifdef CONFIG_UEC_ETH4
 358 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
 359 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
 360 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 361 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 362 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 363 #define CONFIG_SYS_UEC4_PHY_ADDR       3
 364 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
 365 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 366 #define CONFIG_SYS_UEC4_TX_CLK          QE_CLK16 /* CLK16 for RMII */
 367 #define CONFIG_SYS_UEC4_ETH_TYPE        FAST_ETH
 368 #define CONFIG_SYS_UEC4_PHY_ADDR        0xB     /* 0xB for RMII */
 369 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
 370 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 371 #endif /* CONFIG_UEC_ETH4 */
 372
 373 #undef CONFIG_UEC_ETH6         /* GETH6 */
 374 #define CONFIG_HAS_ETH5
 375
 376 #ifdef CONFIG_UEC_ETH6
 377 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
 378 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
 379 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 380 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 381 #define CONFIG_SYS_UEC6_PHY_ADDR       4
 382 #define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
 383 #endif /* CONFIG_UEC_ETH6 */
 384
 385 #undef CONFIG_UEC_ETH8         /* GETH8 */
 386 #define CONFIG_HAS_ETH7
 387
 388 #ifdef CONFIG_UEC_ETH8
 389 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
 390 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
 391 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 392 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 393 #define CONFIG_SYS_UEC8_PHY_ADDR       6
 394 #define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
 395 #endif /* CONFIG_UEC_ETH8 */
 396
 397 #endif /* CONFIG_QE */
 398
 399 #if defined(CONFIG_PCI)
 400
 401 #define CONFIG_NET_MULTI
 402 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 403
 404 #undef CONFIG_EEPRO100
 405 #undef CONFIG_TULIP
 406
 407 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 408
 409 #endif  /* CONFIG_PCI */
 410
 411 #ifndef CONFIG_NET_MULTI
 412 #define CONFIG_NET_MULTI        1
 413 #endif
 414
 415 /*
 416  * Environment
 417  */
 418 #define CONFIG_ENV_IS_IN_FLASH  1
 419 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 420 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 256K(one sector) for env */
 421 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 422
 423 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 424 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 425
 426 /* QE microcode/firmware address */
 427 #define CONFIG_SYS_QE_FW_ADDR   0xfff00000
 428
 429 /*
 430  * BOOTP options
 431  */
 432 #define CONFIG_BOOTP_BOOTFILESIZE
 433 #define CONFIG_BOOTP_BOOTPATH
 434 #define CONFIG_BOOTP_GATEWAY
 435 #define CONFIG_BOOTP_HOSTNAME
 436
 437
 438 /*
 439  * Command line configuration.
 440  */
 441 #include <config_cmd_default.h>
 442
 443 #define CONFIG_CMD_PING
 444 #define CONFIG_CMD_I2C
 445 #define CONFIG_CMD_MII
 446 #define CONFIG_CMD_ELF
 447 #define CONFIG_CMD_IRQ
 448 #define CONFIG_CMD_SETEXPR
 449
 450 #if defined(CONFIG_PCI)
 451     #define CONFIG_CMD_PCI
 452 #endif
 453
 454
 455 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 456
 457 #define CONFIG_MMC     1
 458
 459 #ifdef CONFIG_MMC
 460 #define CONFIG_FSL_ESDHC
 461 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 462 #define CONFIG_CMD_MMC
 463 #define CONFIG_GENERIC_MMC
 464 #define CONFIG_CMD_EXT2
 465 #define CONFIG_CMD_FAT
 466 #define CONFIG_DOS_PARTITION
 467 #endif
 468
 469 /*
 470  * Miscellaneous configurable options
 471  */
 472 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 473 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 474 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 475 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 476 #if defined(CONFIG_CMD_KGDB)
 477 #define CONFIG_SYS_CBSIZE       2048            /* Console I/O Buffer Size */
 478 #else
 479 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 480 #endif
 481 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 482                                                 /* Print Buffer Size */
 483 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
 484 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 485                                                 /* Boot Argument Buffer Size */
 486 #define CONFIG_SYS_HZ   1000            /* decrementer freq: 1ms ticks */
 487
 488 /*
 489  * For booting Linux, the board info and command line data
 490  * have to be in the first 16 MB of memory, since this is
 491  * the maximum mapped by the Linux kernel during initialization.
 492  */
 493 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)
 494                                         /* Initial Memory map for Linux*/
 495
 496 /*
 497  * Internal Definitions
 498  *
 499  * Boot Flags
 500  */
 501 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 502 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 503
 504 #if defined(CONFIG_CMD_KGDB)
 505 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 506 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 507 #endif
 508
 509 /*
 510  * Environment Configuration
 511  */
 512 #define CONFIG_HOSTNAME mpc8569mds
 513 #define CONFIG_ROOTPATH  /nfsroot
 514 #define CONFIG_BOOTFILE  your.uImage
 515
 516 #define CONFIG_SERVERIP  192.168.1.1
 517 #define CONFIG_GATEWAYIP 192.168.1.1
 518 #define CONFIG_NETMASK   255.255.255.0
 519
 520 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 521
 522 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 523 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 524
 525 #define CONFIG_BAUDRATE 115200
 526
 527 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 528         "netdev=eth0\0"                                                 \
 529         "consoledev=ttyS0\0"                                            \
 530         "ramdiskaddr=600000\0"                                          \
 531         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 532         "fdtaddr=400000\0"                                              \
 533         "fdtfile=your.fdt.dtb\0"                                        \
 534         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 535         "nfsroot=$serverip:$rootpath "                                  \
 536         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 537         "console=$consoledev,$baudrate $othbootargs\0"                  \
 538         "ramargs=setenv bootargs root=/dev/ram rw "                     \
 539         "console=$consoledev,$baudrate $othbootargs\0"                  \
 540
 541 #define CONFIG_NFSBOOTCOMMAND                                           \
 542         "run nfsargs;"                                                  \
 543         "tftp $loadaddr $bootfile;"                                     \
 544         "tftp $fdtaddr $fdtfile;"                                       \
 545         "bootm $loadaddr - $fdtaddr"
 546
 547 #define CONFIG_RAMBOOTCOMMAND                                           \
 548         "run ramargs;"                                                  \
 549         "tftp $ramdiskaddr $ramdiskfile;"                               \
 550         "tftp $loadaddr $bootfile;"                                     \
 551         "bootm $loadaddr $ramdiskaddr"
 552
 553 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 554
 555 #endif  /* __CONFIG_H */