include/configs/MPC8572DS.h

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8572ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8572          1
  35 #define CONFIG_MPC8572DS        1
  36 #define CONFIG_MP               1       /* support multiple processors */
  37 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  38
  39 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  40 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  41 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  42 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  44 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  45 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  46
  47 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  48
  49 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  50 #define CONFIG_ENV_OVERWRITE
  51
  52 /*
  53  * When initializing flash, if we cannot find the manufacturer ID,
  54  * assume this is the AMD flash associated with the CDS board.
  55  * This allows booting from a promjet.
  56  */
  57 #define CONFIG_ASSUME_AMD_FLASH
  58
  59 #ifndef __ASSEMBLY__
  60 extern unsigned long get_board_sys_clk(unsigned long dummy);
  61 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  62 #endif
  63 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  64 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  65 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  66 #define CONFIG_GET_CLK_FROM_ICS307        /* decode sysclk and ddrclk freq
  67                                              from ICS307 instead of switches */
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74
  75 #define CONFIG_ENABLE_36BIT_PHYS        1
  76
  77 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  78 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  79 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  80
  81 /*
  82  * Base addresses -- Note these are effective addresses where the
  83  * actual resources get mapped (not physical addresses)
  84  */
  85 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  86 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  88 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  89
  90 #define CONFIG_SYS_PCIE3_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
  91 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
  92 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
  93
  94 /* DDR Setup */
  95 #define CONFIG_FSL_DDR2
  96 #undef CONFIG_FSL_DDR_INTERACTIVE
  97 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  98 #define CONFIG_DDR_SPD
  99 #undef CONFIG_DDR_DLL
 100
 101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 102 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 103
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 106
 107 #define CONFIG_NUM_DDR_CONTROLLERS      2
 108 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 109 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 110
 111 /* I2C addresses of SPD EEPROMs */
 112 #define CONFIG_SYS_SPD_BUS_NUM          1       /* SPD EEPROMS locate on I2C bus 1 */
 113 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 114 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 1 DIMM 0 */
 115
 116 /* These are used when DDR doesn't use SPD.  */
 117 #define CONFIG_SYS_SDRAM_SIZE           512             /* DDR is 512MB */
 118 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000001F
 119 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 120 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 121 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 122 #define CONFIG_SYS_DDR_TIMING_1         0x626b2634
 123 #define CONFIG_SYS_DDR_TIMING_2         0x062874cf
 124 #define CONFIG_SYS_DDR_MODE_1           0x00440462
 125 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 126 #define CONFIG_SYS_DDR_INTERVAL         0x0c300100
 127 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 128 #define CONFIG_SYS_DDR_CLK_CTRL         0x00800000
 129 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 130 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 131 #define CONFIG_SYS_DDR_CONTROL          0xc3000008      /* Type = DDR2 */
 132 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 133
 134 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 135 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 136 #define CONFIG_SYS_DDR_SBE              0x00010000
 137
 138 /*
 139  * Make sure required options are set
 140  */
 141 #ifndef CONFIG_SPD_EEPROM
 142 #error ("CONFIG_SPD_EEPROM is required")
 143 #endif
 144
 145 #undef CONFIG_CLOCKS_IN_MHZ
 146
 147 /*
 148  * Memory map
 149  *
 150  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 151  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 152  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 153  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 154  *
 155  * Localbus cacheable (TBD)
 156  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 157  *
 158  * Localbus non-cacheable
 159  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 160  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 161  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 162  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 163  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 164  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 165  */
 166
 167 /*
 168  * Local Bus Definitions
 169  */
 170 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 171
 172 #define CONFIG_SYS_BR0_PRELIM           0xe8001001
 173 #define CONFIG_SYS_OR0_PRELIM           0xf8000ff7
 174
 175 #define CONFIG_SYS_BR1_PRELIM           0xe0001001
 176 #define CONFIG_SYS_OR1_PRELIM           0xf8000ff7
 177
 178 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
 179 #define CONFIG_SYS_FLASH_QUIET_TEST
 180 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 181
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 184 #undef  CONFIG_SYS_FLASH_CHECKSUM
 185 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 186 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 187
 188 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 189
 190 #define CONFIG_FLASH_CFI_DRIVER
 191 #define CONFIG_SYS_FLASH_CFI
 192 #define CONFIG_SYS_FLASH_EMPTY_INFO
 193 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 194
 195 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 196
 197 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 198 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 199
 200 #define CONFIG_SYS_BR3_PRELIM   (PIXIS_BASE | 0x0801)   /* port size 8bit */
 201 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 202
 203 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 204 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 205 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 206 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 207 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 208 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 209 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 210 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 211 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 212 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 213 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 214 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 215 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 216 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 217 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 218 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 219 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 220 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 221 #define PIXIS_VSYSCLK0          0x1C    /* VELA SYSCLK0 Register */
 222 #define PIXIS_VSYSCLK1          0x1D    /* VELA SYSCLK1 Register */
 223 #define PIXIS_VSYSCLK2          0x1E    /* VELA SYSCLK2 Register */
 224 #define PIXIS_VDDRCLK0          0x1F    /* VELA DDRCLK0 Register */
 225 #define PIXIS_VDDRCLK1          0x20    /* VELA DDRCLK1 Register */
 226 #define PIXIS_VDDRCLK2          0x21    /* VELA DDRCLK2 Register */
 227 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 228 #define PIXIS_LED               0x25    /* LED Register */
 229
 230 /* old pixis referenced names */
 231 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 232 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 233 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xc0
 234 #define PIXIS_VSPEED2_TSEC1SER  0x8
 235 #define PIXIS_VSPEED2_TSEC2SER  0x4
 236 #define PIXIS_VSPEED2_TSEC3SER  0x2
 237 #define PIXIS_VSPEED2_TSEC4SER  0x1
 238 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 239 #define PIXIS_VCFGEN1_TSEC2SER  0x20
 240 #define PIXIS_VCFGEN1_TSEC3SER  0x20
 241 #define PIXIS_VCFGEN1_TSEC4SER  0x20
 242 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER \
 243                                         | PIXIS_VSPEED2_TSEC2SER \
 244                                         | PIXIS_VSPEED2_TSEC3SER \
 245                                         | PIXIS_VSPEED2_TSEC4SER)
 246 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER \
 247                                         | PIXIS_VCFGEN1_TSEC2SER \
 248                                         | PIXIS_VCFGEN1_TSEC3SER \
 249                                         | PIXIS_VCFGEN1_TSEC4SER)
 250
 251 #define CONFIG_SYS_INIT_RAM_LOCK        1
 252 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 253 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 254
 255 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 256 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 257 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 258
 259 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 260 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 261
 262 #define CONFIG_SYS_NAND_BASE            0xffa00000
 263 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 264 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 265                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 266                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 267                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 268 #define CONFIG_SYS_MAX_NAND_DEVICE    4
 269 #define NAND_MAX_CHIPS          1
 270 #define CONFIG_MTD_NAND_VERIFY_WRITE
 271 #define CONFIG_CMD_NAND         1
 272 #define CONFIG_NAND_FSL_ELBC    1
 273 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 274
 275 /* NAND flash config */
 276 #define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
 277                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 278                                | BR_PS_8               /* Port Size = 8 bit */ \
 279                                | BR_MS_FCM             /* MSEL = FCM */ \
 280                                | BR_V)                 /* valid */
 281 #define CONFIG_NAND_OR_PRELIM  (0xFFFC0000            /* length 256K */ \
 282                                | OR_FCM_PGS            /* Large Page*/ \
 283                                | OR_FCM_CSCT \
 284                                | OR_FCM_CST \
 285                                | OR_FCM_CHT \
 286                                | OR_FCM_SCY_1 \
 287                                | OR_FCM_TRLX \
 288                                | OR_FCM_EHTR)
 289
 290 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 291 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 292
 293 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
 294                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 295                                | BR_PS_8               /* Port Size = 8 bit */ \
 296                                | BR_MS_FCM             /* MSEL = FCM */ \
 297                                | BR_V)                 /* valid */
 298 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
 299 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
 300                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 301                                | BR_PS_8               /* Port Size = 8 bit */ \
 302                                | BR_MS_FCM             /* MSEL = FCM */ \
 303                                | BR_V)                 /* valid */
 304 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
 305
 306 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
 307                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 308                                | BR_PS_8               /* Port Size = 8 bit */ \
 309                                | BR_MS_FCM             /* MSEL = FCM */ \
 310                                | BR_V)                 /* valid */
 311 #define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
 312
 313
 314 /* Serial Port - controlled on board with jumper J8
 315  * open - index 2
 316  * shorted - index 1
 317  */
 318 #define CONFIG_CONS_INDEX       1
 319 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 320 #define CONFIG_SYS_NS16550
 321 #define CONFIG_SYS_NS16550_SERIAL
 322 #define CONFIG_SYS_NS16550_REG_SIZE     1
 323 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 324
 325 #define CONFIG_SYS_BAUDRATE_TABLE       \
 326         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 327
 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 330
 331 /* Use the HUSH parser */
 332 #define CONFIG_SYS_HUSH_PARSER
 333 #ifdef  CONFIG_SYS_HUSH_PARSER
 334 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 335 #endif
 336
 337 /*
 338  * Pass open firmware flat tree
 339  */
 340 #define CONFIG_OF_LIBFDT                1
 341 #define CONFIG_OF_BOARD_SETUP           1
 342 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 343
 344 #define CONFIG_SYS_64BIT_VSPRINTF       1
 345 #define CONFIG_SYS_64BIT_STRTOUL        1
 346
 347 /* new uImage format support */
 348 #define CONFIG_FIT              1
 349 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 350
 351 /* I2C */
 352 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 353 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 354 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 355 #define CONFIG_I2C_MULTI_BUS
 356 #define CONFIG_I2C_CMD_TREE
 357 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 358 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 359 #define CONFIG_SYS_I2C_SLAVE            0x7F
 360 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
 361 #define CONFIG_SYS_I2C_OFFSET           0x3000
 362 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 363
 364 /*
 365  * I2C2 EEPROM
 366  */
 367 #define CONFIG_ID_EEPROM
 368 #ifdef CONFIG_ID_EEPROM
 369 #define CONFIG_SYS_I2C_EEPROM_NXID
 370 #endif
 371 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 372 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 373 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 374
 375 /*
 376  * General PCI
 377  * Memory space is mapped 1-1, but I/O space must start from 0.
 378  */
 379
 380 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 381 #define CONFIG_SYS_PCIE3_MEM_BASE       0x80000000
 382 #define CONFIG_SYS_PCIE3_MEM_PHYS       CONFIG_SYS_PCIE3_MEM_BASE
 383 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 384 #define CONFIG_SYS_PCIE3_IO_BASE        0x00000000
 385 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 386 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 387
 388 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 389 #define CONFIG_SYS_PCIE2_MEM_BASE       0xa0000000
 390 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BASE
 391 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 392 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 393 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 394 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 395
 396 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 397 #define CONFIG_SYS_PCIE1_MEM_BASE       0xc0000000
 398 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 399 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 400 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 401 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 402 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 403
 404 #if defined(CONFIG_PCI)
 405
 406 /*PCIE video card used*/
 407 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_PHYS
 408
 409 /* video */
 410 #define CONFIG_VIDEO
 411
 412 #if defined(CONFIG_VIDEO)
 413 #define CONFIG_BIOSEMU
 414 #define CONFIG_CFB_CONSOLE
 415 #define CONFIG_VIDEO_SW_CURSOR
 416 #define CONFIG_VGA_AS_SINGLE_DEVICE
 417 #define CONFIG_ATI_RADEON_FB
 418 #define CONFIG_VIDEO_LOGO
 419 /*#define CONFIG_CONSOLE_CURSOR*/
 420 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 421 #endif
 422
 423 #define CONFIG_NET_MULTI
 424 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 425
 426 #undef CONFIG_EEPRO100
 427 #undef CONFIG_TULIP
 428 #undef CONFIG_RTL8139
 429
 430 #ifdef CONFIG_RTL8139
 431 /* This macro is used by RTL8139 but not defined in PPC architecture */
 432 #define KSEG1ADDR(x)            (x)
 433 #define _IO_BASE        0x00000000
 434 #endif
 435
 436 #ifndef CONFIG_PCI_PNP
 437         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BASE
 438         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BASE
 439         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 440 #endif
 441
 442 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 443 #define CONFIG_DOS_PARTITION
 444 #define CONFIG_SCSI_AHCI
 445
 446 #ifdef CONFIG_SCSI_AHCI
 447 #define CONFIG_SATA_ULI5288
 448 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 449 #define CONFIG_SYS_SCSI_MAX_LUN 1
 450 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 451 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 452 #endif /* SCSI */
 453
 454 #endif  /* CONFIG_PCI */
 455
 456
 457 #if defined(CONFIG_TSEC_ENET)
 458
 459 #ifndef CONFIG_NET_MULTI
 460 #define CONFIG_NET_MULTI        1
 461 #endif
 462
 463 #define CONFIG_MII              1       /* MII PHY management */
 464 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 465 #define CONFIG_TSEC1    1
 466 #define CONFIG_TSEC1_NAME       "eTSEC1"
 467 #define CONFIG_TSEC2    1
 468 #define CONFIG_TSEC2_NAME       "eTSEC2"
 469 #define CONFIG_TSEC3    1
 470 #define CONFIG_TSEC3_NAME       "eTSEC3"
 471 #define CONFIG_TSEC4    1
 472 #define CONFIG_TSEC4_NAME       "eTSEC4"
 473
 474 #define CONFIG_PIXIS_SGMII_CMD
 475 #define CONFIG_FSL_SGMII_RISER  1
 476 #define SGMII_RISER_PHY_OFFSET  0x1c
 477
 478 #ifdef CONFIG_FSL_SGMII_RISER
 479 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 480 #endif
 481
 482 #define TSEC1_PHY_ADDR          0
 483 #define TSEC2_PHY_ADDR          1
 484 #define TSEC3_PHY_ADDR          2
 485 #define TSEC4_PHY_ADDR          3
 486
 487 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 488 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 489 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 490 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 491
 492 #define TSEC1_PHYIDX            0
 493 #define TSEC2_PHYIDX            0
 494 #define TSEC3_PHYIDX            0
 495 #define TSEC4_PHYIDX            0
 496
 497 #define CONFIG_ETHPRIME         "eTSEC1"
 498
 499 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 500 #endif  /* CONFIG_TSEC_ENET */
 501
 502 /*
 503  * Environment
 504  */
 505 #define CONFIG_ENV_IS_IN_FLASH  1
 506 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 507 #define CONFIG_ENV_ADDR         0xfff80000
 508 #else
 509 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 510 #endif
 511 #define CONFIG_ENV_SIZE         0x2000
 512 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 513
 514 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 515 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 516
 517 /*
 518  * Command line configuration.
 519  */
 520 #include <config_cmd_default.h>
 521
 522 #define CONFIG_CMD_IRQ
 523 #define CONFIG_CMD_PING
 524 #define CONFIG_CMD_I2C
 525 #define CONFIG_CMD_MII
 526 #define CONFIG_CMD_ELF
 527 #define CONFIG_CMD_IRQ
 528 #define CONFIG_CMD_SETEXPR
 529
 530 #if defined(CONFIG_PCI)
 531 #define CONFIG_CMD_PCI
 532 #define CONFIG_CMD_BEDBUG
 533 #define CONFIG_CMD_NET
 534 #define CONFIG_CMD_SCSI
 535 #define CONFIG_CMD_EXT2
 536 #endif
 537
 538 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 539
 540 /*
 541  * Miscellaneous configurable options
 542  */
 543 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 544 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 545 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 546 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 547 #if defined(CONFIG_CMD_KGDB)
 548 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 549 #else
 550 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 551 #endif
 552 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 553 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 554 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 555 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 556
 557 /*
 558  * For booting Linux, the board info and command line data
 559  * have to be in the first 8 MB of memory, since this is
 560  * the maximum mapped by the Linux kernel during initialization.
 561  */
 562 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 563
 564 /*
 565  * Internal Definitions
 566  *
 567  * Boot Flags
 568  */
 569 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 570 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 571
 572 #if defined(CONFIG_CMD_KGDB)
 573 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 574 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 575 #endif
 576
 577 /*
 578  * Environment Configuration
 579  */
 580
 581 /* The mac addresses for all ethernet interface */
 582 #if defined(CONFIG_TSEC_ENET)
 583 #define CONFIG_HAS_ETH0
 584 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 585 #define CONFIG_HAS_ETH1
 586 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 587 #define CONFIG_HAS_ETH2
 588 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 589 #define CONFIG_HAS_ETH3
 590 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 591 #endif
 592
 593 #define CONFIG_IPADDR           192.168.1.254
 594
 595 #define CONFIG_HOSTNAME         unknown
 596 #define CONFIG_ROOTPATH         /opt/nfsroot
 597 #define CONFIG_BOOTFILE         uImage
 598 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 599
 600 #define CONFIG_SERVERIP         192.168.1.1
 601 #define CONFIG_GATEWAYIP        192.168.1.1
 602 #define CONFIG_NETMASK          255.255.255.0
 603
 604 /* default location for tftp and bootm */
 605 #define CONFIG_LOADADDR         1000000
 606
 607 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 608 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 609
 610 #define CONFIG_BAUDRATE 115200
 611
 612 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 613  "memctl_intlv_ctl=2\0"                                         \
 614  "netdev=eth0\0"                                                \
 615  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 616  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 617         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 618         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 619         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 620         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 621         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 622  "consoledev=ttyS0\0"                           \
 623  "ramdiskaddr=2000000\0"                        \
 624  "ramdiskfile=8572ds/ramdisk.uboot\0"           \
 625  "fdtaddr=c00000\0"                             \
 626  "fdtfile=8572ds/mpc8572ds.dtb\0"               \
 627  "bdev=sda3\0"
 628
 629 #define CONFIG_HDBOOT                           \
 630  "setenv bootargs root=/dev/$bdev rw "          \
 631  "console=$consoledev,$baudrate $othbootargs;"  \
 632  "tftp $loadaddr $bootfile;"                    \
 633  "tftp $fdtaddr $fdtfile;"                      \
 634  "bootm $loadaddr - $fdtaddr"
 635
 636 #define CONFIG_NFSBOOTCOMMAND           \
 637  "setenv bootargs root=/dev/nfs rw "    \
 638  "nfsroot=$serverip:$rootpath "         \
 639  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 640  "console=$consoledev,$baudrate $othbootargs;"  \
 641  "tftp $loadaddr $bootfile;"            \
 642  "tftp $fdtaddr $fdtfile;"              \
 643  "bootm $loadaddr - $fdtaddr"
 644
 645 #define CONFIG_RAMBOOTCOMMAND           \
 646  "setenv bootargs root=/dev/ram rw "    \
 647  "console=$consoledev,$baudrate $othbootargs;"  \
 648  "tftp $ramdiskaddr $ramdiskfile;"      \
 649  "tftp $loadaddr $bootfile;"            \
 650  "tftp $fdtaddr $fdtfile;"              \
 651  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 652
 653 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 654
 655 #endif  /* __CONFIG_H */