include/configs/MPC8572DS.h

   1 /*
   2  * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8572ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include "../board/freescale/common/ics307_clk.h"
  15
  16 #ifndef CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  18 #endif
  19
  20 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  22 #endif
  23
  24 #ifndef CONFIG_SYS_MONITOR_BASE
  25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  26 #endif
  27
  28 /* High Level Configuration Options */
  29 #define CONFIG_MP               1       /* support multiple processors */
  30
  31 #define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
  32 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
  33 #define CONFIG_PCIE3            1       /* PCIE controller 3 (ULI bridge) */
  34 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  35 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  36 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  37 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  38
  39 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  40 #define CONFIG_ENV_OVERWRITE
  41
  42 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  43 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
  44 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  45
  46 /*
  47  * These can be toggled for performance analysis, otherwise use default.
  48  */
  49 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  50 #define CONFIG_BTB                      /* toggle branch predition */
  51
  52 #define CONFIG_ENABLE_36BIT_PHYS        1
  53
  54 #ifdef CONFIG_PHYS_64BIT
  55 #define CONFIG_ADDR_MAP                 1
  56 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  57 #endif
  58
  59 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  60 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  61
  62 /*
  63  * Config the L2 Cache as L2 SRAM
  64  */
  65 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  66 #ifdef CONFIG_PHYS_64BIT
  67 #define CONFIG_SYS_INIT_L2_ADDR_PHYS            0xff8f80000ull
  68 #else
  69 #define CONFIG_SYS_INIT_L2_ADDR_PHYS            CONFIG_SYS_INIT_L2_ADDR
  70 #endif
  71 #define CONFIG_SYS_L2_SIZE              (512 << 10)
  72 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  73
  74 #define CONFIG_SYS_CCSRBAR              0xffe00000
  75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  76
  77 #if defined(CONFIG_NAND_SPL)
  78 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  79 #endif
  80
  81 /* DDR Setup */
  82 #define CONFIG_VERY_BIG_RAM
  83 #undef CONFIG_FSL_DDR_INTERACTIVE
  84 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  85 #define CONFIG_DDR_SPD
  86
  87 #define CONFIG_DDR_ECC
  88 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  89 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  90
  91 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  92 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  93
  94 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  95 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  96
  97 /* I2C addresses of SPD EEPROMs */
  98 #define CONFIG_SYS_SPD_BUS_NUM          1       /* SPD EEPROMS locate on I2C bus 1 */
  99 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 100 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 1 DIMM 0 */
 101
 102 /* These are used when DDR doesn't use SPD.  */
 103 #define CONFIG_SYS_SDRAM_SIZE           512             /* DDR is 512MB */
 104 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000001F
 105 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 106 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 107 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 108 #define CONFIG_SYS_DDR_TIMING_1         0x626b2634
 109 #define CONFIG_SYS_DDR_TIMING_2         0x062874cf
 110 #define CONFIG_SYS_DDR_MODE_1           0x00440462
 111 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 112 #define CONFIG_SYS_DDR_INTERVAL         0x0c300100
 113 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 114 #define CONFIG_SYS_DDR_CLK_CTRL         0x00800000
 115 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 116 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 117 #define CONFIG_SYS_DDR_CONTROL          0xc3000008      /* Type = DDR2 */
 118 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 119
 120 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 121 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 122 #define CONFIG_SYS_DDR_SBE              0x00010000
 123
 124 /*
 125  * Make sure required options are set
 126  */
 127 #ifndef CONFIG_SPD_EEPROM
 128 #error ("CONFIG_SPD_EEPROM is required")
 129 #endif
 130
 131 #undef CONFIG_CLOCKS_IN_MHZ
 132
 133 /*
 134  * Memory map
 135  *
 136  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 137  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 138  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 139  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 140  *
 141  * Localbus cacheable (TBD)
 142  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 143  *
 144  * Localbus non-cacheable
 145  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 146  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 147  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 148  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 149  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 150  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 151  */
 152
 153 /*
 154  * Local Bus Definitions
 155  */
 156 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 157 #ifdef CONFIG_PHYS_64BIT
 158 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 159 #else
 160 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 161 #endif
 162
 163 #define CONFIG_FLASH_BR_PRELIM \
 164         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 165 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
 166
 167 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 168 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 169
 170 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 171 #define CONFIG_SYS_FLASH_QUIET_TEST
 172 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 173
 174 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 175 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 176 #undef  CONFIG_SYS_FLASH_CHECKSUM
 177 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 178 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 179
 180 #undef CONFIG_SYS_RAMBOOT
 181
 182 #define CONFIG_FLASH_CFI_DRIVER
 183 #define CONFIG_SYS_FLASH_CFI
 184 #define CONFIG_SYS_FLASH_EMPTY_INFO
 185 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 186
 187 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 188
 189 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 190 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 191 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 192 #ifdef CONFIG_PHYS_64BIT
 193 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 194 #else
 195 #define PIXIS_BASE_PHYS PIXIS_BASE
 196 #endif
 197
 198 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 199 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 200
 201 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 202 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 203 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 204 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 205 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 206 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 207 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 208 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 209 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 210 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 211 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 212 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 213 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 214 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 215 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 216 #define PIXIS_VBOOT_LBMAP       0xc0    /* VBOOT - CFG_LBMAP */
 217 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 218 #define PIXIS_VBOOT_LBMAP_PJET  0x01    /* cfg_lbmap - boot from projet */
 219 #define PIXIS_VBOOT_LBMAP_NAND  0x02    /* cfg_lbmap - boot from NAND */
 220 #define PIXIS_VBOOT_LBMAP_NOR1  0x03    /* cfg_lbmap - boot from NOR 1 */
 221 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 222 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 223 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 224 #define PIXIS_VSYSCLK0          0x1C    /* VELA SYSCLK0 Register */
 225 #define PIXIS_VSYSCLK1          0x1D    /* VELA SYSCLK1 Register */
 226 #define PIXIS_VSYSCLK2          0x1E    /* VELA SYSCLK2 Register */
 227 #define PIXIS_VDDRCLK0          0x1F    /* VELA DDRCLK0 Register */
 228 #define PIXIS_VDDRCLK1          0x20    /* VELA DDRCLK1 Register */
 229 #define PIXIS_VDDRCLK2          0x21    /* VELA DDRCLK2 Register */
 230 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 231 #define PIXIS_LED               0x25    /* LED Register */
 232
 233 #define PIXIS_SPD_SYSCLK_MASK           0x7             /* SYSCLK option */
 234
 235 /* old pixis referenced names */
 236 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 237 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 238 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xc0
 239 #define PIXIS_VSPEED2_TSEC1SER  0x8
 240 #define PIXIS_VSPEED2_TSEC2SER  0x4
 241 #define PIXIS_VSPEED2_TSEC3SER  0x2
 242 #define PIXIS_VSPEED2_TSEC4SER  0x1
 243 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 244 #define PIXIS_VCFGEN1_TSEC2SER  0x20
 245 #define PIXIS_VCFGEN1_TSEC3SER  0x20
 246 #define PIXIS_VCFGEN1_TSEC4SER  0x20
 247 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER \
 248                                         | PIXIS_VSPEED2_TSEC2SER \
 249                                         | PIXIS_VSPEED2_TSEC3SER \
 250                                         | PIXIS_VSPEED2_TSEC4SER)
 251 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER \
 252                                         | PIXIS_VCFGEN1_TSEC2SER \
 253                                         | PIXIS_VCFGEN1_TSEC3SER \
 254                                         | PIXIS_VCFGEN1_TSEC4SER)
 255
 256 #define CONFIG_SYS_INIT_RAM_LOCK        1
 257 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 258 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 259
 260 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 261 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 262
 263 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 264 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 265
 266 #ifndef CONFIG_NAND_SPL
 267 #define CONFIG_SYS_NAND_BASE            0xffa00000
 268 #ifdef CONFIG_PHYS_64BIT
 269 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 270 #else
 271 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 272 #endif
 273 #else
 274 #define CONFIG_SYS_NAND_BASE            0xfff00000
 275 #ifdef CONFIG_PHYS_64BIT
 276 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 277 #else
 278 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 279 #endif
 280 #endif
 281
 282 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 283                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 284                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 285                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 286 #define CONFIG_SYS_MAX_NAND_DEVICE    4
 287 #define CONFIG_NAND_FSL_ELBC    1
 288 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 289 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
 290 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
 291
 292 /* NAND boot: 4K NAND loader config */
 293 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 294 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 295 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 296 #define CONFIG_SYS_NAND_U_BOOT_START \
 297                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 298 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 299 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 300 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 301
 302 /* NAND flash config */
 303 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 304                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 305                                | BR_PS_8               /* Port Size = 8 bit */ \
 306                                | BR_MS_FCM             /* MSEL = FCM */ \
 307                                | BR_V)                 /* valid */
 308 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 309                                | OR_FCM_PGS            /* Large Page*/ \
 310                                | OR_FCM_CSCT \
 311                                | OR_FCM_CST \
 312                                | OR_FCM_CHT \
 313                                | OR_FCM_SCY_1 \
 314                                | OR_FCM_TRLX \
 315                                | OR_FCM_EHTR)
 316
 317 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 318 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 319 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 320 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 321 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 322                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 323                                | BR_PS_8               /* Port Size = 8 bit */ \
 324                                | BR_MS_FCM             /* MSEL = FCM */ \
 325                                | BR_V)                 /* valid */
 326 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 327 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
 328                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 329                                | BR_PS_8               /* Port Size = 8 bit */ \
 330                                | BR_MS_FCM             /* MSEL = FCM */ \
 331                                | BR_V)                 /* valid */
 332 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 333
 334 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
 335                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 336                                | BR_PS_8               /* Port Size = 8 bit */ \
 337                                | BR_MS_FCM             /* MSEL = FCM */ \
 338                                | BR_V)                 /* valid */
 339 #define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 340
 341 /* Serial Port - controlled on board with jumper J8
 342  * open - index 2
 343  * shorted - index 1
 344  */
 345 #define CONFIG_CONS_INDEX       1
 346 #define CONFIG_SYS_NS16550_SERIAL
 347 #define CONFIG_SYS_NS16550_REG_SIZE     1
 348 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 349 #ifdef CONFIG_NAND_SPL
 350 #define CONFIG_NS16550_MIN_FUNCTIONS
 351 #endif
 352
 353 #define CONFIG_SYS_BAUDRATE_TABLE       \
 354         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 355
 356 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 357 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 358
 359 /* I2C */
 360 #define CONFIG_SYS_I2C
 361 #define CONFIG_SYS_I2C_FSL
 362 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 363 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 364 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 365 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 366 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 367 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 368 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 369 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 370
 371 /*
 372  * I2C2 EEPROM
 373  */
 374 #define CONFIG_ID_EEPROM
 375 #ifdef CONFIG_ID_EEPROM
 376 #define CONFIG_SYS_I2C_EEPROM_NXID
 377 #endif
 378 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 379 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 380 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 381
 382 /*
 383  * General PCI
 384  * Memory space is mapped 1-1, but I/O space must start from 0.
 385  */
 386
 387 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 388 #define CONFIG_SYS_PCIE3_NAME           "ULI"
 389 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 390 #ifdef CONFIG_PHYS_64BIT
 391 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 392 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 393 #else
 394 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 395 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 396 #endif
 397 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 398 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 399 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 400 #ifdef CONFIG_PHYS_64BIT
 401 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 402 #else
 403 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 404 #endif
 405 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 406
 407 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 408 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 409 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 410 #ifdef CONFIG_PHYS_64BIT
 411 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 412 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 413 #else
 414 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 415 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 416 #endif
 417 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 418 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 419 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 420 #ifdef CONFIG_PHYS_64BIT
 421 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 422 #else
 423 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 424 #endif
 425 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 426
 427 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 428 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 429 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 430 #ifdef CONFIG_PHYS_64BIT
 431 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 432 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 433 #else
 434 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 435 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 436 #endif
 437 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 438 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 439 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 440 #ifdef CONFIG_PHYS_64BIT
 441 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 442 #else
 443 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 444 #endif
 445 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 446
 447 #if defined(CONFIG_PCI)
 448
 449 /*PCIE video card used*/
 450 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 451
 452 /* video */
 453
 454 #if defined(CONFIG_VIDEO)
 455 #define CONFIG_BIOSEMU
 456 #define CONFIG_ATI_RADEON_FB
 457 #define CONFIG_VIDEO_LOGO
 458 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 459 #endif
 460
 461 #undef CONFIG_EEPRO100
 462 #undef CONFIG_TULIP
 463
 464 #ifndef CONFIG_PCI_PNP
 465         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
 466         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
 467         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 468 #endif
 469
 470 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 471
 472 #ifdef CONFIG_SCSI_AHCI
 473 #define CONFIG_SATA_ULI5288
 474 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 475 #define CONFIG_SYS_SCSI_MAX_LUN 1
 476 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 477 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 478 #endif /* SCSI */
 479
 480 #endif  /* CONFIG_PCI */
 481
 482 #if defined(CONFIG_TSEC_ENET)
 483
 484 #define CONFIG_MII              1       /* MII PHY management */
 485 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 486 #define CONFIG_TSEC1    1
 487 #define CONFIG_TSEC1_NAME       "eTSEC1"
 488 #define CONFIG_TSEC2    1
 489 #define CONFIG_TSEC2_NAME       "eTSEC2"
 490 #define CONFIG_TSEC3    1
 491 #define CONFIG_TSEC3_NAME       "eTSEC3"
 492 #define CONFIG_TSEC4    1
 493 #define CONFIG_TSEC4_NAME       "eTSEC4"
 494
 495 #define CONFIG_PIXIS_SGMII_CMD
 496 #define CONFIG_FSL_SGMII_RISER  1
 497 #define SGMII_RISER_PHY_OFFSET  0x1c
 498
 499 #ifdef CONFIG_FSL_SGMII_RISER
 500 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 501 #endif
 502
 503 #define TSEC1_PHY_ADDR          0
 504 #define TSEC2_PHY_ADDR          1
 505 #define TSEC3_PHY_ADDR          2
 506 #define TSEC4_PHY_ADDR          3
 507
 508 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 509 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 510 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 511 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 512
 513 #define TSEC1_PHYIDX            0
 514 #define TSEC2_PHYIDX            0
 515 #define TSEC3_PHYIDX            0
 516 #define TSEC4_PHYIDX            0
 517
 518 #define CONFIG_ETHPRIME         "eTSEC1"
 519 #endif  /* CONFIG_TSEC_ENET */
 520
 521 /*
 522  * Environment
 523  */
 524
 525 #if defined(CONFIG_SYS_RAMBOOT)
 526
 527 #else
 528         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 529         #define CONFIG_ENV_ADDR 0xfff80000
 530         #else
 531         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 532         #endif
 533         #define CONFIG_ENV_SIZE 0x2000
 534         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 535 #endif
 536
 537 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 538 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 539
 540 /*
 541  * USB
 542  */
 543
 544 #ifdef CONFIG_USB_EHCI_HCD
 545 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 546 #define CONFIG_PCI_EHCI_DEVICE                  0
 547 #endif
 548
 549 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 550
 551 /*
 552  * Miscellaneous configurable options
 553  */
 554 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 555 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 556 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 557 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 558
 559 /*
 560  * For booting Linux, the board info and command line data
 561  * have to be in the first 64 MB of memory, since this is
 562  * the maximum mapped by the Linux kernel during initialization.
 563  */
 564 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 565 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 566
 567 #if defined(CONFIG_CMD_KGDB)
 568 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 569 #endif
 570
 571 /*
 572  * Environment Configuration
 573  */
 574 #if defined(CONFIG_TSEC_ENET)
 575 #define CONFIG_HAS_ETH0
 576 #define CONFIG_HAS_ETH1
 577 #define CONFIG_HAS_ETH2
 578 #define CONFIG_HAS_ETH3
 579 #endif
 580
 581 #define CONFIG_IPADDR           192.168.1.254
 582
 583 #define CONFIG_HOSTNAME         unknown
 584 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 585 #define CONFIG_BOOTFILE         "uImage"
 586 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 587
 588 #define CONFIG_SERVERIP         192.168.1.1
 589 #define CONFIG_GATEWAYIP        192.168.1.1
 590 #define CONFIG_NETMASK          255.255.255.0
 591
 592 /* default location for tftp and bootm */
 593 #define CONFIG_LOADADDR         1000000
 594
 595 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 596 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0"         \
 597 "netdev=eth0\0"                                         \
 598 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 599 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 600         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 601                 " +$filesize; " \
 602         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 603                 " +$filesize; " \
 604         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 605                 " $filesize; "  \
 606         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 607                 " +$filesize; " \
 608         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 609                 " $filesize\0"  \
 610 "consoledev=ttyS0\0"                            \
 611 "ramdiskaddr=2000000\0"                 \
 612 "ramdiskfile=8572ds/ramdisk.uboot\0"            \
 613 "fdtaddr=1e00000\0"                             \
 614 "fdtfile=8572ds/mpc8572ds.dtb\0"                \
 615 "bdev=sda3\0"
 616
 617 #define CONFIG_HDBOOT                           \
 618  "setenv bootargs root=/dev/$bdev rw "          \
 619  "console=$consoledev,$baudrate $othbootargs;"  \
 620  "tftp $loadaddr $bootfile;"                    \
 621  "tftp $fdtaddr $fdtfile;"                      \
 622  "bootm $loadaddr - $fdtaddr"
 623
 624 #define CONFIG_NFSBOOTCOMMAND           \
 625  "setenv bootargs root=/dev/nfs rw "    \
 626  "nfsroot=$serverip:$rootpath "         \
 627  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 628  "console=$consoledev,$baudrate $othbootargs;"  \
 629  "tftp $loadaddr $bootfile;"            \
 630  "tftp $fdtaddr $fdtfile;"              \
 631  "bootm $loadaddr - $fdtaddr"
 632
 633 #define CONFIG_RAMBOOTCOMMAND           \
 634  "setenv bootargs root=/dev/ram rw "    \
 635  "console=$consoledev,$baudrate $othbootargs;"  \
 636  "tftp $ramdiskaddr $ramdiskfile;"      \
 637  "tftp $loadaddr $bootfile;"            \
 638  "tftp $fdtaddr $fdtfile;"              \
 639  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 640
 641 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 642
 643 #endif  /* __CONFIG_H */