include/configs/MPC8572DS.h

   1 /*
   2  * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8572ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_36BIT
  33 #define CONFIG_PHYS_64BIT
  34 #endif
  35
  36 #ifdef CONFIG_NAND
  37 #define CONFIG_NAND_U_BOOT
  38 #define CONFIG_RAMBOOT_NAND
  39 #ifdef CONFIG_NAND_SPL
  40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  42 #else
  43 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  44 #define CONFIG_SYS_TEXT_BASE    0xf8f82000
  45 #endif /* CONFIG_NAND_SPL */
  46 #endif
  47
  48 #ifndef CONFIG_SYS_TEXT_BASE
  49 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  50 #endif
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #ifndef CONFIG_SYS_MONITOR_BASE
  57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  58 #endif
  59
  60 /* High Level Configuration Options */
  61 #define CONFIG_BOOKE            1       /* BOOKE */
  62 #define CONFIG_E500             1       /* BOOKE e500 family */
  63 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  64 #define CONFIG_MPC8572          1
  65 #define CONFIG_MPC8572DS        1
  66 #define CONFIG_MP               1       /* support multiple processors */
  67
  68 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  69 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  70 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  71 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  72 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  73 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  74 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  75 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  76 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  77
  78 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  79
  80 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  81 #define CONFIG_ENV_OVERWRITE
  82
  83 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  84 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
  85 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  86
  87 /*
  88  * These can be toggled for performance analysis, otherwise use default.
  89  */
  90 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  91 #define CONFIG_BTB                      /* toggle branch predition */
  92
  93 #define CONFIG_ENABLE_36BIT_PHYS        1
  94
  95 #ifdef CONFIG_PHYS_64BIT
  96 #define CONFIG_ADDR_MAP                 1
  97 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  98 #endif
  99
 100 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
 101 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 102 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 103
 104 /*
 105  * Config the L2 Cache as L2 SRAM
 106  */
 107 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 108 #ifdef CONFIG_PHYS_64BIT
 109 #define CONFIG_SYS_INIT_L2_ADDR_PHYS            0xff8f80000ull
 110 #else
 111 #define CONFIG_SYS_INIT_L2_ADDR_PHYS            CONFIG_SYS_INIT_L2_ADDR
 112 #endif
 113 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 114 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 115
 116 #define CONFIG_SYS_CCSRBAR              0xffe00000
 117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 118
 119 #if defined(CONFIG_NAND_SPL)
 120 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 121 #endif
 122
 123 /* DDR Setup */
 124 #define CONFIG_VERY_BIG_RAM
 125 #define CONFIG_FSL_DDR2
 126 #undef CONFIG_FSL_DDR_INTERACTIVE
 127 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 128 #define CONFIG_DDR_SPD
 129
 130 #define CONFIG_DDR_ECC
 131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 132 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 133
 134 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 135 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 136
 137 #define CONFIG_NUM_DDR_CONTROLLERS      2
 138 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 139 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 140
 141 /* I2C addresses of SPD EEPROMs */
 142 #define CONFIG_SYS_SPD_BUS_NUM          1       /* SPD EEPROMS locate on I2C bus 1 */
 143 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 144 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 1 DIMM 0 */
 145
 146 /* These are used when DDR doesn't use SPD.  */
 147 #define CONFIG_SYS_SDRAM_SIZE           512             /* DDR is 512MB */
 148 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000001F
 149 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 150 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 151 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 152 #define CONFIG_SYS_DDR_TIMING_1         0x626b2634
 153 #define CONFIG_SYS_DDR_TIMING_2         0x062874cf
 154 #define CONFIG_SYS_DDR_MODE_1           0x00440462
 155 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 156 #define CONFIG_SYS_DDR_INTERVAL         0x0c300100
 157 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 158 #define CONFIG_SYS_DDR_CLK_CTRL         0x00800000
 159 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 160 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 161 #define CONFIG_SYS_DDR_CONTROL          0xc3000008      /* Type = DDR2 */
 162 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 163
 164 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 165 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 166 #define CONFIG_SYS_DDR_SBE              0x00010000
 167
 168 /*
 169  * Make sure required options are set
 170  */
 171 #ifndef CONFIG_SPD_EEPROM
 172 #error ("CONFIG_SPD_EEPROM is required")
 173 #endif
 174
 175 #undef CONFIG_CLOCKS_IN_MHZ
 176
 177 /*
 178  * Memory map
 179  *
 180  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 181  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 182  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 183  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 184  *
 185  * Localbus cacheable (TBD)
 186  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 187  *
 188  * Localbus non-cacheable
 189  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 190  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 191  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 192  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 193  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 194  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 195  */
 196
 197 /*
 198  * Local Bus Definitions
 199  */
 200 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 201 #ifdef CONFIG_PHYS_64BIT
 202 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 203 #else
 204 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 205 #endif
 206
 207
 208 #define CONFIG_FLASH_BR_PRELIM \
 209         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 210 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
 211
 212 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 213 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 214
 215 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 216 #define CONFIG_SYS_FLASH_QUIET_TEST
 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 218
 219 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 220 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 221 #undef  CONFIG_SYS_FLASH_CHECKSUM
 222 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 223 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 224
 225 #if defined(CONFIG_RAMBOOT_NAND)
 226 #define CONFIG_SYS_RAMBOOT
 227 #define CONFIG_SYS_EXTRA_ENV_RELOC
 228 #else
 229 #undef CONFIG_SYS_RAMBOOT
 230 #endif
 231
 232 #define CONFIG_FLASH_CFI_DRIVER
 233 #define CONFIG_SYS_FLASH_CFI
 234 #define CONFIG_SYS_FLASH_EMPTY_INFO
 235 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 236
 237 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 238
 239 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 240 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 241 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 242 #ifdef CONFIG_PHYS_64BIT
 243 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 244 #else
 245 #define PIXIS_BASE_PHYS PIXIS_BASE
 246 #endif
 247
 248 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 249 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 250
 251 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 252 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 253 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 254 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 255 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 256 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 257 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 258 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 259 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 260 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 261 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 262 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 263 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 264 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 265 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 266 #define PIXIS_VBOOT_LBMAP       0xc0    /* VBOOT - CFG_LBMAP */
 267 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 268 #define PIXIS_VBOOT_LBMAP_PJET  0x01    /* cfg_lbmap - boot from projet */
 269 #define PIXIS_VBOOT_LBMAP_NAND  0x02    /* cfg_lbmap - boot from NAND */
 270 #define PIXIS_VBOOT_LBMAP_NOR1  0x03    /* cfg_lbmap - boot from NOR 1 */
 271 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 272 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 273 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 274 #define PIXIS_VSYSCLK0          0x1C    /* VELA SYSCLK0 Register */
 275 #define PIXIS_VSYSCLK1          0x1D    /* VELA SYSCLK1 Register */
 276 #define PIXIS_VSYSCLK2          0x1E    /* VELA SYSCLK2 Register */
 277 #define PIXIS_VDDRCLK0          0x1F    /* VELA DDRCLK0 Register */
 278 #define PIXIS_VDDRCLK1          0x20    /* VELA DDRCLK1 Register */
 279 #define PIXIS_VDDRCLK2          0x21    /* VELA DDRCLK2 Register */
 280 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 281 #define PIXIS_LED               0x25    /* LED Register */
 282
 283 #define PIXIS_SPD_SYSCLK_MASK           0x7             /* SYSCLK option */
 284
 285 /* old pixis referenced names */
 286 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 287 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 288 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xc0
 289 #define PIXIS_VSPEED2_TSEC1SER  0x8
 290 #define PIXIS_VSPEED2_TSEC2SER  0x4
 291 #define PIXIS_VSPEED2_TSEC3SER  0x2
 292 #define PIXIS_VSPEED2_TSEC4SER  0x1
 293 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 294 #define PIXIS_VCFGEN1_TSEC2SER  0x20
 295 #define PIXIS_VCFGEN1_TSEC3SER  0x20
 296 #define PIXIS_VCFGEN1_TSEC4SER  0x20
 297 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER \
 298                                         | PIXIS_VSPEED2_TSEC2SER \
 299                                         | PIXIS_VSPEED2_TSEC3SER \
 300                                         | PIXIS_VSPEED2_TSEC4SER)
 301 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER \
 302                                         | PIXIS_VCFGEN1_TSEC2SER \
 303                                         | PIXIS_VCFGEN1_TSEC3SER \
 304                                         | PIXIS_VCFGEN1_TSEC4SER)
 305
 306 #define CONFIG_SYS_INIT_RAM_LOCK        1
 307 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 308 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 309
 310 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 311 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 312
 313 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 314 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 315
 316 #ifndef CONFIG_NAND_SPL
 317 #define CONFIG_SYS_NAND_BASE            0xffa00000
 318 #ifdef CONFIG_PHYS_64BIT
 319 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 320 #else
 321 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 322 #endif
 323 #else
 324 #define CONFIG_SYS_NAND_BASE            0xfff00000
 325 #ifdef CONFIG_PHYS_64BIT
 326 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 327 #else
 328 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 329 #endif
 330 #endif
 331
 332 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 333                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 334                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 335                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 336 #define CONFIG_SYS_MAX_NAND_DEVICE    4
 337 #define CONFIG_MTD_NAND_VERIFY_WRITE
 338 #define CONFIG_CMD_NAND         1
 339 #define CONFIG_NAND_FSL_ELBC    1
 340 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 341
 342 /* NAND boot: 4K NAND loader config */
 343 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 344 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 345 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 346 #define CONFIG_SYS_NAND_U_BOOT_START \
 347                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 348 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 349 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 350 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 351
 352
 353 /* NAND flash config */
 354 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 355                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 356                                | BR_PS_8               /* Port Size = 8 bit */ \
 357                                | BR_MS_FCM             /* MSEL = FCM */ \
 358                                | BR_V)                 /* valid */
 359 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 360                                | OR_FCM_PGS            /* Large Page*/ \
 361                                | OR_FCM_CSCT \
 362                                | OR_FCM_CST \
 363                                | OR_FCM_CHT \
 364                                | OR_FCM_SCY_1 \
 365                                | OR_FCM_TRLX \
 366                                | OR_FCM_EHTR)
 367
 368 #ifdef CONFIG_RAMBOOT_NAND
 369 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 370 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 371 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 372 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 373 #else
 374 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 375 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 376 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 377 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 378 #endif
 379 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 380                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 381                                | BR_PS_8               /* Port Size = 8 bit */ \
 382                                | BR_MS_FCM             /* MSEL = FCM */ \
 383                                | BR_V)                 /* valid */
 384 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 385 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
 386                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 387                                | BR_PS_8               /* Port Size = 8 bit */ \
 388                                | BR_MS_FCM             /* MSEL = FCM */ \
 389                                | BR_V)                 /* valid */
 390 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 391
 392 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
 393                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 394                                | BR_PS_8               /* Port Size = 8 bit */ \
 395                                | BR_MS_FCM             /* MSEL = FCM */ \
 396                                | BR_V)                 /* valid */
 397 #define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 398
 399
 400 /* Serial Port - controlled on board with jumper J8
 401  * open - index 2
 402  * shorted - index 1
 403  */
 404 #define CONFIG_CONS_INDEX       1
 405 #define CONFIG_SYS_NS16550
 406 #define CONFIG_SYS_NS16550_SERIAL
 407 #define CONFIG_SYS_NS16550_REG_SIZE     1
 408 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 409 #ifdef CONFIG_NAND_SPL
 410 #define CONFIG_NS16550_MIN_FUNCTIONS
 411 #endif
 412
 413 #define CONFIG_SYS_BAUDRATE_TABLE       \
 414         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 415
 416 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 417 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 418
 419 /* Use the HUSH parser */
 420 #define CONFIG_SYS_HUSH_PARSER
 421
 422 /*
 423  * Pass open firmware flat tree
 424  */
 425 #define CONFIG_OF_LIBFDT                1
 426 #define CONFIG_OF_BOARD_SETUP           1
 427 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 428
 429 /* new uImage format support */
 430 #define CONFIG_FIT              1
 431 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 432
 433 /* I2C */
 434 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 435 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 436 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 437 #define CONFIG_I2C_MULTI_BUS
 438 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 439 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 440 #define CONFIG_SYS_I2C_SLAVE            0x7F
 441 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
 442 #define CONFIG_SYS_I2C_OFFSET           0x3000
 443 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 444
 445 /*
 446  * I2C2 EEPROM
 447  */
 448 #define CONFIG_ID_EEPROM
 449 #ifdef CONFIG_ID_EEPROM
 450 #define CONFIG_SYS_I2C_EEPROM_NXID
 451 #endif
 452 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 453 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 454 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 455
 456 /*
 457  * General PCI
 458  * Memory space is mapped 1-1, but I/O space must start from 0.
 459  */
 460
 461 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 462 #define CONFIG_SYS_PCIE3_NAME           "ULI"
 463 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 464 #ifdef CONFIG_PHYS_64BIT
 465 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 466 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 467 #else
 468 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 469 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 470 #endif
 471 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 472 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 473 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 474 #ifdef CONFIG_PHYS_64BIT
 475 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 476 #else
 477 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 478 #endif
 479 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 480
 481 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 482 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 483 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 484 #ifdef CONFIG_PHYS_64BIT
 485 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 486 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 487 #else
 488 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 489 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 490 #endif
 491 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 492 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 493 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 494 #ifdef CONFIG_PHYS_64BIT
 495 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 496 #else
 497 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 498 #endif
 499 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 500
 501 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 502 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 503 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 504 #ifdef CONFIG_PHYS_64BIT
 505 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 506 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 507 #else
 508 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 509 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 510 #endif
 511 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 512 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 513 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 514 #ifdef CONFIG_PHYS_64BIT
 515 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 516 #else
 517 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 518 #endif
 519 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 520
 521 #if defined(CONFIG_PCI)
 522
 523 /*PCIE video card used*/
 524 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 525
 526 /* video */
 527 #define CONFIG_VIDEO
 528
 529 #if defined(CONFIG_VIDEO)
 530 #define CONFIG_BIOSEMU
 531 #define CONFIG_CFB_CONSOLE
 532 #define CONFIG_VIDEO_SW_CURSOR
 533 #define CONFIG_VGA_AS_SINGLE_DEVICE
 534 #define CONFIG_ATI_RADEON_FB
 535 #define CONFIG_VIDEO_LOGO
 536 /*#define CONFIG_CONSOLE_CURSOR*/
 537 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 538 #endif
 539
 540 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 541
 542 #undef CONFIG_EEPRO100
 543 #undef CONFIG_TULIP
 544 #undef CONFIG_RTL8139
 545 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
 546
 547 #ifndef CONFIG_PCI_PNP
 548         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
 549         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
 550         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 551 #endif
 552
 553 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 554 #define CONFIG_DOS_PARTITION
 555 #define CONFIG_SCSI_AHCI
 556
 557 #ifdef CONFIG_SCSI_AHCI
 558 #define CONFIG_SATA_ULI5288
 559 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 560 #define CONFIG_SYS_SCSI_MAX_LUN 1
 561 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 562 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 563 #endif /* SCSI */
 564
 565 #endif  /* CONFIG_PCI */
 566
 567
 568 #if defined(CONFIG_TSEC_ENET)
 569
 570 #define CONFIG_MII              1       /* MII PHY management */
 571 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 572 #define CONFIG_TSEC1    1
 573 #define CONFIG_TSEC1_NAME       "eTSEC1"
 574 #define CONFIG_TSEC2    1
 575 #define CONFIG_TSEC2_NAME       "eTSEC2"
 576 #define CONFIG_TSEC3    1
 577 #define CONFIG_TSEC3_NAME       "eTSEC3"
 578 #define CONFIG_TSEC4    1
 579 #define CONFIG_TSEC4_NAME       "eTSEC4"
 580
 581 #define CONFIG_PIXIS_SGMII_CMD
 582 #define CONFIG_FSL_SGMII_RISER  1
 583 #define SGMII_RISER_PHY_OFFSET  0x1c
 584
 585 #ifdef CONFIG_FSL_SGMII_RISER
 586 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 587 #endif
 588
 589 #define TSEC1_PHY_ADDR          0
 590 #define TSEC2_PHY_ADDR          1
 591 #define TSEC3_PHY_ADDR          2
 592 #define TSEC4_PHY_ADDR          3
 593
 594 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 595 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 596 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 597 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 598
 599 #define TSEC1_PHYIDX            0
 600 #define TSEC2_PHYIDX            0
 601 #define TSEC3_PHYIDX            0
 602 #define TSEC4_PHYIDX            0
 603
 604 #define CONFIG_ETHPRIME         "eTSEC1"
 605
 606 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 607 #endif  /* CONFIG_TSEC_ENET */
 608
 609 /*
 610  * Environment
 611  */
 612
 613 #if defined(CONFIG_SYS_RAMBOOT)
 614 #if defined(CONFIG_RAMBOOT_NAND)
 615 #define CONFIG_ENV_IS_IN_NAND   1
 616 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
 617 #define CONFIG_ENV_OFFSET       ((512 * 1024)\
 618                                 + CONFIG_SYS_NAND_BLOCK_SIZE)
 619 #endif
 620
 621 #else
 622         #define CONFIG_ENV_IS_IN_FLASH  1
 623         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 624         #define CONFIG_ENV_ADDR 0xfff80000
 625         #else
 626         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 627         #endif
 628         #define CONFIG_ENV_SIZE 0x2000
 629         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 630 #endif
 631
 632 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 633 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 634
 635 /*
 636  * Command line configuration.
 637  */
 638 #include <config_cmd_default.h>
 639
 640 #define CONFIG_CMD_ERRATA
 641 #define CONFIG_CMD_IRQ
 642 #define CONFIG_CMD_PING
 643 #define CONFIG_CMD_I2C
 644 #define CONFIG_CMD_MII
 645 #define CONFIG_CMD_ELF
 646 #define CONFIG_CMD_SETEXPR
 647 #define CONFIG_CMD_REGINFO
 648
 649 #if defined(CONFIG_PCI)
 650 #define CONFIG_CMD_PCI
 651 #define CONFIG_CMD_NET
 652 #define CONFIG_CMD_SCSI
 653 #define CONFIG_CMD_EXT2
 654 #endif
 655
 656 /*
 657  * USB
 658  */
 659 #define CONFIG_USB_EHCI
 660
 661 #ifdef CONFIG_USB_EHCI
 662 #define CONFIG_CMD_USB
 663 #define CONFIG_USB_EHCI_PCI
 664 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 665 #define CONFIG_USB_STORAGE
 666 #define CONFIG_PCI_EHCI_DEVICE                  0
 667 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      2
 668 #endif
 669
 670 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 671
 672 /*
 673  * Miscellaneous configurable options
 674  */
 675 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 676 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 677 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 678 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 679 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 680 #if defined(CONFIG_CMD_KGDB)
 681 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 682 #else
 683 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 684 #endif
 685 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 686 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 687 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 688 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 689
 690 /*
 691  * For booting Linux, the board info and command line data
 692  * have to be in the first 64 MB of memory, since this is
 693  * the maximum mapped by the Linux kernel during initialization.
 694  */
 695 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 696 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 697
 698 #if defined(CONFIG_CMD_KGDB)
 699 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 700 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 701 #endif
 702
 703 /*
 704  * Environment Configuration
 705  */
 706
 707 /* The mac addresses for all ethernet interface */
 708 #if defined(CONFIG_TSEC_ENET)
 709 #define CONFIG_HAS_ETH0
 710 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 711 #define CONFIG_HAS_ETH1
 712 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 713 #define CONFIG_HAS_ETH2
 714 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 715 #define CONFIG_HAS_ETH3
 716 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 717 #endif
 718
 719 #define CONFIG_IPADDR           192.168.1.254
 720
 721 #define CONFIG_HOSTNAME         unknown
 722 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 723 #define CONFIG_BOOTFILE         "uImage"
 724 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 725
 726 #define CONFIG_SERVERIP         192.168.1.1
 727 #define CONFIG_GATEWAYIP        192.168.1.1
 728 #define CONFIG_NETMASK          255.255.255.0
 729
 730 /* default location for tftp and bootm */
 731 #define CONFIG_LOADADDR         1000000
 732
 733 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 734 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 735
 736 #define CONFIG_BAUDRATE 115200
 737
 738 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 739 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0"         \
 740 "netdev=eth0\0"                                         \
 741 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 742 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 743         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 744                 " +$filesize; " \
 745         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 746                 " +$filesize; " \
 747         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 748                 " $filesize; "  \
 749         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 750                 " +$filesize; " \
 751         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 752                 " $filesize\0"  \
 753 "consoledev=ttyS0\0"                            \
 754 "ramdiskaddr=2000000\0"                 \
 755 "ramdiskfile=8572ds/ramdisk.uboot\0"            \
 756 "fdtaddr=c00000\0"                              \
 757 "fdtfile=8572ds/mpc8572ds.dtb\0"                \
 758 "bdev=sda3\0"
 759
 760 #define CONFIG_HDBOOT                           \
 761  "setenv bootargs root=/dev/$bdev rw "          \
 762  "console=$consoledev,$baudrate $othbootargs;"  \
 763  "tftp $loadaddr $bootfile;"                    \
 764  "tftp $fdtaddr $fdtfile;"                      \
 765  "bootm $loadaddr - $fdtaddr"
 766
 767 #define CONFIG_NFSBOOTCOMMAND           \
 768  "setenv bootargs root=/dev/nfs rw "    \
 769  "nfsroot=$serverip:$rootpath "         \
 770  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 771  "console=$consoledev,$baudrate $othbootargs;"  \
 772  "tftp $loadaddr $bootfile;"            \
 773  "tftp $fdtaddr $fdtfile;"              \
 774  "bootm $loadaddr - $fdtaddr"
 775
 776 #define CONFIG_RAMBOOTCOMMAND           \
 777  "setenv bootargs root=/dev/ram rw "    \
 778  "console=$consoledev,$baudrate $othbootargs;"  \
 779  "tftp $ramdiskaddr $ramdiskfile;"      \
 780  "tftp $loadaddr $bootfile;"            \
 781  "tftp $fdtaddr $fdtfile;"              \
 782  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 783
 784 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 785
 786 #endif  /* __CONFIG_H */