include/configs/MPC8610HPCD.h

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * MPC8610HPCD board configuration file
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_MPC86xx          1       /* MPC86xx */
  18 #define CONFIG_MPC8610          1       /* MPC8610 specific */
  19 #define CONFIG_MPC8610HPCD      1       /* MPC8610HPCD board specific */
  20 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  23
  24 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  25
  26 /* video */
  27 #undef CONFIG_VIDEO
  28
  29 #ifdef CONFIG_VIDEO
  30 #define CONFIG_CMD_BMP
  31 #define CONFIG_CFB_CONSOLE
  32 #define CONFIG_VGA_AS_SINGLE_DEVICE
  33 #define CONFIG_VIDEO_LOGO
  34 #define CONFIG_VIDEO_BMP_LOGO
  35 #endif
  36
  37 #ifdef RUN_DIAG
  38 #define CONFIG_SYS_DIAG_ADDR            0xff800000
  39 #endif
  40
  41 /*
  42  * virtual address to be used for temporary mappings.  There
  43  * should be 128k free at this VA.
  44  */
  45 #define CONFIG_SYS_SCRATCH_VA   0xc0000000
  46
  47 #define CONFIG_PCI              1       /* Enable PCI/PCIE*/
  48 #define CONFIG_PCI1             1       /* PCI controler 1 */
  49 #define CONFIG_PCIE1            1       /* PCIe 1 connected to ULI bridge */
  50 #define CONFIG_PCIE2            1       /* PCIe 2 connected to slot */
  51 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  52 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  53 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  54
  55 #define CONFIG_ENV_OVERWRITE
  56 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  57
  58 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  59 #define CONFIG_HIGH_BATS        1       /* High BATs supported & enabled */
  60 #define CONFIG_ALTIVEC          1
  61
  62 /*
  63  * L2CR setup -- make sure this is right for your board!
  64  */
  65 #define CONFIG_SYS_L2
  66 #define L2_INIT         0
  67 #define L2_ENABLE       (L2CR_L2E |0x00100000 )
  68
  69 #ifndef CONFIG_SYS_CLK_FREQ
  70 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  71 #endif
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  74 #define CONFIG_MISC_INIT_R              1
  75
  76 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  77 #define CONFIG_SYS_MEMTEST_END          0x00400000
  78
  79 /*
  80  * Base addresses -- Note these are effective addresses where the
  81  * actual resources get mapped (not physical addresses)
  82  */
  83 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  84 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  85 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  86
  87 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  88 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  89 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  90
  91 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_CCSRBAR+0x2c000)
  92
  93 /* DDR Setup */
  94 #define CONFIG_FSL_DDR2
  95 #undef CONFIG_FSL_DDR_INTERACTIVE
  96 #define CONFIG_SPD_EEPROM               /* Use SPD for DDR */
  97 #define CONFIG_DDR_SPD
  98
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 100 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 101
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 105 #define CONFIG_VERY_BIG_RAM
 106
 107 #define CONFIG_NUM_DDR_CONTROLLERS      1
 108 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 109 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 110
 111 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 112
 113 /* These are used when DDR doesn't use SPD.  */
 114 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 115
 116 #if 0 /* TODO */
 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 118 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 123 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 124 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 126 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 129 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 130 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 132
 133 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 134 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 135 #define CONFIG_SYS_DDR_SBE              0x000f0000
 136
 137 #endif
 138
 139
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_NXID
 142 #define CONFIG_ID_EEPROM
 143 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 145
 146
 147 #define CONFIG_SYS_FLASH_BASE           0xf0000000 /* start of FLASH 128M */
 148 #define CONFIG_SYS_FLASH_BASE2          0xf8000000
 149
 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 151
 152 #define CONFIG_SYS_BR0_PRELIM           0xf8001001 /* port size 16bit */
 153 #define CONFIG_SYS_OR0_PRELIM           0xf8006e65 /* 128MB NOR Flash*/
 154
 155 #define CONFIG_SYS_BR1_PRELIM           0xf0001001 /* port size 16bit */
 156 #define CONFIG_SYS_OR1_PRELIM           0xf8006e65 /* 128MB Promjet */
 157 #if 0 /* TODO */
 158 #define CONFIG_SYS_BR2_PRELIM           0xf0000000
 159 #define CONFIG_SYS_OR2_PRELIM           0xf0000000 /* 256MB NAND Flash - bank 1 */
 160 #endif
 161 #define CONFIG_SYS_BR3_PRELIM           0xe8000801 /* port size 8bit */
 162 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7 /* 1MB PIXIS area*/
 163
 164
 165 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 166 #define PIXIS_BASE      0xe8000000      /* PIXIS registers */
 167 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 168 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 169 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 170 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 171 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch */
 172 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 173 #define PIXIS_BRDCFG0           0x8     /* PIXIS Board Configuration Register0*/
 174 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 175 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 176 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 177 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 178 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 179 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 180 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 181 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 182 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xC0    /* Reset altbank mask */
 183
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 185 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 186
 187 #undef  CONFIG_SYS_FLASH_CHECKSUM
 188 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 189 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 191 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 192
 193 #define CONFIG_FLASH_CFI_DRIVER
 194 #define CONFIG_SYS_FLASH_CFI
 195 #define CONFIG_SYS_FLASH_EMPTY_INFO
 196
 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 198 #define CONFIG_SYS_RAMBOOT
 199 #else
 200 #undef  CONFIG_SYS_RAMBOOT
 201 #endif
 202
 203 #if defined(CONFIG_SYS_RAMBOOT)
 204 #undef CONFIG_SPD_EEPROM
 205 #define CONFIG_SYS_SDRAM_SIZE   256
 206 #endif
 207
 208 #undef CONFIG_CLOCKS_IN_MHZ
 209
 210 #define CONFIG_SYS_INIT_RAM_LOCK        1
 211 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 212 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 213 #else
 214 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4000000      /* Initial RAM address */
 215 #endif
 216 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 217
 218 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 219 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 220 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 221
 222 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 223 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 224
 225 /* Serial Port */
 226 #define CONFIG_CONS_INDEX       1
 227 #define CONFIG_SYS_NS16550
 228 #define CONFIG_SYS_NS16550_SERIAL
 229 #define CONFIG_SYS_NS16550_REG_SIZE     1
 230 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 231
 232 #define CONFIG_SYS_BAUDRATE_TABLE \
 233         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 234
 235 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 236 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 237
 238 /* Use the HUSH parser */
 239 #define CONFIG_SYS_HUSH_PARSER
 240 #ifdef  CONFIG_SYS_HUSH_PARSER
 241 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 242 #endif
 243
 244 /*
 245  * Pass open firmware flat tree to kernel
 246  */
 247 #define CONFIG_OF_LIBFDT                1
 248 #define CONFIG_OF_BOARD_SETUP           1
 249 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 250
 251
 252 /* maximum size of the flat tree (8K) */
 253 #define OF_FLAT_TREE_MAX_SIZE   8192
 254
 255 /*
 256  * I2C
 257  */
 258 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 259 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 260 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 261 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 262 #define CONFIG_SYS_I2C_SLAVE            0x7F
 263 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 264 #define CONFIG_SYS_I2C_OFFSET           0x3000
 265
 266 /*
 267  * General PCI
 268  * Addresses are mapped 1-1.
 269  */
 270 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 271 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 272 #define CONFIG_SYS_PCI1_MEM_VIRT        CONFIG_SYS_PCI1_MEM_BUS
 273 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 274 #define CONFIG_SYS_PCI1_IO_BUS  0x0000000
 275 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 276 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 277 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 278
 279 /* controller 1, Base address 0xa000 */
 280 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 281 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 282 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 283 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 284 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 285 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /* 1M */
 286
 287 /* controller 2, Base Address 0x9000 */
 288 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 289 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 290 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 291 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000      /* reuse mem LAW */
 292 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe2000000
 293 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00100000      /* 1M */
 294
 295
 296 #if defined(CONFIG_PCI)
 297
 298 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 299
 300 #define CONFIG_NET_MULTI
 301 #define CONFIG_CMD_NET
 302 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 303 #define CONFIG_CMD_REGINFO
 304
 305 #define CONFIG_ULI526X
 306 #ifdef CONFIG_ULI526X
 307 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 308 #endif
 309
 310 /************************************************************
 311  * USB support
 312  ************************************************************/
 313 #define CONFIG_PCI_OHCI         1
 314 #define CONFIG_USB_OHCI_NEW             1
 315 #define CONFIG_USB_KEYBOARD     1
 316 #define CONFIG_SYS_STDIO_DEREGISTER
 317 #define CONFIG_SYS_USB_EVENT_POLL       1
 318 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 319 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 320 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 321
 322 #if !defined(CONFIG_PCI_PNP)
 323 #define PCI_ENET0_IOADDR        0xe0000000
 324 #define PCI_ENET0_MEMADDR       0xe0000000
 325 #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 326 #endif
 327
 328 #define CONFIG_DOS_PARTITION
 329 #define CONFIG_SCSI_AHCI
 330
 331 #ifdef CONFIG_SCSI_AHCI
 332 #define CONFIG_SATA_ULI5288
 333 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 334 #define CONFIG_SYS_SCSI_MAX_LUN 1
 335 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 336 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 337 #endif
 338
 339 #endif  /* CONFIG_PCI */
 340
 341 /*
 342  * BAT0         2G      Cacheable, non-guarded
 343  * 0x0000_0000  2G      DDR
 344  */
 345 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW)
 346 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW)
 347
 348 /*
 349  * BAT1         1G      Cache-inhibited, guarded
 350  * 0x8000_0000  256M    PCI-1 Memory
 351  * 0xa000_0000  256M    PCI-Express 1 Memory
 352  * 0x9000_0000  256M    PCI-Express 2 Memory
 353  */
 354
 355 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 356                         | BATL_GUARDEDSTORAGE)
 357 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 358 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 359 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 360
 361 /*
 362  * BAT2         16M     Cache-inhibited, guarded
 363  * 0xe100_0000  1M      PCI-1 I/O
 364  */
 365
 366 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 367                         | BATL_GUARDEDSTORAGE)
 368 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 369 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 370 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 371
 372 /*
 373  * BAT3         4M      Cache-inhibited, guarded
 374  * 0xe000_0000  4M      CCSR
 375  */
 376
 377 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 378                         | BATL_GUARDEDSTORAGE)
 379 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
 380 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 381 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 382
 383 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 384 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 385                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 386                                        | BATL_GUARDEDSTORAGE)
 387 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 388                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 389 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 390                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 391 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 392 #endif
 393
 394 /*
 395  * BAT4         32M     Cache-inhibited, guarded
 396  * 0xe200_0000  1M      PCI-Express 2 I/O
 397  * 0xe300_0000  1M      PCI-Express 1 I/O
 398  */
 399
 400 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 401                         | BATL_GUARDEDSTORAGE)
 402 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 403 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 404 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 405
 406
 407 /*
 408  * BAT5         128K    Cacheable, non-guarded
 409  * 0xe400_0000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 410  */
 411 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 412 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 413 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 414 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 415
 416 /*
 417  * BAT6         256M    Cache-inhibited, guarded
 418  * 0xf000_0000  256M    FLASH
 419  */
 420 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE   | BATL_PP_RW | BATL_CACHEINHIBIT \
 421                         | BATL_GUARDEDSTORAGE)
 422 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE   | BATU_BL_256M | BATU_VS | BATU_VP)
 423 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 424 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 425
 426 /* Map the last 1M of flash where we're running from reset */
 427 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 428                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 429 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 430 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 431                                  | BATL_MEMCOHERENCE)
 432 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 433
 434 /*
 435  * BAT7         4M      Cache-inhibited, guarded
 436  * 0xe800_0000  4M      PIXIS
 437  */
 438 #define CONFIG_SYS_DBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 439                         | BATL_GUARDEDSTORAGE)
 440 #define CONFIG_SYS_DBAT7U       (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 441 #define CONFIG_SYS_IBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 442 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 443
 444
 445 /*
 446  * Environment
 447  */
 448 #ifndef CONFIG_SYS_RAMBOOT
 449 #define CONFIG_ENV_IS_IN_FLASH  1
 450 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 451 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 126k (one sector) for env */
 452 #define CONFIG_ENV_SIZE         0x2000
 453 #else
 454 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 455 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 456 #define CONFIG_ENV_SIZE         0x2000
 457 #endif
 458
 459 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 460 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 461
 462
 463 /*
 464  * BOOTP options
 465  */
 466 #define CONFIG_BOOTP_BOOTFILESIZE
 467 #define CONFIG_BOOTP_BOOTPATH
 468 #define CONFIG_BOOTP_GATEWAY
 469 #define CONFIG_BOOTP_HOSTNAME
 470
 471
 472 /*
 473  * Command line configuration.
 474  */
 475 #include <config_cmd_default.h>
 476
 477 #define CONFIG_CMD_PING
 478 #define CONFIG_CMD_I2C
 479 #define CONFIG_CMD_MII
 480
 481 #if defined(CONFIG_SYS_RAMBOOT)
 482 #undef CONFIG_CMD_SAVEENV
 483 #endif
 484
 485 #if defined(CONFIG_PCI)
 486 #define CONFIG_CMD_PCI
 487 #define CONFIG_CMD_SCSI
 488 #define CONFIG_CMD_EXT2
 489 #define CONFIG_CMD_USB
 490 #endif
 491
 492
 493 #define CONFIG_WATCHDOG                 /* watchdog enabled */
 494 #define CONFIG_SYS_WATCHDOG_FREQ        5000    /* Feed interval, 5s */
 495
 496 /*DIU Configuration*/
 497 #define DIU_CONNECT_TO_DVI              /* DIU controller connects to DVI encoder*/
 498
 499 /*
 500  * Miscellaneous configurable options
 501  */
 502 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 503 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 504 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 505 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 506
 507 #if defined(CONFIG_CMD_KGDB)
 508 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 509 #else
 510 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 511 #endif
 512
 513 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 514 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 515 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 516 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 517
 518 /*
 519  * For booting Linux, the board info and command line data
 520  * have to be in the first 8 MB of memory, since this is
 521  * the maximum mapped by the Linux kernel during initialization.
 522  */
 523 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 524
 525 #if defined(CONFIG_CMD_KGDB)
 526 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 527 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 528 #endif
 529
 530 /*
 531  * Environment Configuration
 532  */
 533 #define CONFIG_IPADDR           192.168.1.100
 534
 535 #define CONFIG_HOSTNAME         unknown
 536 #define CONFIG_ROOTPATH         /opt/nfsroot
 537 #define CONFIG_BOOTFILE         uImage
 538 #define CONFIG_UBOOTPATH        8610hpcd/u-boot.bin
 539
 540 #define CONFIG_SERVERIP         192.168.1.1
 541 #define CONFIG_GATEWAYIP        192.168.1.1
 542 #define CONFIG_NETMASK          255.255.255.0
 543
 544 /* default location for tftp and bootm */
 545 #define CONFIG_LOADADDR         1000000
 546
 547 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 548 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 549
 550 #define CONFIG_BAUDRATE 115200
 551
 552 #if defined(CONFIG_PCI1)
 553 #define PCI_ENV \
 554  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 555         "echo e;md ${a}e00 9\0" \
 556  "pci1regs=setenv a e0008; run pcireg\0" \
 557  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 558         "pci d.w $b.0 56 1\0" \
 559  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
 560         "pci w.w $b.0 56 ffff\0"        \
 561  "pci1err=setenv a e0008; run pcierr\0" \
 562  "pci1errc=setenv a e0008; run pcierrc\0"
 563 #else
 564 #define PCI_ENV ""
 565 #endif
 566
 567 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
 568 #define PCIE_ENV \
 569  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 570         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 571  "pcie1regs=setenv a e000a; run pciereg\0"      \
 572  "pcie2regs=setenv a e0009; run pciereg\0"      \
 573  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
 574         "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"        \
 575         "pci d $b.0 130 1\0" \
 576  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
 577         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
 578         "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"            \
 579  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 580  "pcie1err=setenv a e000a; run pcieerr\0"       \
 581  "pcie2err=setenv a e0009; run pcieerr\0"       \
 582  "pcie1errc=setenv a e000a; run pcieerrc\0"     \
 583  "pcie2errc=setenv a e0009; run pcieerrc\0"
 584 #else
 585 #define PCIE_ENV ""
 586 #endif
 587
 588 #define DMA_ENV \
 589  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
 590         "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
 591  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
 592         "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
 593  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
 594         "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
 595  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 596         "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 597
 598 #ifdef ENV_DEBUG
 599 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 600  "netdev=eth0\0"                                                \
 601  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 602  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 603         "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 604         "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 605         "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 606         "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 607         "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 608  "consoledev=ttyS0\0"                                           \
 609  "ramdiskaddr=2000000\0"                                        \
 610  "ramdiskfile=8610hpcd/ramdisk.uboot\0"                         \
 611  "fdtaddr=c00000\0"                                             \
 612  "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                          \
 613  "bdev=sda3\0"                                  \
 614  "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 615  "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 616  "maxcpus=1"    \
 617  "eoi=mw e00400b0 0\0"                                          \
 618  "iack=md e00400a0 1\0"                                         \
 619  "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
 620         "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
 621         "md ${a}f00 5\0" \
 622  "ddr1regs=setenv a e0002; run ddrreg\0" \
 623  "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
 624         "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
 625         "md ${a}e60 1; md ${a}ef0 1d\0" \
 626  "guregs=setenv a e00e0; run gureg\0" \
 627  "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
 628  "mcmregs=setenv a e0001; run mcmreg\0" \
 629  "diuregs=md e002c000 1d\0" \
 630  "dium=mw e002c01c\0" \
 631  "diuerr=md e002c014 1\0" \
 632  "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
 633  "monitor=0-DVI\0" \
 634  "pmregs=md e00e1000 2b\0" \
 635  "lawregs=md e0000c08 4b\0" \
 636  "lbcregs=md e0005000 36\0" \
 637  "dma0regs=md e0021100 12\0" \
 638  "dma1regs=md e0021180 12\0" \
 639  "dma2regs=md e0021200 12\0" \
 640  "dma3regs=md e0021280 12\0" \
 641  PCI_ENV \
 642  PCIE_ENV \
 643  DMA_ENV
 644 #else
 645 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 646  "netdev=eth0\0"                                                \
 647  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 648  "consoledev=ttyS0\0"                                           \
 649  "ramdiskaddr=2000000\0"                                        \
 650  "ramdiskfile=8610hpcd/ramdisk.uboot\0"                         \
 651  "fdtaddr=c00000\0"                                             \
 652  "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                          \
 653  "bdev=sda3\0"                                                  \
 654  "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
 655  "monitor=0-DVI\0"
 656 #endif
 657
 658 #define CONFIG_NFSBOOTCOMMAND                                   \
 659  "setenv bootargs root=/dev/nfs rw "                            \
 660         "nfsroot=$serverip:$rootpath "                          \
 661         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 662         "console=$consoledev,$baudrate $othbootargs;"           \
 663  "tftp $loadaddr $bootfile;"                                    \
 664  "tftp $fdtaddr $fdtfile;"                                      \
 665  "bootm $loadaddr - $fdtaddr"
 666
 667 #define CONFIG_RAMBOOTCOMMAND \
 668  "setenv bootargs root=/dev/ram rw "                            \
 669         "console=$consoledev,$baudrate $othbootargs;"           \
 670  "tftp $ramdiskaddr $ramdiskfile;"                              \
 671  "tftp $loadaddr $bootfile;"                                    \
 672  "tftp $fdtaddr $fdtfile;"                                      \
 673  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 674
 675 #define CONFIG_BOOTCOMMAND              \
 676  "setenv bootargs root=/dev/$bdev rw "  \
 677         "console=$consoledev,$baudrate $othbootargs;"   \
 678  "tftp $loadaddr $bootfile;"            \
 679  "tftp $fdtaddr $fdtfile;"              \
 680  "bootm $loadaddr - $fdtaddr"
 681
 682 #endif  /* __CONFIG_H */