include/configs/MPC8610HPCD.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * MPC8610HPCD board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  15
  16 /* video */
  17 #define CONFIG_FSL_DIU_FB
  18
  19 #ifdef CONFIG_FSL_DIU_FB
  20 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x2c000)
  21 #define CONFIG_VIDEO_LOGO
  22 #define CONFIG_VIDEO_BMP_LOGO
  23 #endif
  24
  25 #ifdef RUN_DIAG
  26 #define CONFIG_SYS_DIAG_ADDR            0xff800000
  27 #endif
  28
  29 /*
  30  * virtual address to be used for temporary mappings.  There
  31  * should be 128k free at this VA.
  32  */
  33 #define CONFIG_SYS_SCRATCH_VA   0xc0000000
  34
  35 #define CONFIG_PCI1             1       /* PCI controller 1 */
  36 #define CONFIG_PCIE1            1       /* PCIe 1 connected to ULI bridge */
  37 #define CONFIG_PCIE2            1       /* PCIe 2 connected to slot */
  38 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  39 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  40 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  41
  42 #define CONFIG_ENV_OVERWRITE
  43 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  44
  45 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  46 #define CONFIG_ALTIVEC          1
  47
  48 /*
  49  * L2CR setup -- make sure this is right for your board!
  50  */
  51 #define CONFIG_SYS_L2
  52 #define L2_INIT         0
  53 #define L2_ENABLE       (L2CR_L2E |0x00100000 )
  54
  55 #ifndef CONFIG_SYS_CLK_FREQ
  56 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  57 #endif
  58
  59 /*
  60  * Base addresses -- Note these are effective addresses where the
  61  * actual resources get mapped (not physical addresses)
  62  */
  63 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  64 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  65
  66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  67 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  68 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  69
  70 /* DDR Setup */
  71 #define CONFIG_SPD_EEPROM               /* Use SPD for DDR */
  72 #define CONFIG_DDR_SPD
  73
  74 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  75 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  76
  77 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  78 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  79 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  80 #define CONFIG_VERY_BIG_RAM
  81
  82 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  83 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  84
  85 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  86
  87 /* These are used when DDR doesn't use SPD.  */
  88 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
  89
  90 #if 0 /* TODO */
  91 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  92 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
  93 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  94 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  95 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  96 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  97 #define CONFIG_SYS_DDR_MODE_1           0x00480432
  98 #define CONFIG_SYS_DDR_MODE_2           0x00000000
  99 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 100 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 101 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 102 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 103 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 104 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 105 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 106
 107 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 108 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 109 #define CONFIG_SYS_DDR_SBE              0x000f0000
 110
 111 #endif
 112
 113 #define CONFIG_ID_EEPROM
 114 #define CONFIG_SYS_I2C_EEPROM_NXID
 115 #define CONFIG_ID_EEPROM
 116 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 118
 119 #define CONFIG_SYS_FLASH_BASE           0xf0000000 /* start of FLASH 128M */
 120 #define CONFIG_SYS_FLASH_BASE2          0xf8000000
 121
 122 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 123
 124 #define CONFIG_SYS_BR0_PRELIM           0xf8001001 /* port size 16bit */
 125 #define CONFIG_SYS_OR0_PRELIM           0xf8006e65 /* 128MB NOR Flash*/
 126
 127 #define CONFIG_SYS_BR1_PRELIM           0xf0001001 /* port size 16bit */
 128 #define CONFIG_SYS_OR1_PRELIM           0xf8006e65 /* 128MB Promjet */
 129 #if 0 /* TODO */
 130 #define CONFIG_SYS_BR2_PRELIM           0xf0000000
 131 #define CONFIG_SYS_OR2_PRELIM           0xf0000000 /* 256MB NAND Flash - bank 1 */
 132 #endif
 133 #define CONFIG_SYS_BR3_PRELIM           0xe8000801 /* port size 8bit */
 134 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7 /* 1MB PIXIS area*/
 135
 136 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 137 #define PIXIS_BASE      0xe8000000      /* PIXIS registers */
 138 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 139 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 140 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 141 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 142 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch */
 143 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 144 #define PIXIS_BRDCFG0           0x8     /* PIXIS Board Configuration Register0*/
 145 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 146 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 147 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 148 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 149 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 150 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 151 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 152 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 153 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xC0    /* Reset altbank mask */
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 156 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 157
 158 #undef  CONFIG_SYS_FLASH_CHECKSUM
 159 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 160 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 162 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 163
 164 #define CONFIG_SYS_FLASH_EMPTY_INFO
 165
 166 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 167 #define CONFIG_SYS_RAMBOOT
 168 #else
 169 #undef  CONFIG_SYS_RAMBOOT
 170 #endif
 171
 172 #if defined(CONFIG_SYS_RAMBOOT)
 173 #undef CONFIG_SPD_EEPROM
 174 #define CONFIG_SYS_SDRAM_SIZE   256
 175 #endif
 176
 177 #undef CONFIG_CLOCKS_IN_MHZ
 178
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 181 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 182 #else
 183 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4000000      /* Initial RAM address */
 184 #endif
 185 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 186
 187 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 188 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 189
 190 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 191 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 192
 193 /* Serial Port */
 194 #define CONFIG_SYS_NS16550_SERIAL
 195 #define CONFIG_SYS_NS16550_REG_SIZE     1
 196 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 197
 198 #define CONFIG_SYS_BAUDRATE_TABLE \
 199         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 200
 201 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 202 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 203
 204 /* maximum size of the flat tree (8K) */
 205 #define OF_FLAT_TREE_MAX_SIZE   8192
 206
 207 /*
 208  * I2C
 209  */
 210 #define CONFIG_SYS_I2C
 211 #define CONFIG_SYS_I2C_FSL
 212 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 213 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 214 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 215 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 216
 217 /*
 218  * General PCI
 219  * Addresses are mapped 1-1.
 220  */
 221 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 222 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 223 #define CONFIG_SYS_PCI1_MEM_VIRT        CONFIG_SYS_PCI1_MEM_BUS
 224 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 225 #define CONFIG_SYS_PCI1_IO_BUS  0x0000000
 226 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 227 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 228 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 229
 230 /* controller 1, Base address 0xa000 */
 231 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 232 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 233 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 234 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 235 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 236 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 237 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /* 1M */
 238
 239 /* controller 2, Base Address 0x9000 */
 240 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 241 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 242 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 243 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 244 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000      /* reuse mem LAW */
 245 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe2000000
 246 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00100000      /* 1M */
 247
 248 #if defined(CONFIG_PCI)
 249
 250 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 251
 252 #define CONFIG_ULI526X
 253
 254 /************************************************************
 255  * USB support
 256  ************************************************************/
 257 #define CONFIG_PCI_OHCI         1
 258 #define CONFIG_USB_OHCI_NEW             1
 259 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 260 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 261 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 262
 263 #if !defined(CONFIG_PCI_PNP)
 264 #define PCI_ENET0_IOADDR        0xe0000000
 265 #define PCI_ENET0_MEMADDR       0xe0000000
 266 #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 267 #endif
 268
 269 #ifdef CONFIG_SCSI_AHCI
 270 #define CONFIG_SATA_ULI5288
 271 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 272 #define CONFIG_SYS_SCSI_MAX_LUN 1
 273 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 274 #endif
 275
 276 #endif  /* CONFIG_PCI */
 277
 278 /*
 279  * BAT0         2G      Cacheable, non-guarded
 280  * 0x0000_0000  2G      DDR
 281  */
 282 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW)
 283 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW)
 284
 285 /*
 286  * BAT1         1G      Cache-inhibited, guarded
 287  * 0x8000_0000  256M    PCI-1 Memory
 288  * 0xa000_0000  256M    PCI-Express 1 Memory
 289  * 0x9000_0000  256M    PCI-Express 2 Memory
 290  */
 291
 292 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 293                         | BATL_GUARDEDSTORAGE)
 294 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 295 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 296 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 297
 298 /*
 299  * BAT2         16M     Cache-inhibited, guarded
 300  * 0xe100_0000  1M      PCI-1 I/O
 301  */
 302
 303 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 304                         | BATL_GUARDEDSTORAGE)
 305 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 306 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 307 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 308
 309 /*
 310  * BAT3         4M      Cache-inhibited, guarded
 311  * 0xe000_0000  4M      CCSR
 312  */
 313
 314 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 315                         | BATL_GUARDEDSTORAGE)
 316 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
 317 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 318 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 319
 320 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 321 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 322                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 323                                        | BATL_GUARDEDSTORAGE)
 324 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 325                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 326 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 327                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 328 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 329 #endif
 330
 331 /*
 332  * BAT4         32M     Cache-inhibited, guarded
 333  * 0xe200_0000  1M      PCI-Express 2 I/O
 334  * 0xe300_0000  1M      PCI-Express 1 I/O
 335  */
 336
 337 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 338                         | BATL_GUARDEDSTORAGE)
 339 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 340 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 341 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 342
 343 /*
 344  * BAT5         128K    Cacheable, non-guarded
 345  * 0xe400_0000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 346  */
 347 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 348 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 349 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 350 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 351
 352 /*
 353  * BAT6         256M    Cache-inhibited, guarded
 354  * 0xf000_0000  256M    FLASH
 355  */
 356 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE   | BATL_PP_RW | BATL_CACHEINHIBIT \
 357                         | BATL_GUARDEDSTORAGE)
 358 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE   | BATU_BL_256M | BATU_VS | BATU_VP)
 359 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 360 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 361
 362 /* Map the last 1M of flash where we're running from reset */
 363 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 364                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 365 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 366 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 367                                  | BATL_MEMCOHERENCE)
 368 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 369
 370 /*
 371  * BAT7         4M      Cache-inhibited, guarded
 372  * 0xe800_0000  4M      PIXIS
 373  */
 374 #define CONFIG_SYS_DBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 375                         | BATL_GUARDEDSTORAGE)
 376 #define CONFIG_SYS_DBAT7U       (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 377 #define CONFIG_SYS_IBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 378 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 379
 380 /*
 381  * Environment
 382  */
 383
 384 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 385 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 386
 387 /*
 388  * BOOTP options
 389  */
 390 #define CONFIG_BOOTP_BOOTFILESIZE
 391
 392 /*
 393  * Command line configuration.
 394  */
 395
 396 #define CONFIG_WATCHDOG                 /* watchdog enabled */
 397 #define CONFIG_SYS_WATCHDOG_FREQ        5000    /* Feed interval, 5s */
 398
 399 /*
 400  * Miscellaneous configurable options
 401  */
 402 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 403
 404 /*
 405  * For booting Linux, the board info and command line data
 406  * have to be in the first 8 MB of memory, since this is
 407  * the maximum mapped by the Linux kernel during initialization.
 408  */
 409 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 410 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 411
 412 #if defined(CONFIG_CMD_KGDB)
 413 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 414 #endif
 415
 416 /*
 417  * Environment Configuration
 418  */
 419 #define CONFIG_IPADDR           192.168.1.100
 420
 421 #define CONFIG_HOSTNAME         "unknown"
 422 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 423 #define CONFIG_BOOTFILE         "uImage"
 424 #define CONFIG_UBOOTPATH        8610hpcd/u-boot.bin
 425
 426 #define CONFIG_SERVERIP         192.168.1.1
 427 #define CONFIG_GATEWAYIP        192.168.1.1
 428 #define CONFIG_NETMASK          255.255.255.0
 429
 430 /* default location for tftp and bootm */
 431 #define CONFIG_LOADADDR         0x10000000
 432
 433 #if defined(CONFIG_PCI1)
 434 #define PCI_ENV \
 435  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 436         "echo e;md ${a}e00 9\0" \
 437  "pci1regs=setenv a e0008; run pcireg\0" \
 438  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 439         "pci d.w $b.0 56 1\0" \
 440  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
 441         "pci w.w $b.0 56 ffff\0"        \
 442  "pci1err=setenv a e0008; run pcierr\0" \
 443  "pci1errc=setenv a e0008; run pcierrc\0"
 444 #else
 445 #define PCI_ENV ""
 446 #endif
 447
 448 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
 449 #define PCIE_ENV \
 450  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 451         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 452  "pcie1regs=setenv a e000a; run pciereg\0"      \
 453  "pcie2regs=setenv a e0009; run pciereg\0"      \
 454  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
 455         "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"        \
 456         "pci d $b.0 130 1\0" \
 457  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
 458         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
 459         "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"            \
 460  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 461  "pcie1err=setenv a e000a; run pcieerr\0"       \
 462  "pcie2err=setenv a e0009; run pcieerr\0"       \
 463  "pcie1errc=setenv a e000a; run pcieerrc\0"     \
 464  "pcie2errc=setenv a e0009; run pcieerrc\0"
 465 #else
 466 #define PCIE_ENV ""
 467 #endif
 468
 469 #define DMA_ENV \
 470  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
 471         "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
 472  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
 473         "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
 474  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
 475         "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
 476  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 477         "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 478
 479 #ifdef ENV_DEBUG
 480 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 481 "netdev=eth0\0"                                                 \
 482 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 483 "tftpflash=tftpboot $loadaddr $uboot; "                         \
 484         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 485                 " +$filesize; " \
 486         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 487                 " +$filesize; " \
 488         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 489                 " $filesize; "  \
 490         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 491                 " +$filesize; " \
 492         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 493                 " $filesize\0"  \
 494 "consoledev=ttyS0\0"                                            \
 495 "ramdiskaddr=0x18000000\0"                                      \
 496 "ramdiskfile=8610hpcd/ramdisk.uboot\0"                          \
 497 "fdtaddr=0x17c00000\0"                                          \
 498 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                           \
 499 "bdev=sda3\0"                                   \
 500 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 501 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 502 "maxcpus=1"     \
 503 "eoi=mw e00400b0 0\0"                                           \
 504 "iack=md e00400a0 1\0"                                          \
 505 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
 506         "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
 507         "md ${a}f00 5\0" \
 508 "ddr1regs=setenv a e0002; run ddrreg\0" \
 509 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
 510         "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
 511         "md ${a}e60 1; md ${a}ef0 1d\0" \
 512 "guregs=setenv a e00e0; run gureg\0" \
 513 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
 514 "mcmregs=setenv a e0001; run mcmreg\0" \
 515 "diuregs=md e002c000 1d\0" \
 516 "dium=mw e002c01c\0" \
 517 "diuerr=md e002c014 1\0" \
 518 "pmregs=md e00e1000 2b\0" \
 519 "lawregs=md e0000c08 4b\0" \
 520 "lbcregs=md e0005000 36\0" \
 521 "dma0regs=md e0021100 12\0" \
 522 "dma1regs=md e0021180 12\0" \
 523 "dma2regs=md e0021200 12\0" \
 524 "dma3regs=md e0021280 12\0" \
 525  PCI_ENV \
 526  PCIE_ENV \
 527  DMA_ENV
 528 #else
 529 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 530         "netdev=eth0\0"                                         \
 531         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 532         "consoledev=ttyS0\0"                                    \
 533         "ramdiskaddr=0x18000000\0"                              \
 534         "ramdiskfile=8610hpcd/ramdisk.uboot\0"                  \
 535         "fdtaddr=0x17c00000\0"                                  \
 536         "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                   \
 537         "bdev=sda3\0"
 538 #endif
 539
 540 #define CONFIG_NFSBOOTCOMMAND                                   \
 541  "setenv bootargs root=/dev/nfs rw "                            \
 542         "nfsroot=$serverip:$rootpath "                          \
 543         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 544         "console=$consoledev,$baudrate $othbootargs;"           \
 545  "tftp $loadaddr $bootfile;"                                    \
 546  "tftp $fdtaddr $fdtfile;"                                      \
 547  "bootm $loadaddr - $fdtaddr"
 548
 549 #define CONFIG_RAMBOOTCOMMAND \
 550  "setenv bootargs root=/dev/ram rw "                            \
 551         "console=$consoledev,$baudrate $othbootargs;"           \
 552  "tftp $ramdiskaddr $ramdiskfile;"                              \
 553  "tftp $loadaddr $bootfile;"                                    \
 554  "tftp $fdtaddr $fdtfile;"                                      \
 555  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 556
 557 #define CONFIG_BOOTCOMMAND              \
 558  "setenv bootargs root=/dev/$bdev rw "  \
 559         "console=$consoledev,$baudrate $othbootargs;"   \
 560  "tftp $loadaddr $bootfile;"            \
 561  "tftp $fdtaddr $fdtfile;"              \
 562  "bootm $loadaddr - $fdtaddr"
 563
 564 #endif  /* __CONFIG_H */