include/configs/MPC8610HPCD.h

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * MPC8610HPCD board configuration file
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_MPC86xx          1       /* MPC86xx */
  18 #define CONFIG_MPC8610          1       /* MPC8610 specific */
  19 #define CONFIG_MPC8610HPCD      1       /* MPC8610HPCD board specific */
  20 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  21
  22 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  23
  24 /* video */
  25 #undef CONFIG_VIDEO
  26
  27 #if defined(CONFIG_VIDEO)
  28 #define CONFIG_CFB_CONSOLE
  29 #define CONFIG_VGA_AS_SINGLE_DEVICE
  30 #endif
  31
  32 #ifdef RUN_DIAG
  33 #define CONFIG_SYS_DIAG_ADDR            0xff800000
  34 #endif
  35
  36 /*
  37  * virtual address to be used for temporary mappings.  There
  38  * should be 128k free at this VA.
  39  */
  40 #define CONFIG_SYS_SCRATCH_VA   0xc0000000
  41
  42 #define CONFIG_PCI              1       /* Enable PCI/PCIE*/
  43 #define CONFIG_PCI1             1       /* PCI controler 1 */
  44 #define CONFIG_PCIE1            1       /* PCIe 1 connected to ULI bridge */
  45 #define CONFIG_PCIE2            1       /* PCIe 2 connected to slot */
  46 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  47 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  48 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  49
  50 #define CONFIG_ENV_OVERWRITE
  51 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  52
  53 #define CONFIG_HIGH_BATS        1       /* High BATs supported & enabled */
  54 #define CONFIG_ALTIVEC          1
  55
  56 /*
  57  * L2CR setup -- make sure this is right for your board!
  58  */
  59 #define CONFIG_SYS_L2
  60 #define L2_INIT         0
  61 #define L2_ENABLE       (L2CR_L2E |0x00100000 )
  62
  63 #ifndef CONFIG_SYS_CLK_FREQ
  64 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  65 #endif
  66
  67 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  68 #define CONFIG_MISC_INIT_R              1
  69
  70 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  71 #define CONFIG_SYS_MEMTEST_END          0x00400000
  72
  73 /*
  74  * Base addresses -- Note these are effective addresses where the
  75  * actual resources get mapped (not physical addresses)
  76  */
  77 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  78 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  79 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  80
  81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  82 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  83 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  84
  85 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
  86 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
  87 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
  88
  89 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_CCSRBAR+0x2c000)
  90
  91 /* DDR Setup */
  92 #define CONFIG_FSL_DDR2
  93 #undef CONFIG_FSL_DDR_INTERACTIVE
  94 #define CONFIG_SPD_EEPROM               /* Use SPD for DDR */
  95 #define CONFIG_DDR_SPD
  96
  97 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  98 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  99
 100 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 101 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 102 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 103 #define CONFIG_VERY_BIG_RAM
 104
 105 #define CONFIG_NUM_DDR_CONTROLLERS      1
 106 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 107 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 108
 109 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 110
 111 /* These are used when DDR doesn't use SPD.  */
 112 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 113
 114 #if 0 /* TODO */
 115 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 116 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 117 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 118 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 119 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 120 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 121 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 122 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 123 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 124 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 125 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 126 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 127 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 128 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 129 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 130
 131 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 132 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 133 #define CONFIG_SYS_DDR_SBE              0x000f0000
 134
 135 #endif
 136
 137
 138 #define CONFIG_ID_EEPROM
 139 #define CONFIG_SYS_I2C_EEPROM_NXID
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 143
 144
 145 #define CONFIG_SYS_FLASH_BASE           0xf0000000 /* start of FLASH 128M */
 146 #define CONFIG_SYS_FLASH_BASE2          0xf8000000
 147
 148 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 149
 150 #define CONFIG_SYS_BR0_PRELIM           0xf8001001 /* port size 16bit */
 151 #define CONFIG_SYS_OR0_PRELIM           0xf8006e65 /* 128MB NOR Flash*/
 152
 153 #define CONFIG_SYS_BR1_PRELIM           0xf0001001 /* port size 16bit */
 154 #define CONFIG_SYS_OR1_PRELIM           0xf8006e65 /* 128MB Promjet */
 155 #if 0 /* TODO */
 156 #define CONFIG_SYS_BR2_PRELIM           0xf0000000
 157 #define CONFIG_SYS_OR2_PRELIM           0xf0000000 /* 256MB NAND Flash - bank 1 */
 158 #endif
 159 #define CONFIG_SYS_BR3_PRELIM           0xe8000801 /* port size 8bit */
 160 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7 /* 1MB PIXIS area*/
 161
 162
 163 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 164 #define PIXIS_BASE      0xe8000000      /* PIXIS registers */
 165 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 166 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 167 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 168 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 169 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch */
 170 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 171 #define PIXIS_BRDCFG0           0x8     /* PIXIS Board Configuration Register0*/
 172 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 173 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 174 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 175 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 176 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 177 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 178 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 179 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 180 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x0C    /* Reset altbank mask*/
 181
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 184
 185 #undef  CONFIG_SYS_FLASH_CHECKSUM
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 188 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 189 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 190
 191 #define CONFIG_FLASH_CFI_DRIVER
 192 #define CONFIG_SYS_FLASH_CFI
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO
 194
 195 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 196 #define CONFIG_SYS_RAMBOOT
 197 #else
 198 #undef  CONFIG_SYS_RAMBOOT
 199 #endif
 200
 201 #if defined(CONFIG_SYS_RAMBOOT)
 202 #undef CONFIG_SPD_EEPROM
 203 #define CONFIG_SYS_SDRAM_SIZE   256
 204 #endif
 205
 206 #undef CONFIG_CLOCKS_IN_MHZ
 207
 208 #define CONFIG_SYS_INIT_RAM_LOCK        1
 209 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 210 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 211 #else
 212 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4000000      /* Initial RAM address */
 213 #endif
 214 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 215
 216 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 218 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 219
 220 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 221 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 222
 223 /* Serial Port */
 224 #define CONFIG_CONS_INDEX       1
 225 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 226 #define CONFIG_SYS_NS16550
 227 #define CONFIG_SYS_NS16550_SERIAL
 228 #define CONFIG_SYS_NS16550_REG_SIZE     1
 229 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 230
 231 #define CONFIG_SYS_BAUDRATE_TABLE \
 232         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 233
 234 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 235 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 236
 237 /* Use the HUSH parser */
 238 #define CONFIG_SYS_HUSH_PARSER
 239 #ifdef  CONFIG_SYS_HUSH_PARSER
 240 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 241 #endif
 242
 243 /*
 244  * Pass open firmware flat tree to kernel
 245  */
 246 #define CONFIG_OF_LIBFDT                1
 247 #define CONFIG_OF_BOARD_SETUP           1
 248 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 249
 250
 251 /* maximum size of the flat tree (8K) */
 252 #define OF_FLAT_TREE_MAX_SIZE   8192
 253
 254 #define CONFIG_SYS_64BIT_VSPRINTF       1
 255 #define CONFIG_SYS_64BIT_STRTOUL        1
 256
 257 /*
 258  * I2C
 259  */
 260 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 261 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 262 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 263 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 264 #define CONFIG_SYS_I2C_SLAVE            0x7F
 265 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 266 #define CONFIG_SYS_I2C_OFFSET           0x3000
 267
 268 /*
 269  * General PCI
 270  * Addresses are mapped 1-1.
 271  */
 272 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 273 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 274 #define CONFIG_SYS_PCI1_MEM_VIRT        CONFIG_SYS_PCI1_MEM_BUS
 275 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 276 #define CONFIG_SYS_PCI1_IO_BUS  0x0000000
 277 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 278 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 279 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 280
 281 /* controller 1, Base address 0xa000 */
 282 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 283 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 284 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 285 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 286 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 287 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /* 1M */
 288
 289 /* controller 2, Base Address 0x9000 */
 290 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 291 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 292 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 293 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000      /* reuse mem LAW */
 294 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe2000000
 295 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00100000      /* 1M */
 296
 297
 298 #if defined(CONFIG_PCI)
 299
 300 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 301
 302 #define CONFIG_NET_MULTI
 303 #define CONFIG_CMD_NET
 304 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 305 #define CONFIG_CMD_REGINFO
 306
 307 #define CONFIG_ULI526X
 308 #ifdef CONFIG_ULI526X
 309 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 310 #endif
 311
 312 /************************************************************
 313  * USB support
 314  ************************************************************/
 315 #define CONFIG_PCI_OHCI         1
 316 #define CONFIG_USB_OHCI_NEW             1
 317 #define CONFIG_USB_KEYBOARD     1
 318 #define CONFIG_SYS_STDIO_DEREGISTER
 319 #define CONFIG_SYS_USB_EVENT_POLL       1
 320 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 321 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 322 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 323
 324 #if !defined(CONFIG_PCI_PNP)
 325 #define PCI_ENET0_IOADDR        0xe0000000
 326 #define PCI_ENET0_MEMADDR       0xe0000000
 327 #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 328 #endif
 329
 330 #define CONFIG_DOS_PARTITION
 331 #define CONFIG_SCSI_AHCI
 332
 333 #ifdef CONFIG_SCSI_AHCI
 334 #define CONFIG_SATA_ULI5288
 335 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 336 #define CONFIG_SYS_SCSI_MAX_LUN 1
 337 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 338 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 339 #endif
 340
 341 #endif  /* CONFIG_PCI */
 342
 343 /*
 344  * BAT0         2G      Cacheable, non-guarded
 345  * 0x0000_0000  2G      DDR
 346  */
 347 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 348 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 349 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 350 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 351
 352 /*
 353  * BAT1         1G      Cache-inhibited, guarded
 354  * 0x8000_0000  256M    PCI-1 Memory
 355  * 0xa000_0000  256M    PCI-Express 1 Memory
 356  * 0x9000_0000  256M    PCI-Express 2 Memory
 357  */
 358
 359 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 360                         | BATL_GUARDEDSTORAGE)
 361 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 362 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 363 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 364
 365 /*
 366  * BAT2         16M     Cache-inhibited, guarded
 367  * 0xe100_0000  1M      PCI-1 I/O
 368  */
 369
 370 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 371                         | BATL_GUARDEDSTORAGE)
 372 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 373 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 374 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 375
 376 /*
 377  * BAT3         4M      Cache-inhibited, guarded
 378  * 0xe000_0000  4M      CCSR
 379  */
 380
 381 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 382                         | BATL_GUARDEDSTORAGE)
 383 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
 384 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 385 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 386
 387 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 388 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 389                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 390                                        | BATL_GUARDEDSTORAGE)
 391 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 392                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 393 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 394                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 395 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 396 #endif
 397
 398 /*
 399  * BAT4         32M     Cache-inhibited, guarded
 400  * 0xe200_0000  1M      PCI-Express 2 I/O
 401  * 0xe300_0000  1M      PCI-Express 1 I/O
 402  */
 403
 404 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 405                         | BATL_GUARDEDSTORAGE)
 406 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 407 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 408 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 409
 410
 411 /*
 412  * BAT5         128K    Cacheable, non-guarded
 413  * 0xe400_0000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 414  */
 415 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 416 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 417 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 418 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 419
 420 /*
 421  * BAT6         256M    Cache-inhibited, guarded
 422  * 0xf000_0000  256M    FLASH
 423  */
 424 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE   | BATL_PP_RW | BATL_CACHEINHIBIT \
 425                         | BATL_GUARDEDSTORAGE)
 426 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE   | BATU_BL_256M | BATU_VS | BATU_VP)
 427 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 428 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 429
 430 /* Map the last 1M of flash where we're running from reset */
 431 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 432                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 433 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 434 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 435                                  | BATL_MEMCOHERENCE)
 436 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 437
 438 /*
 439  * BAT7         4M      Cache-inhibited, guarded
 440  * 0xe800_0000  4M      PIXIS
 441  */
 442 #define CONFIG_SYS_DBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 443                         | BATL_GUARDEDSTORAGE)
 444 #define CONFIG_SYS_DBAT7U       (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 445 #define CONFIG_SYS_IBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 446 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 447
 448
 449 /*
 450  * Environment
 451  */
 452 #ifndef CONFIG_SYS_RAMBOOT
 453 #define CONFIG_ENV_IS_IN_FLASH  1
 454 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 455 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 126k (one sector) for env */
 456 #define CONFIG_ENV_SIZE         0x2000
 457 #else
 458 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 459 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 460 #define CONFIG_ENV_SIZE         0x2000
 461 #endif
 462
 463 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 465
 466
 467 /*
 468  * BOOTP options
 469  */
 470 #define CONFIG_BOOTP_BOOTFILESIZE
 471 #define CONFIG_BOOTP_BOOTPATH
 472 #define CONFIG_BOOTP_GATEWAY
 473 #define CONFIG_BOOTP_HOSTNAME
 474
 475
 476 /*
 477  * Command line configuration.
 478  */
 479 #include <config_cmd_default.h>
 480
 481 #define CONFIG_CMD_PING
 482 #define CONFIG_CMD_I2C
 483 #define CONFIG_CMD_MII
 484
 485 #if defined(CONFIG_SYS_RAMBOOT)
 486 #undef CONFIG_CMD_SAVEENV
 487 #endif
 488
 489 #if defined(CONFIG_PCI)
 490 #define CONFIG_CMD_PCI
 491 #define CONFIG_CMD_SCSI
 492 #define CONFIG_CMD_EXT2
 493 #define CONFIG_CMD_USB
 494 #endif
 495
 496
 497 #define CONFIG_WATCHDOG                 /* watchdog enabled */
 498 #define CONFIG_SYS_WATCHDOG_FREQ        5000    /* Feed interval, 5s */
 499
 500 /*DIU Configuration*/
 501 #define DIU_CONNECT_TO_DVI              /* DIU controller connects to DVI encoder*/
 502
 503 /*
 504  * Miscellaneous configurable options
 505  */
 506 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 507 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 508 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 509 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 510
 511 #if defined(CONFIG_CMD_KGDB)
 512 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 513 #else
 514 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 515 #endif
 516
 517 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 518 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 519 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 520 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 521
 522 /*
 523  * For booting Linux, the board info and command line data
 524  * have to be in the first 8 MB of memory, since this is
 525  * the maximum mapped by the Linux kernel during initialization.
 526  */
 527 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 528
 529 /*
 530  * Internal Definitions
 531  *
 532  * Boot Flags
 533  */
 534 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 535 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 536
 537 #if defined(CONFIG_CMD_KGDB)
 538 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 539 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 540 #endif
 541
 542 /*
 543  * Environment Configuration
 544  */
 545 #define CONFIG_IPADDR           192.168.1.100
 546
 547 #define CONFIG_HOSTNAME         unknown
 548 #define CONFIG_ROOTPATH         /opt/nfsroot
 549 #define CONFIG_BOOTFILE         uImage
 550 #define CONFIG_UBOOTPATH        8610hpcd/u-boot.bin
 551
 552 #define CONFIG_SERVERIP         192.168.1.1
 553 #define CONFIG_GATEWAYIP        192.168.1.1
 554 #define CONFIG_NETMASK          255.255.255.0
 555
 556 /* default location for tftp and bootm */
 557 #define CONFIG_LOADADDR         1000000
 558
 559 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 560 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 561
 562 #define CONFIG_BAUDRATE 115200
 563
 564 #if defined(CONFIG_PCI1)
 565 #define PCI_ENV \
 566  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 567         "echo e;md ${a}e00 9\0" \
 568  "pci1regs=setenv a e0008; run pcireg\0" \
 569  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 570         "pci d.w $b.0 56 1\0" \
 571  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
 572         "pci w.w $b.0 56 ffff\0"        \
 573  "pci1err=setenv a e0008; run pcierr\0" \
 574  "pci1errc=setenv a e0008; run pcierrc\0"
 575 #else
 576 #define PCI_ENV ""
 577 #endif
 578
 579 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
 580 #define PCIE_ENV \
 581  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 582         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 583  "pcie1regs=setenv a e000a; run pciereg\0"      \
 584  "pcie2regs=setenv a e0009; run pciereg\0"      \
 585  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
 586         "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"        \
 587         "pci d $b.0 130 1\0" \
 588  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
 589         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
 590         "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"            \
 591  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 592  "pcie1err=setenv a e000a; run pcieerr\0"       \
 593  "pcie2err=setenv a e0009; run pcieerr\0"       \
 594  "pcie1errc=setenv a e000a; run pcieerrc\0"     \
 595  "pcie2errc=setenv a e0009; run pcieerrc\0"
 596 #else
 597 #define PCIE_ENV ""
 598 #endif
 599
 600 #define DMA_ENV \
 601  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
 602         "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
 603  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
 604         "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
 605  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
 606         "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
 607  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 608         "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 609
 610 #ifdef ENV_DEBUG
 611 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 612  "netdev=eth0\0"                                                \
 613  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 614  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 615         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 616         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 617         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 618         "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
 619         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 620  "consoledev=ttyS0\0"                                           \
 621  "ramdiskaddr=2000000\0"                                        \
 622  "ramdiskfile=8610hpcd/ramdisk.uboot\0"                         \
 623  "fdtaddr=c00000\0"                                             \
 624  "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                          \
 625  "bdev=sda3\0"                                  \
 626  "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 627  "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 628  "maxcpus=1"    \
 629  "eoi=mw e00400b0 0\0"                                          \
 630  "iack=md e00400a0 1\0"                                         \
 631  "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
 632         "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
 633         "md ${a}f00 5\0" \
 634  "ddr1regs=setenv a e0002; run ddrreg\0" \
 635  "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
 636         "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
 637         "md ${a}e60 1; md ${a}ef0 1d\0" \
 638  "guregs=setenv a e00e0; run gureg\0" \
 639  "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
 640  "mcmregs=setenv a e0001; run mcmreg\0" \
 641  "diuregs=md e002c000 1d\0" \
 642  "dium=mw e002c01c\0" \
 643  "diuerr=md e002c014 1\0" \
 644  "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
 645  "monitor=0-DVI\0" \
 646  "pmregs=md e00e1000 2b\0" \
 647  "lawregs=md e0000c08 4b\0" \
 648  "lbcregs=md e0005000 36\0" \
 649  "dma0regs=md e0021100 12\0" \
 650  "dma1regs=md e0021180 12\0" \
 651  "dma2regs=md e0021200 12\0" \
 652  "dma3regs=md e0021280 12\0" \
 653  PCI_ENV \
 654  PCIE_ENV \
 655  DMA_ENV
 656 #else
 657 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 658  "netdev=eth0\0"                                                \
 659  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 660  "consoledev=ttyS0\0"                                           \
 661  "ramdiskaddr=2000000\0"                                        \
 662  "ramdiskfile=8610hpcd/ramdisk.uboot\0"                         \
 663  "fdtaddr=c00000\0"                                             \
 664  "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                          \
 665  "bdev=sda3\0"                                                  \
 666  "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
 667  "monitor=0-DVI\0"
 668 #endif
 669
 670 #define CONFIG_NFSBOOTCOMMAND                                   \
 671  "setenv bootargs root=/dev/nfs rw "                            \
 672         "nfsroot=$serverip:$rootpath "                          \
 673         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 674         "console=$consoledev,$baudrate $othbootargs;"           \
 675  "tftp $loadaddr $bootfile;"                                    \
 676  "tftp $fdtaddr $fdtfile;"                                      \
 677  "bootm $loadaddr - $fdtaddr"
 678
 679 #define CONFIG_RAMBOOTCOMMAND \
 680  "setenv bootargs root=/dev/ram rw "                            \
 681         "console=$consoledev,$baudrate $othbootargs;"           \
 682  "tftp $ramdiskaddr $ramdiskfile;"                              \
 683  "tftp $loadaddr $bootfile;"                                    \
 684  "tftp $fdtaddr $fdtfile;"                                      \
 685  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 686
 687 #define CONFIG_BOOTCOMMAND              \
 688  "setenv bootargs root=/dev/$bdev rw "  \
 689         "console=$consoledev,$baudrate $othbootargs;"   \
 690  "tftp $loadaddr $bootfile;"            \
 691  "tftp $fdtaddr $fdtfile;"              \
 692  "bootm $loadaddr - $fdtaddr"
 693
 694 #endif  /* __CONFIG_H */