include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  40 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  41 /*#define CONFIG_PHYS_64BIT     1*/     /* Place devices in 36-bit space */
  42 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  43
  44 #ifdef RUN_DIAG
  45 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  46 #endif
  47
  48 /*
  49  * virtual address to be used for temporary mappings.  There
  50  * should be 128k free at this VA.
  51  */
  52 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  53
  54 /*
  55  * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
  56  */
  57 /*#define CONFIG_RIO            1*/
  58
  59 #ifndef CONFIG_RIO                      /* RIO/PCI are mutually exclusive */
  60 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  61 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  62 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  63 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  64 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  65 #endif
  66 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  67
  68 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  72 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  73
  74 #define CONFIG_ALTIVEC          1
  75
  76 /*
  77  * L2CR setup -- make sure this is right for your board!
  78  */
  79 #define CONFIG_SYS_L2
  80 #define L2_INIT         0
  81 #define L2_ENABLE       (L2CR_L2E)
  82
  83 #ifndef CONFIG_SYS_CLK_FREQ
  84 #ifndef __ASSEMBLY__
  85 extern unsigned long get_board_sys_clk(unsigned long dummy);
  86 #endif
  87 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  88 #endif
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  91
  92 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  93 #define CONFIG_SYS_MEMTEST_END          0x00400000
  94
  95 /*
  96  * With the exception of PCI Memory and Rapid IO, most devices will simply
  97  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  98  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  99  */
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
 102 #else
 103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
 104 #endif
 105
 106 /*
 107  * Base addresses -- Note these are effective addresses where the
 108  * actual resources get mapped (not physical addresses)
 109  */
 110 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 111 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 112 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 113
 114 /* Physical addresses */
 115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0xf
 118 #define CONFIG_SYS_CCSRBAR_PHYS         (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 119                                          | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
 120 #else
 121 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
 122 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
 123 #endif
 124
 125 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
 126 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR+0x9000)
 127
 128 /*
 129  * DDR Setup
 130  */
 131 #define CONFIG_FSL_DDR2
 132 #undef CONFIG_FSL_DDR_INTERACTIVE
 133 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 134 #define CONFIG_DDR_SPD
 135
 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 137 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 138
 139 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 140 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 141 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 142 #define CONFIG_VERY_BIG_RAM
 143
 144 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 145
 146 #define CONFIG_NUM_DDR_CONTROLLERS      2
 147 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 148 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 149
 150 /*
 151  * I2C addresses of SPD EEPROMs
 152  */
 153 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 154 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 155 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 156 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 157
 158
 159 /*
 160  * These are used when DDR doesn't use SPD.
 161  */
 162 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 163 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 164 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 165 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 166 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 167 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 168 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 169 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 170 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 171 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 172 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 173 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 174 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 175 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 176 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 177 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 178
 179 #define CONFIG_ID_EEPROM
 180 #define CONFIG_SYS_I2C_EEPROM_NXID
 181 #define CONFIG_ID_EEPROM
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 184
 185 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      (CONFIG_SYS_FLASH_BASE \
 187                                          | CONFIG_SYS_PHYS_ADDR_HIGH)
 188
 189 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 190
 191 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 192                                  | 0x00001001)  /* port size 16bit */
 193 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 194
 195 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 196                                  | 0x00001001)  /* port size 16bit */
 197 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 198
 199 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 200                                  | 0x00000801) /* port size 8bit */
 201 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 202
 203 /*
 204  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 205  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 206  * required for the smallest BAT mapping, so there's a 64k hole.
 207  */
 208 #define CONFIG_SYS_LBC_BASE             0xffde0000
 209 #define CONFIG_SYS_LBC_BASE_PHYS        (CONFIG_SYS_LBC_BASE \
 210                                          | CONFIG_SYS_PHYS_ADDR_HIGH)
 211
 212 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 213 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 214 #define PIXIS_BASE_PHYS         (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
 215 #define PIXIS_SIZE              0x00008000      /* 32k */
 216 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 217 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 218 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 219 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 220 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 221 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 222 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 223 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 224 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 225 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 226 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 227 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 228 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 229 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 230 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 231
 232 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 233 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 234 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 235
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 237 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 238
 239 #undef  CONFIG_SYS_FLASH_CHECKSUM
 240 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 241 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 242 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE       /* start of monitor */
 243 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 244
 245 #define CONFIG_FLASH_CFI_DRIVER
 246 #define CONFIG_SYS_FLASH_CFI
 247 #define CONFIG_SYS_FLASH_EMPTY_INFO
 248
 249 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 250 #define CONFIG_SYS_RAMBOOT
 251 #else
 252 #undef  CONFIG_SYS_RAMBOOT
 253 #endif
 254
 255 #if defined(CONFIG_SYS_RAMBOOT)
 256 #undef CONFIG_SPD_EEPROM
 257 #define CONFIG_SYS_SDRAM_SIZE   256
 258 #endif
 259
 260 #undef CONFIG_CLOCKS_IN_MHZ
 261
 262 #define CONFIG_SYS_INIT_RAM_LOCK        1
 263 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 264 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 265 #else
 266 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 267 #endif
 268 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 269
 270 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 271 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 272 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 273
 274 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 275 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 276
 277 /* Serial Port */
 278 #define CONFIG_CONS_INDEX     1
 279 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 280 #define CONFIG_SYS_NS16550
 281 #define CONFIG_SYS_NS16550_SERIAL
 282 #define CONFIG_SYS_NS16550_REG_SIZE     1
 283 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 284
 285 #define CONFIG_SYS_BAUDRATE_TABLE  \
 286         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 287
 288 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 289 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 290
 291 /* Use the HUSH parser */
 292 #define CONFIG_SYS_HUSH_PARSER
 293 #ifdef  CONFIG_SYS_HUSH_PARSER
 294 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 295 #endif
 296
 297 /*
 298  * Pass open firmware flat tree to kernel
 299  */
 300 #define CONFIG_OF_LIBFDT                1
 301 #define CONFIG_OF_BOARD_SETUP           1
 302 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 303
 304
 305 #define CONFIG_SYS_64BIT_VSPRINTF       1
 306 #define CONFIG_SYS_64BIT_STRTOUL        1
 307
 308 /*
 309  * I2C
 310  */
 311 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 312 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 313 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 314 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 315 #define CONFIG_SYS_I2C_SLAVE            0x7F
 316 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 317 #define CONFIG_SYS_I2C_OFFSET           0x3100
 318
 319 /*
 320  * RapidIO MMU
 321  */
 322 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000      /* base address */
 323 #ifdef CONFIG_PHYS_64BIT
 324 #define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
 325 #else
 326 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 327 #endif
 328 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 329
 330 /*
 331  * General PCI
 332  * Addresses are mapped 1-1.
 333  */
 334
 335 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 336 #ifdef CONFIG_PHYS_64BIT
 337 #define CONFIG_SYS_PCI1_MEM_BUS         0xc0000000
 338 #define CONFIG_SYS_PCI1_MEM_PHYS        0x0000000c00000000ULL
 339 #else
 340 #define CONFIG_SYS_PCI1_MEM_BUS         CONFIG_SYS_PCI1_MEM_VIRT
 341 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_VIRT
 342 #endif
 343 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 344 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 345 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
 346 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
 347                                  | CONFIG_SYS_PHYS_ADDR_HIGH)
 348 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64K */
 349
 350 /* For RTL8139 */
 351 #define KSEG1ADDR(x)            ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 352 #define _IO_BASE                0x00000000
 353
 354 #ifdef CONFIG_PHYS_64BIT
 355 /*
 356  * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
 357  * This will increase the amount of PCI address space available for
 358  * for mapping RAM.
 359  */
 360 #define CONFIG_SYS_PCI2_MEM_BUS         CONFIG_SYS_PCI1_MEM_BUS
 361 #else
 362 #define CONFIG_SYS_PCI2_MEM_BUS         (CONFIG_SYS_PCI1_MEM_BUS \
 363                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 364 #endif
 365 #define CONFIG_SYS_PCI2_MEM_VIRT        (CONFIG_SYS_PCI1_MEM_VIRT \
 366                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 367 #define CONFIG_SYS_PCI2_MEM_PHYS        (CONFIG_SYS_PCI1_MEM_PHYS \
 368                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 369 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 370 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 371 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
 372                                  + CONFIG_SYS_PCI1_IO_SIZE)
 373 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
 374                                  + CONFIG_SYS_PCI1_IO_SIZE)
 375 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
 376
 377 #if defined(CONFIG_PCI)
 378
 379 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 380
 381 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 382
 383 #define CONFIG_NET_MULTI
 384 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 385
 386 #define CONFIG_RTL8139
 387
 388 #undef CONFIG_EEPRO100
 389 #undef CONFIG_TULIP
 390
 391 /************************************************************
 392  * USB support
 393  ************************************************************/
 394 #define CONFIG_PCI_OHCI                 1
 395 #define CONFIG_USB_OHCI_NEW             1
 396 #define CONFIG_USB_KEYBOARD             1
 397 #define CONFIG_SYS_DEVICE_DEREGISTER
 398 #define CONFIG_SYS_USB_EVENT_POLL               1
 399 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 400 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 401 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 402
 403 /*PCIE video card used*/
 404 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCI2_IO_VIRT
 405
 406 /*PCI video card used*/
 407 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 408
 409 /* video */
 410 #define CONFIG_VIDEO
 411
 412 #if defined(CONFIG_VIDEO)
 413 #define CONFIG_BIOSEMU
 414 #define CONFIG_CFB_CONSOLE
 415 #define CONFIG_VIDEO_SW_CURSOR
 416 #define CONFIG_VGA_AS_SINGLE_DEVICE
 417 #define CONFIG_ATI_RADEON_FB
 418 #define CONFIG_VIDEO_LOGO
 419 /*#define CONFIG_CONSOLE_CURSOR*/
 420 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
 421 #endif
 422
 423 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 424
 425 #define CONFIG_DOS_PARTITION
 426 #define CONFIG_SCSI_AHCI
 427
 428 #ifdef CONFIG_SCSI_AHCI
 429 #define CONFIG_SATA_ULI5288
 430 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 431 #define CONFIG_SYS_SCSI_MAX_LUN 1
 432 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 433 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 434 #endif
 435
 436 #define CONFIG_MPC86XX_PCI2
 437
 438 #endif  /* CONFIG_PCI */
 439
 440 #if defined(CONFIG_TSEC_ENET)
 441
 442 #ifndef CONFIG_NET_MULTI
 443 #define CONFIG_NET_MULTI        1
 444 #endif
 445
 446 #define CONFIG_MII              1       /* MII PHY management */
 447
 448 #define CONFIG_TSEC1            1
 449 #define CONFIG_TSEC1_NAME       "eTSEC1"
 450 #define CONFIG_TSEC2            1
 451 #define CONFIG_TSEC2_NAME       "eTSEC2"
 452 #define CONFIG_TSEC3            1
 453 #define CONFIG_TSEC3_NAME       "eTSEC3"
 454 #define CONFIG_TSEC4            1
 455 #define CONFIG_TSEC4_NAME       "eTSEC4"
 456
 457 #define TSEC1_PHY_ADDR          0
 458 #define TSEC2_PHY_ADDR          1
 459 #define TSEC3_PHY_ADDR          2
 460 #define TSEC4_PHY_ADDR          3
 461 #define TSEC1_PHYIDX            0
 462 #define TSEC2_PHYIDX            0
 463 #define TSEC3_PHYIDX            0
 464 #define TSEC4_PHYIDX            0
 465 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 466 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 467 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 468 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 469
 470 #define CONFIG_ETHPRIME         "eTSEC1"
 471
 472 #endif  /* CONFIG_TSEC_ENET */
 473
 474 /*  Contort an addr into the format needed for BATs */
 475 #ifdef CONFIG_PHYS_64BIT
 476 #define BAT_PHYS_ADDR(x)         ((unsigned long) \
 477                                   ((x & 0x00000000ffffffffULL) |        \
 478                                    ((x & 0x0000000e00000000ULL) >> 24) | \
 479                                    ((x & 0x0000000100000000ULL) >> 30)))
 480 #else
 481 #define BAT_PHYS_ADDR(x)        (x)
 482 #endif
 483
 484
 485 /* Put high physical address bits into the BAT format */
 486 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 487 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 488
 489 /*
 490  * BAT0         DDR
 491  */
 492 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 493 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 494 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 495 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 496
 497 /*
 498  * BAT1         LBC (PIXIS/CF)
 499  */
 500 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
 501                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 502                                  BATL_GUARDEDSTORAGE)
 503 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 504                                  | BATU_VS | BATU_VP)
 505 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
 506                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 507 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 508
 509 /* if CONFIG_PCI:
 510  * BAT2         PCI1 and PCI1 MEM
 511  * if CONFIG_RIO
 512  * BAT2         Rapidio Memory
 513  */
 514 #ifdef CONFIG_PCI
 515 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
 516                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 517                                  | BATL_GUARDEDSTORAGE)
 518 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
 519                                  | BATU_VS | BATU_VP)
 520 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
 521                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 522 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 523 #else /* CONFIG_RIO */
 524 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
 525                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 526                                  BATL_GUARDEDSTORAGE)
 527 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
 528                                  | BATU_VS | BATU_VP)
 529 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
 530                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 531
 532 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 533                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 534 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 535 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 536 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 537 #endif
 538
 539 /*
 540  * BAT3         CCSR Space
 541  * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
 542  * instead.  The assembler chokes on ULL.
 543  */
 544 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 545                                  | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 546                                  | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 547                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 548                                  | BATL_GUARDEDSTORAGE)
 549 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 550                                  | BATU_VP)
 551 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 552                                  | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 553                                  | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 554                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 555 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 556
 557 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 558 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 559                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 560                                        | BATL_GUARDEDSTORAGE)
 561 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 562                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 563 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 564                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 565 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 566 #endif
 567
 568 /*
 569  * BAT4         PCI1_IO and PCI2_IO
 570  */
 571 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
 572                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 573                                  | BATL_GUARDEDSTORAGE)
 574 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
 575                                  | BATU_VS | BATU_VP)
 576 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
 577                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 578 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 579
 580 /*
 581  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 582  */
 583 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 584 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 585 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 586 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 587
 588 /*
 589  * BAT6         FLASH
 590  */
 591 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 592                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 593                                  | BATL_GUARDEDSTORAGE)
 594 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 595                                  | BATU_VP)
 596 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 597                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 598 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 599
 600 /* Map the last 1M of flash where we're running from reset */
 601 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 602                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 603 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 604 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 605                                  | BATL_MEMCOHERENCE)
 606 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 607
 608 /*
 609  * BAT7         FREE - used later for tmp mappings
 610  */
 611 #define CONFIG_SYS_DBAT7L 0x00000000
 612 #define CONFIG_SYS_DBAT7U 0x00000000
 613 #define CONFIG_SYS_IBAT7L 0x00000000
 614 #define CONFIG_SYS_IBAT7U 0x00000000
 615
 616 /*
 617  * Environment
 618  */
 619 #ifndef CONFIG_SYS_RAMBOOT
 620     #define CONFIG_ENV_IS_IN_FLASH      1
 621     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE + 0x60000)
 622     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 623 #else
 624     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 625     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 626 #endif
 627 #define CONFIG_ENV_SIZE         0x2000
 628
 629 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 630 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 631
 632
 633 /*
 634  * BOOTP options
 635  */
 636 #define CONFIG_BOOTP_BOOTFILESIZE
 637 #define CONFIG_BOOTP_BOOTPATH
 638 #define CONFIG_BOOTP_GATEWAY
 639 #define CONFIG_BOOTP_HOSTNAME
 640
 641
 642 /*
 643  * Command line configuration.
 644  */
 645 #include <config_cmd_default.h>
 646
 647 #define CONFIG_CMD_PING
 648 #define CONFIG_CMD_I2C
 649 #define CONFIG_CMD_REGINFO
 650
 651 #if defined(CONFIG_SYS_RAMBOOT)
 652     #undef CONFIG_CMD_ENV
 653 #endif
 654
 655 #if defined(CONFIG_PCI)
 656     #define CONFIG_CMD_PCI
 657     #define CONFIG_CMD_SCSI
 658     #define CONFIG_CMD_EXT2
 659     #define CONFIG_CMD_USB
 660 #endif
 661
 662
 663 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 664
 665 /*
 666  * Miscellaneous configurable options
 667  */
 668 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 669 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 670 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 671 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 672
 673 #if defined(CONFIG_CMD_KGDB)
 674     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 675 #else
 676     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 677 #endif
 678
 679 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 680 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 681 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 682 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 683
 684 /*
 685  * For booting Linux, the board info and command line data
 686  * have to be in the first 8 MB of memory, since this is
 687  * the maximum mapped by the Linux kernel during initialization.
 688  */
 689 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 690
 691 /*
 692  * Internal Definitions
 693  *
 694  * Boot Flags
 695  */
 696 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 697 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 698
 699 #if defined(CONFIG_CMD_KGDB)
 700     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 701     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 702 #endif
 703
 704 /*
 705  * Environment Configuration
 706  */
 707
 708 /* The mac addresses for all ethernet interface */
 709 #if defined(CONFIG_TSEC_ENET)
 710 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 711 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 712 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 713 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 714 #endif
 715
 716 #define CONFIG_HAS_ETH0         1
 717 #define CONFIG_HAS_ETH1         1
 718 #define CONFIG_HAS_ETH2         1
 719 #define CONFIG_HAS_ETH3         1
 720
 721 #define CONFIG_IPADDR           192.168.1.100
 722
 723 #define CONFIG_HOSTNAME         unknown
 724 #define CONFIG_ROOTPATH         /opt/nfsroot
 725 #define CONFIG_BOOTFILE         uImage
 726 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 727
 728 #define CONFIG_SERVERIP         192.168.1.1
 729 #define CONFIG_GATEWAYIP        192.168.1.1
 730 #define CONFIG_NETMASK          255.255.255.0
 731
 732 /* default location for tftp and bootm */
 733 #define CONFIG_LOADADDR         1000000
 734
 735 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 736 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 737
 738 #define CONFIG_BAUDRATE 115200
 739
 740 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 741         "netdev=eth0\0"                                                 \
 742         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 743         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 744                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 745                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 746                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 747                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 748                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 749         "consoledev=ttyS0\0"                                            \
 750         "ramdiskaddr=2000000\0"                                         \
 751         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 752         "fdtaddr=c00000\0"                                              \
 753         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 754         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 755         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 756         "maxcpus=2"
 757
 758
 759 #define CONFIG_NFSBOOTCOMMAND                                           \
 760         "setenv bootargs root=/dev/nfs rw "                             \
 761               "nfsroot=$serverip:$rootpath "                            \
 762               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 763               "console=$consoledev,$baudrate $othbootargs;"             \
 764         "tftp $loadaddr $bootfile;"                                     \
 765         "tftp $fdtaddr $fdtfile;"                                       \
 766         "bootm $loadaddr - $fdtaddr"
 767
 768 #define CONFIG_RAMBOOTCOMMAND                                           \
 769         "setenv bootargs root=/dev/ram rw "                             \
 770               "console=$consoledev,$baudrate $othbootargs;"             \
 771         "tftp $ramdiskaddr $ramdiskfile;"                               \
 772         "tftp $loadaddr $bootfile;"                                     \
 773         "tftp $fdtaddr $fdtfile;"                                       \
 774         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 775
 776 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 777
 778 #endif  /* __CONFIG_H */