include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_MP               1       /* support multiple processors */
  40 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  41 /*#define CONFIG_PHYS_64BIT     1*/     /* Place devices in 36-bit space */
  42 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  43
  44 #ifdef RUN_DIAG
  45 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  46 #endif
  47
  48 /*
  49  * virtual address to be used for temporary mappings.  There
  50  * should be 128k free at this VA.
  51  */
  52 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  53
  54 /*
  55  * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
  56  */
  57 /*#define CONFIG_RIO            1*/
  58
  59 #ifndef CONFIG_RIO                      /* RIO/PCI are mutually exclusive */
  60 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  61 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  62 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  63 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  64 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  65 #endif
  66 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  67
  68 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  72 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  73
  74 #define CONFIG_ALTIVEC          1
  75
  76 /*
  77  * L2CR setup -- make sure this is right for your board!
  78  */
  79 #define CONFIG_SYS_L2
  80 #define L2_INIT         0
  81 #define L2_ENABLE       (L2CR_L2E)
  82
  83 #ifndef CONFIG_SYS_CLK_FREQ
  84 #ifndef __ASSEMBLY__
  85 extern unsigned long get_board_sys_clk(unsigned long dummy);
  86 #endif
  87 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  88 #endif
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  91
  92 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  93 #define CONFIG_SYS_MEMTEST_END          0x00400000
  94
  95 /*
  96  * With the exception of PCI Memory and Rapid IO, most devices will simply
  97  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  98  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  99  */
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
 102 #else
 103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
 104 #endif
 105
 106 /*
 107  * Base addresses -- Note these are effective addresses where the
 108  * actual resources get mapped (not physical addresses)
 109  */
 110 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 111 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 112 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 113
 114 /* Physical addresses */
 115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0xf
 118 #define CONFIG_SYS_CCSRBAR_PHYS         (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 119                                          | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
 120 #else
 121 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
 122 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
 123 #endif
 124
 125 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
 126 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR+0x9000)
 127
 128 /*
 129  * DDR Setup
 130  */
 131 #define CONFIG_FSL_DDR2
 132 #undef CONFIG_FSL_DDR_INTERACTIVE
 133 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 134 #define CONFIG_DDR_SPD
 135
 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 137 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 138
 139 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 140 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 141 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 142 #define CONFIG_VERY_BIG_RAM
 143
 144 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 145
 146 #define CONFIG_NUM_DDR_CONTROLLERS      2
 147 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 148 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 149
 150 /*
 151  * I2C addresses of SPD EEPROMs
 152  */
 153 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 154 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 155 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 156 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 157
 158
 159 /*
 160  * These are used when DDR doesn't use SPD.
 161  */
 162 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 163 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 164 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 165 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 166 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 167 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 168 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 169 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 170 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 171 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 172 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 173 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 174 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 175 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 176 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 177 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 178
 179 #define CONFIG_ID_EEPROM
 180 #define CONFIG_SYS_I2C_EEPROM_NXID
 181 #define CONFIG_ID_EEPROM
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 184
 185 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      (CONFIG_SYS_FLASH_BASE \
 187                                          | CONFIG_SYS_PHYS_ADDR_HIGH)
 188
 189 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 190
 191 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 192                                  | 0x00001001)  /* port size 16bit */
 193 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 194
 195 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 196                                  | 0x00001001)  /* port size 16bit */
 197 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 198
 199 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 200                                  | 0x00000801) /* port size 8bit */
 201 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 202
 203 /*
 204  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 205  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 206  * required for the smallest BAT mapping, so there's a 64k hole.
 207  */
 208 #define CONFIG_SYS_LBC_BASE             0xffde0000
 209 #define CONFIG_SYS_LBC_BASE_PHYS        (CONFIG_SYS_LBC_BASE \
 210                                          | CONFIG_SYS_PHYS_ADDR_HIGH)
 211
 212 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 213 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 214 #define PIXIS_BASE_PHYS         (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
 215 #define PIXIS_SIZE              0x00008000      /* 32k */
 216 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 217 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 218 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 219 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 220 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 221 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 222 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 223 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 224 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 225 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 226 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 227 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 228 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 229 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 230 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 231 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 232 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 233
 234 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 235 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 236 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 237
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 239 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 240
 241 #undef  CONFIG_SYS_FLASH_CHECKSUM
 242 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 243 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 244 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE       /* start of monitor */
 245 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 246
 247 #define CONFIG_FLASH_CFI_DRIVER
 248 #define CONFIG_SYS_FLASH_CFI
 249 #define CONFIG_SYS_FLASH_EMPTY_INFO
 250
 251 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 252 #define CONFIG_SYS_RAMBOOT
 253 #else
 254 #undef  CONFIG_SYS_RAMBOOT
 255 #endif
 256
 257 #if defined(CONFIG_SYS_RAMBOOT)
 258 #undef CONFIG_SPD_EEPROM
 259 #define CONFIG_SYS_SDRAM_SIZE   256
 260 #endif
 261
 262 #undef CONFIG_CLOCKS_IN_MHZ
 263
 264 #define CONFIG_SYS_INIT_RAM_LOCK        1
 265 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 266 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 267 #else
 268 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 269 #endif
 270 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 271
 272 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 273 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 274 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 275
 276 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 277 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 278
 279 /* Serial Port */
 280 #define CONFIG_CONS_INDEX     1
 281 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 282 #define CONFIG_SYS_NS16550
 283 #define CONFIG_SYS_NS16550_SERIAL
 284 #define CONFIG_SYS_NS16550_REG_SIZE     1
 285 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 286
 287 #define CONFIG_SYS_BAUDRATE_TABLE  \
 288         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 289
 290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 292
 293 /* Use the HUSH parser */
 294 #define CONFIG_SYS_HUSH_PARSER
 295 #ifdef  CONFIG_SYS_HUSH_PARSER
 296 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 297 #endif
 298
 299 /*
 300  * Pass open firmware flat tree to kernel
 301  */
 302 #define CONFIG_OF_LIBFDT                1
 303 #define CONFIG_OF_BOARD_SETUP           1
 304 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 305
 306
 307 #define CONFIG_SYS_64BIT_VSPRINTF       1
 308 #define CONFIG_SYS_64BIT_STRTOUL        1
 309
 310 /*
 311  * I2C
 312  */
 313 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 314 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 315 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 316 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 317 #define CONFIG_SYS_I2C_SLAVE            0x7F
 318 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 319 #define CONFIG_SYS_I2C_OFFSET           0x3100
 320
 321 /*
 322  * RapidIO MMU
 323  */
 324 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000      /* base address */
 325 #ifdef CONFIG_PHYS_64BIT
 326 #define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
 327 #else
 328 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 329 #endif
 330 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 331
 332 /*
 333  * General PCI
 334  * Addresses are mapped 1-1.
 335  */
 336
 337 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 338 #ifdef CONFIG_PHYS_64BIT
 339 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 340 #define CONFIG_SYS_PCI1_MEM_PHYS        0x0000000c00000000ULL
 341 #else
 342 #define CONFIG_SYS_PCI1_MEM_BUS         CONFIG_SYS_PCI1_MEM_VIRT
 343 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_VIRT
 344 #endif
 345 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 346 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 347 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
 348 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
 349                                  | CONFIG_SYS_PHYS_ADDR_HIGH)
 350 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64K */
 351
 352 #ifdef CONFIG_PHYS_64BIT
 353 /*
 354  * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
 355  * This will increase the amount of PCI address space available for
 356  * for mapping RAM.
 357  */
 358 #define CONFIG_SYS_PCI2_MEM_BUS         CONFIG_SYS_PCI1_MEM_BUS
 359 #else
 360 #define CONFIG_SYS_PCI2_MEM_BUS         (CONFIG_SYS_PCI1_MEM_BUS \
 361                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 362 #endif
 363 #define CONFIG_SYS_PCI2_MEM_VIRT        (CONFIG_SYS_PCI1_MEM_VIRT \
 364                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 365 #define CONFIG_SYS_PCI2_MEM_PHYS        (CONFIG_SYS_PCI1_MEM_PHYS \
 366                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 367 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 368 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 369 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
 370                                  + CONFIG_SYS_PCI1_IO_SIZE)
 371 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
 372                                  + CONFIG_SYS_PCI1_IO_SIZE)
 373 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
 374
 375 #if defined(CONFIG_PCI)
 376
 377 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 378
 379 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 380
 381 #define CONFIG_NET_MULTI
 382 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 383
 384 #define CONFIG_RTL8139
 385
 386 #undef CONFIG_EEPRO100
 387 #undef CONFIG_TULIP
 388
 389 /************************************************************
 390  * USB support
 391  ************************************************************/
 392 #define CONFIG_PCI_OHCI                 1
 393 #define CONFIG_USB_OHCI_NEW             1
 394 #define CONFIG_USB_KEYBOARD             1
 395 #define CONFIG_SYS_STDIO_DEREGISTER
 396 #define CONFIG_SYS_USB_EVENT_POLL               1
 397 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 398 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 399 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 400
 401 /*PCIE video card used*/
 402 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCI2_IO_VIRT
 403
 404 /*PCI video card used*/
 405 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 406
 407 /* video */
 408 #define CONFIG_VIDEO
 409
 410 #if defined(CONFIG_VIDEO)
 411 #define CONFIG_BIOSEMU
 412 #define CONFIG_CFB_CONSOLE
 413 #define CONFIG_VIDEO_SW_CURSOR
 414 #define CONFIG_VGA_AS_SINGLE_DEVICE
 415 #define CONFIG_ATI_RADEON_FB
 416 #define CONFIG_VIDEO_LOGO
 417 /*#define CONFIG_CONSOLE_CURSOR*/
 418 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
 419 #endif
 420
 421 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 422
 423 #define CONFIG_DOS_PARTITION
 424 #define CONFIG_SCSI_AHCI
 425
 426 #ifdef CONFIG_SCSI_AHCI
 427 #define CONFIG_SATA_ULI5288
 428 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 429 #define CONFIG_SYS_SCSI_MAX_LUN 1
 430 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 431 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 432 #endif
 433
 434 #define CONFIG_MPC86XX_PCI2
 435
 436 #endif  /* CONFIG_PCI */
 437
 438 #if defined(CONFIG_TSEC_ENET)
 439
 440 #ifndef CONFIG_NET_MULTI
 441 #define CONFIG_NET_MULTI        1
 442 #endif
 443
 444 #define CONFIG_MII              1       /* MII PHY management */
 445
 446 #define CONFIG_TSEC1            1
 447 #define CONFIG_TSEC1_NAME       "eTSEC1"
 448 #define CONFIG_TSEC2            1
 449 #define CONFIG_TSEC2_NAME       "eTSEC2"
 450 #define CONFIG_TSEC3            1
 451 #define CONFIG_TSEC3_NAME       "eTSEC3"
 452 #define CONFIG_TSEC4            1
 453 #define CONFIG_TSEC4_NAME       "eTSEC4"
 454
 455 #define TSEC1_PHY_ADDR          0
 456 #define TSEC2_PHY_ADDR          1
 457 #define TSEC3_PHY_ADDR          2
 458 #define TSEC4_PHY_ADDR          3
 459 #define TSEC1_PHYIDX            0
 460 #define TSEC2_PHYIDX            0
 461 #define TSEC3_PHYIDX            0
 462 #define TSEC4_PHYIDX            0
 463 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 464 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 465 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 466 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 467
 468 #define CONFIG_ETHPRIME         "eTSEC1"
 469
 470 #endif  /* CONFIG_TSEC_ENET */
 471
 472 /*  Contort an addr into the format needed for BATs */
 473 #ifdef CONFIG_PHYS_64BIT
 474 #define BAT_PHYS_ADDR(x)         ((unsigned long) \
 475                                   ((x & 0x00000000ffffffffULL) |        \
 476                                    ((x & 0x0000000e00000000ULL) >> 24) | \
 477                                    ((x & 0x0000000100000000ULL) >> 30)))
 478 #else
 479 #define BAT_PHYS_ADDR(x)        (x)
 480 #endif
 481
 482
 483 /* Put high physical address bits into the BAT format */
 484 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 485 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 486
 487 /*
 488  * BAT0         DDR
 489  */
 490 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 491 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 492 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 493 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 494
 495 /*
 496  * BAT1         LBC (PIXIS/CF)
 497  */
 498 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
 499                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 500                                  BATL_GUARDEDSTORAGE)
 501 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 502                                  | BATU_VS | BATU_VP)
 503 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
 504                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 505 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 506
 507 /* if CONFIG_PCI:
 508  * BAT2         PCI1 and PCI1 MEM
 509  * if CONFIG_RIO
 510  * BAT2         Rapidio Memory
 511  */
 512 #ifdef CONFIG_PCI
 513 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
 514                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 515                                  | BATL_GUARDEDSTORAGE)
 516 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
 517                                  | BATU_VS | BATU_VP)
 518 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
 519                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 520 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 521 #else /* CONFIG_RIO */
 522 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
 523                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 524                                  BATL_GUARDEDSTORAGE)
 525 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
 526                                  | BATU_VS | BATU_VP)
 527 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
 528                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 529
 530 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 531                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 532 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 533 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 534 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 535 #endif
 536
 537 /*
 538  * BAT3         CCSR Space
 539  * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
 540  * instead.  The assembler chokes on ULL.
 541  */
 542 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 543                                  | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 544                                  | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 545                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 546                                  | BATL_GUARDEDSTORAGE)
 547 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 548                                  | BATU_VP)
 549 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 550                                  | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 551                                  | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 552                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 553 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 554
 555 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 556 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 557                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 558                                        | BATL_GUARDEDSTORAGE)
 559 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 560                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 561 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 562                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 563 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 564 #endif
 565
 566 /*
 567  * BAT4         PCI1_IO and PCI2_IO
 568  */
 569 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
 570                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 571                                  | BATL_GUARDEDSTORAGE)
 572 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
 573                                  | BATU_VS | BATU_VP)
 574 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
 575                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 576 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 577
 578 /*
 579  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 580  */
 581 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 582 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 583 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 584 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 585
 586 /*
 587  * BAT6         FLASH
 588  */
 589 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 590                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 591                                  | BATL_GUARDEDSTORAGE)
 592 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 593                                  | BATU_VP)
 594 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 595                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 596 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 597
 598 /* Map the last 1M of flash where we're running from reset */
 599 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 600                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 601 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 602 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 603                                  | BATL_MEMCOHERENCE)
 604 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 605
 606 /*
 607  * BAT7         FREE - used later for tmp mappings
 608  */
 609 #define CONFIG_SYS_DBAT7L 0x00000000
 610 #define CONFIG_SYS_DBAT7U 0x00000000
 611 #define CONFIG_SYS_IBAT7L 0x00000000
 612 #define CONFIG_SYS_IBAT7U 0x00000000
 613
 614 /*
 615  * Environment
 616  */
 617 #ifndef CONFIG_SYS_RAMBOOT
 618     #define CONFIG_ENV_IS_IN_FLASH      1
 619     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE + 0x60000)
 620     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 621 #else
 622     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 623     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 624 #endif
 625 #define CONFIG_ENV_SIZE         0x2000
 626
 627 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 628 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 629
 630
 631 /*
 632  * BOOTP options
 633  */
 634 #define CONFIG_BOOTP_BOOTFILESIZE
 635 #define CONFIG_BOOTP_BOOTPATH
 636 #define CONFIG_BOOTP_GATEWAY
 637 #define CONFIG_BOOTP_HOSTNAME
 638
 639
 640 /*
 641  * Command line configuration.
 642  */
 643 #include <config_cmd_default.h>
 644
 645 #define CONFIG_CMD_PING
 646 #define CONFIG_CMD_I2C
 647 #define CONFIG_CMD_REGINFO
 648
 649 #if defined(CONFIG_SYS_RAMBOOT)
 650     #undef CONFIG_CMD_SAVEENV
 651 #endif
 652
 653 #if defined(CONFIG_PCI)
 654     #define CONFIG_CMD_PCI
 655     #define CONFIG_CMD_SCSI
 656     #define CONFIG_CMD_EXT2
 657     #define CONFIG_CMD_USB
 658 #endif
 659
 660
 661 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 662
 663 /*
 664  * Miscellaneous configurable options
 665  */
 666 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 667 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 668 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 669 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 670
 671 #if defined(CONFIG_CMD_KGDB)
 672     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 673 #else
 674     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 675 #endif
 676
 677 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 678 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 679 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 680 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 681
 682 /*
 683  * For booting Linux, the board info and command line data
 684  * have to be in the first 8 MB of memory, since this is
 685  * the maximum mapped by the Linux kernel during initialization.
 686  */
 687 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 688
 689 /*
 690  * Internal Definitions
 691  *
 692  * Boot Flags
 693  */
 694 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 695 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 696
 697 #if defined(CONFIG_CMD_KGDB)
 698     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 699     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 700 #endif
 701
 702 /*
 703  * Environment Configuration
 704  */
 705
 706 /* The mac addresses for all ethernet interface */
 707 #if defined(CONFIG_TSEC_ENET)
 708 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 709 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 710 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 711 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 712 #endif
 713
 714 #define CONFIG_HAS_ETH0         1
 715 #define CONFIG_HAS_ETH1         1
 716 #define CONFIG_HAS_ETH2         1
 717 #define CONFIG_HAS_ETH3         1
 718
 719 #define CONFIG_IPADDR           192.168.1.100
 720
 721 #define CONFIG_HOSTNAME         unknown
 722 #define CONFIG_ROOTPATH         /opt/nfsroot
 723 #define CONFIG_BOOTFILE         uImage
 724 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 725
 726 #define CONFIG_SERVERIP         192.168.1.1
 727 #define CONFIG_GATEWAYIP        192.168.1.1
 728 #define CONFIG_NETMASK          255.255.255.0
 729
 730 /* default location for tftp and bootm */
 731 #define CONFIG_LOADADDR         1000000
 732
 733 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 734 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 735
 736 #define CONFIG_BAUDRATE 115200
 737
 738 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 739         "netdev=eth0\0"                                                 \
 740         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 741         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 742                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 743                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 744                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 745                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 746                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 747         "consoledev=ttyS0\0"                                            \
 748         "ramdiskaddr=2000000\0"                                         \
 749         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 750         "fdtaddr=c00000\0"                                              \
 751         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 752         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 753         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 754         "maxcpus=2"
 755
 756
 757 #define CONFIG_NFSBOOTCOMMAND                                           \
 758         "setenv bootargs root=/dev/nfs rw "                             \
 759               "nfsroot=$serverip:$rootpath "                            \
 760               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 761               "console=$consoledev,$baudrate $othbootargs;"             \
 762         "tftp $loadaddr $bootfile;"                                     \
 763         "tftp $fdtaddr $fdtfile;"                                       \
 764         "bootm $loadaddr - $fdtaddr"
 765
 766 #define CONFIG_RAMBOOTCOMMAND                                           \
 767         "setenv bootargs root=/dev/ram rw "                             \
 768               "console=$consoledev,$baudrate $othbootargs;"             \
 769         "tftp $ramdiskaddr $ramdiskfile;"                               \
 770         "tftp $loadaddr $bootfile;"                                     \
 771         "tftp $fdtaddr $fdtfile;"                                       \
 772         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 773
 774 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 775
 776 #endif  /* __CONFIG_H */