include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_MP               1       /* support multiple processors */
  40 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  41 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  42 /*#define CONFIG_PHYS_64BIT     1*/     /* Place devices in 36-bit space */
  43 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  44
  45 #ifdef RUN_DIAG
  46 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  47 #endif
  48
  49 /*
  50  * virtual address to be used for temporary mappings.  There
  51  * should be 128k free at this VA.
  52  */
  53 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  54
  55 /*
  56  * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
  57  */
  58 /*#define CONFIG_RIO            1*/
  59
  60 #ifndef CONFIG_RIO                      /* RIO/PCI are mutually exclusive */
  61 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  62 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  63 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  64 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  65 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  66 #endif
  67 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  68
  69 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  70 #define CONFIG_ENV_OVERWRITE
  71
  72 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  73 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  74
  75 #define CONFIG_ALTIVEC          1
  76
  77 /*
  78  * L2CR setup -- make sure this is right for your board!
  79  */
  80 #define CONFIG_SYS_L2
  81 #define L2_INIT         0
  82 #define L2_ENABLE       (L2CR_L2E)
  83
  84 #ifndef CONFIG_SYS_CLK_FREQ
  85 #ifndef __ASSEMBLY__
  86 extern unsigned long get_board_sys_clk(unsigned long dummy);
  87 #endif
  88 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  89 #endif
  90
  91 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  92
  93 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  94 #define CONFIG_SYS_MEMTEST_END          0x00400000
  95
  96 /*
  97  * With the exception of PCI Memory and Rapid IO, most devices will simply
  98  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  99  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
 100  */
 101 #ifdef CONFIG_PHYS_64BIT
 102 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
 103 #else
 104 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
 105 #endif
 106
 107 /*
 108  * Base addresses -- Note these are effective addresses where the
 109  * actual resources get mapped (not physical addresses)
 110  */
 111 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 112 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 113 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 114
 115 /* Physical addresses */
 116 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 117 #ifdef CONFIG_PHYS_64BIT
 118 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0xf
 119 #define CONFIG_SYS_CCSRBAR_PHYS         (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 120                                          | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
 121 #else
 122 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
 123 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
 124 #endif
 125
 126 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
 127 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR+0x9000)
 128
 129 /*
 130  * DDR Setup
 131  */
 132 #define CONFIG_FSL_DDR2
 133 #undef CONFIG_FSL_DDR_INTERACTIVE
 134 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 135 #define CONFIG_DDR_SPD
 136
 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 138 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 139
 140 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 141 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 142 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 143 #define CONFIG_VERY_BIG_RAM
 144
 145 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 146
 147 #define CONFIG_NUM_DDR_CONTROLLERS      2
 148 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 149 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 150
 151 /*
 152  * I2C addresses of SPD EEPROMs
 153  */
 154 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 155 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 156 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 157 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 158
 159
 160 /*
 161  * These are used when DDR doesn't use SPD.
 162  */
 163 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 164 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 165 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 166 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 167 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 168 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 169 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 170 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 171 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 172 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 173 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 174 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 175 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 176 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 177 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 178 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 179
 180 #define CONFIG_ID_EEPROM
 181 #define CONFIG_SYS_I2C_EEPROM_NXID
 182 #define CONFIG_ID_EEPROM
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 185
 186 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 187 #define CONFIG_SYS_FLASH_BASE_PHYS      (CONFIG_SYS_FLASH_BASE \
 188                                          | CONFIG_SYS_PHYS_ADDR_HIGH)
 189
 190 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 191
 192 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 193                                  | 0x00001001)  /* port size 16bit */
 194 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 195
 196 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 197                                  | 0x00001001)  /* port size 16bit */
 198 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 199
 200 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 201                                  | 0x00000801) /* port size 8bit */
 202 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 203
 204 /*
 205  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 206  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 207  * required for the smallest BAT mapping, so there's a 64k hole.
 208  */
 209 #define CONFIG_SYS_LBC_BASE             0xffde0000
 210 #define CONFIG_SYS_LBC_BASE_PHYS        (CONFIG_SYS_LBC_BASE \
 211                                          | CONFIG_SYS_PHYS_ADDR_HIGH)
 212
 213 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 214 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 215 #define PIXIS_BASE_PHYS         (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
 216 #define PIXIS_SIZE              0x00008000      /* 32k */
 217 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 218 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 219 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 220 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 221 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 222 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 223 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 224 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 225 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 226 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 227 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 228 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 229 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 230 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 231 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 232 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 233 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 234
 235 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 236 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 237 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 238
 239 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 240 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 241
 242 #undef  CONFIG_SYS_FLASH_CHECKSUM
 243 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 244 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 245 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE       /* start of monitor */
 246 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 247
 248 #define CONFIG_FLASH_CFI_DRIVER
 249 #define CONFIG_SYS_FLASH_CFI
 250 #define CONFIG_SYS_FLASH_EMPTY_INFO
 251
 252 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 253 #define CONFIG_SYS_RAMBOOT
 254 #else
 255 #undef  CONFIG_SYS_RAMBOOT
 256 #endif
 257
 258 #if defined(CONFIG_SYS_RAMBOOT)
 259 #undef CONFIG_SPD_EEPROM
 260 #define CONFIG_SYS_SDRAM_SIZE   256
 261 #endif
 262
 263 #undef CONFIG_CLOCKS_IN_MHZ
 264
 265 #define CONFIG_SYS_INIT_RAM_LOCK        1
 266 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 267 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 268 #else
 269 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 270 #endif
 271 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 272
 273 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 274 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 275 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 276
 277 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 278 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 279
 280 /* Serial Port */
 281 #define CONFIG_CONS_INDEX     1
 282 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 283 #define CONFIG_SYS_NS16550
 284 #define CONFIG_SYS_NS16550_SERIAL
 285 #define CONFIG_SYS_NS16550_REG_SIZE     1
 286 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 287
 288 #define CONFIG_SYS_BAUDRATE_TABLE  \
 289         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 290
 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 293
 294 /* Use the HUSH parser */
 295 #define CONFIG_SYS_HUSH_PARSER
 296 #ifdef  CONFIG_SYS_HUSH_PARSER
 297 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 298 #endif
 299
 300 /*
 301  * Pass open firmware flat tree to kernel
 302  */
 303 #define CONFIG_OF_LIBFDT                1
 304 #define CONFIG_OF_BOARD_SETUP           1
 305 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 306
 307
 308 #define CONFIG_SYS_64BIT_VSPRINTF       1
 309 #define CONFIG_SYS_64BIT_STRTOUL        1
 310
 311 /*
 312  * I2C
 313  */
 314 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 315 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 316 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 317 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 318 #define CONFIG_SYS_I2C_SLAVE            0x7F
 319 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 320 #define CONFIG_SYS_I2C_OFFSET           0x3100
 321
 322 /*
 323  * RapidIO MMU
 324  */
 325 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000      /* base address */
 326 #ifdef CONFIG_PHYS_64BIT
 327 #define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
 328 #else
 329 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 330 #endif
 331 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 332
 333 /*
 334  * General PCI
 335  * Addresses are mapped 1-1.
 336  */
 337
 338 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 339 #ifdef CONFIG_PHYS_64BIT
 340 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 341 #define CONFIG_SYS_PCI1_MEM_PHYS        0x0000000c00000000ULL
 342 #else
 343 #define CONFIG_SYS_PCI1_MEM_BUS         CONFIG_SYS_PCI1_MEM_VIRT
 344 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_VIRT
 345 #endif
 346 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 347 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 348 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
 349 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
 350                                  | CONFIG_SYS_PHYS_ADDR_HIGH)
 351 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64K */
 352
 353 #ifdef CONFIG_PHYS_64BIT
 354 /*
 355  * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
 356  * This will increase the amount of PCI address space available for
 357  * for mapping RAM.
 358  */
 359 #define CONFIG_SYS_PCI2_MEM_BUS         CONFIG_SYS_PCI1_MEM_BUS
 360 #else
 361 #define CONFIG_SYS_PCI2_MEM_BUS         (CONFIG_SYS_PCI1_MEM_BUS \
 362                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 363 #endif
 364 #define CONFIG_SYS_PCI2_MEM_VIRT        (CONFIG_SYS_PCI1_MEM_VIRT \
 365                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 366 #define CONFIG_SYS_PCI2_MEM_PHYS        (CONFIG_SYS_PCI1_MEM_PHYS \
 367                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 368 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 369 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 370 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
 371                                  + CONFIG_SYS_PCI1_IO_SIZE)
 372 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
 373                                  + CONFIG_SYS_PCI1_IO_SIZE)
 374 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
 375
 376 #if defined(CONFIG_PCI)
 377
 378 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 379
 380 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 381
 382 #define CONFIG_NET_MULTI
 383 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 384
 385 #define CONFIG_RTL8139
 386
 387 #undef CONFIG_EEPRO100
 388 #undef CONFIG_TULIP
 389
 390 /************************************************************
 391  * USB support
 392  ************************************************************/
 393 #define CONFIG_PCI_OHCI                 1
 394 #define CONFIG_USB_OHCI_NEW             1
 395 #define CONFIG_USB_KEYBOARD             1
 396 #define CONFIG_SYS_STDIO_DEREGISTER
 397 #define CONFIG_SYS_USB_EVENT_POLL               1
 398 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 399 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 400 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 401
 402 /*PCIE video card used*/
 403 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCI2_IO_VIRT
 404
 405 /*PCI video card used*/
 406 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 407
 408 /* video */
 409 #define CONFIG_VIDEO
 410
 411 #if defined(CONFIG_VIDEO)
 412 #define CONFIG_BIOSEMU
 413 #define CONFIG_CFB_CONSOLE
 414 #define CONFIG_VIDEO_SW_CURSOR
 415 #define CONFIG_VGA_AS_SINGLE_DEVICE
 416 #define CONFIG_ATI_RADEON_FB
 417 #define CONFIG_VIDEO_LOGO
 418 /*#define CONFIG_CONSOLE_CURSOR*/
 419 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
 420 #endif
 421
 422 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 423
 424 #define CONFIG_DOS_PARTITION
 425 #define CONFIG_SCSI_AHCI
 426
 427 #ifdef CONFIG_SCSI_AHCI
 428 #define CONFIG_SATA_ULI5288
 429 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 430 #define CONFIG_SYS_SCSI_MAX_LUN 1
 431 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 432 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 433 #endif
 434
 435 #define CONFIG_MPC86XX_PCI2
 436
 437 #endif  /* CONFIG_PCI */
 438
 439 #if defined(CONFIG_TSEC_ENET)
 440
 441 #ifndef CONFIG_NET_MULTI
 442 #define CONFIG_NET_MULTI        1
 443 #endif
 444
 445 #define CONFIG_MII              1       /* MII PHY management */
 446
 447 #define CONFIG_TSEC1            1
 448 #define CONFIG_TSEC1_NAME       "eTSEC1"
 449 #define CONFIG_TSEC2            1
 450 #define CONFIG_TSEC2_NAME       "eTSEC2"
 451 #define CONFIG_TSEC3            1
 452 #define CONFIG_TSEC3_NAME       "eTSEC3"
 453 #define CONFIG_TSEC4            1
 454 #define CONFIG_TSEC4_NAME       "eTSEC4"
 455
 456 #define TSEC1_PHY_ADDR          0
 457 #define TSEC2_PHY_ADDR          1
 458 #define TSEC3_PHY_ADDR          2
 459 #define TSEC4_PHY_ADDR          3
 460 #define TSEC1_PHYIDX            0
 461 #define TSEC2_PHYIDX            0
 462 #define TSEC3_PHYIDX            0
 463 #define TSEC4_PHYIDX            0
 464 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 465 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 466 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 467 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 468
 469 #define CONFIG_ETHPRIME         "eTSEC1"
 470
 471 #endif  /* CONFIG_TSEC_ENET */
 472
 473 /*  Contort an addr into the format needed for BATs */
 474 #ifdef CONFIG_PHYS_64BIT
 475 #define BAT_PHYS_ADDR(x)         ((unsigned long) \
 476                                   ((x & 0x00000000ffffffffULL) |        \
 477                                    ((x & 0x0000000e00000000ULL) >> 24) | \
 478                                    ((x & 0x0000000100000000ULL) >> 30)))
 479 #else
 480 #define BAT_PHYS_ADDR(x)        (x)
 481 #endif
 482
 483
 484 /* Put high physical address bits into the BAT format */
 485 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 486 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 487
 488 /*
 489  * BAT0         DDR
 490  */
 491 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 492 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 493 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 494 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 495
 496 /*
 497  * BAT1         LBC (PIXIS/CF)
 498  */
 499 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
 500                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 501                                  BATL_GUARDEDSTORAGE)
 502 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 503                                  | BATU_VS | BATU_VP)
 504 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
 505                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 506 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 507
 508 /* if CONFIG_PCI:
 509  * BAT2         PCI1 and PCI1 MEM
 510  * if CONFIG_RIO
 511  * BAT2         Rapidio Memory
 512  */
 513 #ifdef CONFIG_PCI
 514 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
 515                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 516                                  | BATL_GUARDEDSTORAGE)
 517 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
 518                                  | BATU_VS | BATU_VP)
 519 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
 520                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 521 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 522 #else /* CONFIG_RIO */
 523 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
 524                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 525                                  BATL_GUARDEDSTORAGE)
 526 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
 527                                  | BATU_VS | BATU_VP)
 528 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
 529                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 530
 531 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 532                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 533 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 534 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 535 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 536 #endif
 537
 538 /*
 539  * BAT3         CCSR Space
 540  * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
 541  * instead.  The assembler chokes on ULL.
 542  */
 543 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 544                                  | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 545                                  | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 546                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 547                                  | BATL_GUARDEDSTORAGE)
 548 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 549                                  | BATU_VP)
 550 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR_PHYS_LOW \
 551                                  | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 552                                  | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 553                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 554 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 555
 556 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 557 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 558                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 559                                        | BATL_GUARDEDSTORAGE)
 560 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 561                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 562 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 563                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 564 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 565 #endif
 566
 567 /*
 568  * BAT4         PCI1_IO and PCI2_IO
 569  */
 570 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
 571                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 572                                  | BATL_GUARDEDSTORAGE)
 573 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
 574                                  | BATU_VS | BATU_VP)
 575 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
 576                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 577 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 578
 579 /*
 580  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 581  */
 582 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 583 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 584 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 585 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 586
 587 /*
 588  * BAT6         FLASH
 589  */
 590 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 591                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 592                                  | BATL_GUARDEDSTORAGE)
 593 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 594                                  | BATU_VP)
 595 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 596                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 597 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 598
 599 /* Map the last 1M of flash where we're running from reset */
 600 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 601                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 602 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 603 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 604                                  | BATL_MEMCOHERENCE)
 605 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 606
 607 /*
 608  * BAT7         FREE - used later for tmp mappings
 609  */
 610 #define CONFIG_SYS_DBAT7L 0x00000000
 611 #define CONFIG_SYS_DBAT7U 0x00000000
 612 #define CONFIG_SYS_IBAT7L 0x00000000
 613 #define CONFIG_SYS_IBAT7U 0x00000000
 614
 615 /*
 616  * Environment
 617  */
 618 #ifndef CONFIG_SYS_RAMBOOT
 619     #define CONFIG_ENV_IS_IN_FLASH      1
 620     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE + 0x60000)
 621     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 622 #else
 623     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 624     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 625 #endif
 626 #define CONFIG_ENV_SIZE         0x2000
 627
 628 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 629 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 630
 631
 632 /*
 633  * BOOTP options
 634  */
 635 #define CONFIG_BOOTP_BOOTFILESIZE
 636 #define CONFIG_BOOTP_BOOTPATH
 637 #define CONFIG_BOOTP_GATEWAY
 638 #define CONFIG_BOOTP_HOSTNAME
 639
 640
 641 /*
 642  * Command line configuration.
 643  */
 644 #include <config_cmd_default.h>
 645
 646 #define CONFIG_CMD_PING
 647 #define CONFIG_CMD_I2C
 648 #define CONFIG_CMD_REGINFO
 649
 650 #if defined(CONFIG_SYS_RAMBOOT)
 651     #undef CONFIG_CMD_SAVEENV
 652 #endif
 653
 654 #if defined(CONFIG_PCI)
 655     #define CONFIG_CMD_PCI
 656     #define CONFIG_CMD_SCSI
 657     #define CONFIG_CMD_EXT2
 658     #define CONFIG_CMD_USB
 659 #endif
 660
 661
 662 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 663
 664 /*
 665  * Miscellaneous configurable options
 666  */
 667 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 668 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 669 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 670 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 671
 672 #if defined(CONFIG_CMD_KGDB)
 673     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 674 #else
 675     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 676 #endif
 677
 678 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 679 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 680 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 681 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 682
 683 /*
 684  * For booting Linux, the board info and command line data
 685  * have to be in the first 8 MB of memory, since this is
 686  * the maximum mapped by the Linux kernel during initialization.
 687  */
 688 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 689
 690 /*
 691  * Internal Definitions
 692  *
 693  * Boot Flags
 694  */
 695 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 696 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 697
 698 #if defined(CONFIG_CMD_KGDB)
 699     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 700     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 701 #endif
 702
 703 /*
 704  * Environment Configuration
 705  */
 706
 707 /* The mac addresses for all ethernet interface */
 708 #if defined(CONFIG_TSEC_ENET)
 709 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 710 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 711 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 712 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 713 #endif
 714
 715 #define CONFIG_HAS_ETH0         1
 716 #define CONFIG_HAS_ETH1         1
 717 #define CONFIG_HAS_ETH2         1
 718 #define CONFIG_HAS_ETH3         1
 719
 720 #define CONFIG_IPADDR           192.168.1.100
 721
 722 #define CONFIG_HOSTNAME         unknown
 723 #define CONFIG_ROOTPATH         /opt/nfsroot
 724 #define CONFIG_BOOTFILE         uImage
 725 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 726
 727 #define CONFIG_SERVERIP         192.168.1.1
 728 #define CONFIG_GATEWAYIP        192.168.1.1
 729 #define CONFIG_NETMASK          255.255.255.0
 730
 731 /* default location for tftp and bootm */
 732 #define CONFIG_LOADADDR         1000000
 733
 734 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 735 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 736
 737 #define CONFIG_BAUDRATE 115200
 738
 739 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 740         "netdev=eth0\0"                                                 \
 741         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 742         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 743                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 744                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 745                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 746                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 747                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 748         "consoledev=ttyS0\0"                                            \
 749         "ramdiskaddr=2000000\0"                                         \
 750         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 751         "fdtaddr=c00000\0"                                              \
 752         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 753         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 754         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 755         "maxcpus=2"
 756
 757
 758 #define CONFIG_NFSBOOTCOMMAND                                           \
 759         "setenv bootargs root=/dev/nfs rw "                             \
 760               "nfsroot=$serverip:$rootpath "                            \
 761               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 762               "console=$consoledev,$baudrate $othbootargs;"             \
 763         "tftp $loadaddr $bootfile;"                                     \
 764         "tftp $fdtaddr $fdtfile;"                                       \
 765         "bootm $loadaddr - $fdtaddr"
 766
 767 #define CONFIG_RAMBOOTCOMMAND                                           \
 768         "setenv bootargs root=/dev/ram rw "                             \
 769               "console=$consoledev,$baudrate $othbootargs;"             \
 770         "tftp $ramdiskaddr $ramdiskfile;"                               \
 771         "tftp $loadaddr $bootfile;"                                     \
 772         "tftp $fdtaddr $fdtfile;"                                       \
 773         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 774
 775 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 776
 777 #endif  /* __CONFIG_H */