include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  40 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  41
  42 #ifdef RUN_DIAG
  43 #define CONFIG_SYS_DIAG_ADDR         0xff800000
  44 #endif
  45
  46 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
  47
  48 /*
  49  * virtual address to be used for temporary mappings.  There
  50  * should be 128k free at this VA.
  51  */
  52 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  53
  54 /*
  55  * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
  56  */
  57 /*#define CONFIG_RIO            1*/
  58
  59 #ifndef CONFIG_RIO                      /* RIO/PCI are mutually exclusive */
  60 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  61 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  62 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  63 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  64 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  65 #endif
  66 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  67
  68 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  72
  73 #define CONFIG_ALTIVEC          1
  74
  75 /*
  76  * L2CR setup -- make sure this is right for your board!
  77  */
  78 #define CONFIG_SYS_L2
  79 #define L2_INIT         0
  80 #define L2_ENABLE       (L2CR_L2E)
  81
  82 #ifndef CONFIG_SYS_CLK_FREQ
  83 #ifndef __ASSEMBLY__
  84 extern unsigned long get_board_sys_clk(unsigned long dummy);
  85 #endif
  86 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  87 #endif
  88
  89 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  90
  91 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  92 #define CONFIG_SYS_MEMTEST_END          0x00400000
  93
  94 /*
  95  * Base addresses -- Note these are effective addresses where the
  96  * actual resources get mapped (not physical addresses)
  97  */
  98 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  99 #define CONFIG_SYS_CCSRBAR              0xf8000000      /* relocated CCSRBAR */
 100 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 101
 102 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
 103 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR+0x9000)
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CONFIG_FSL_DDR2
 109 #undef CONFIG_FSL_DDR_INTERACTIVE
 110 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 111 #define CONFIG_DDR_SPD
 112
 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 114 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 115
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 118 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 119 #define CONFIG_VERY_BIG_RAM
 120
 121 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 122
 123 #define CONFIG_NUM_DDR_CONTROLLERS      2
 124 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 125 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 126
 127 /*
 128  * I2C addresses of SPD EEPROMs
 129  */
 130 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 131 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 132 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 133 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 134
 135
 136 /*
 137  * These are used when DDR doesn't use SPD.
 138  */
 139 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 141 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 142 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 143 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 144 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 145 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 146 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 147 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 148 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 149 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 150 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 151 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 152 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 153 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 154 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 155
 156 #define CONFIG_ID_EEPROM
 157 #define CONFIG_SYS_I2C_EEPROM_NXID
 158 #define CONFIG_ID_EEPROM
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 161
 162 /*
 163  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
 164  * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
 165  * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
 166  * However, when u-boot comes up, the flash_init needs hard start addresses
 167  * to build its info table.  For user convenience, the flash addresses is
 168  * fe800000 and ff800000.  That way, u-boot knows where the flash is
 169  * and the user can download u-boot code from promjet to fef00000, a
 170  * more intuitive location than fe700000.
 171  *
 172  * Note that, on switching the boot location, fef00000 becomes fff00000.
 173  */
 174 #define CONFIG_SYS_FLASH_BASE           0xfe800000     /* start of FLASH 32M */
 175 #define CONFIG_SYS_FLASH_BASE2          0xff800000
 176
 177 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 178
 179 /* Convert an address into the right format for the BR registers */
 180 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
 181
 182 #define CONFIG_SYS_BR0_PRELIM           0xff001001      /* port size 16bit */
 183 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Boot Flash area*/
 184
 185 #define CONFIG_SYS_BR1_PRELIM           0xfe001001      /* port size 16bit */
 186 #define CONFIG_SYS_OR1_PRELIM           0xff006ff7      /* 16MB Alternate Boot Flash area*/
 187
 188 #define CONFIG_SYS_BR2_PRELIM           (BR_PHYS_ADDR(CF_BASE)          \
 189                                          | 0x00001001)  /* port size 16bit */
 190 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 191
 192 #define CONFIG_SYS_BR3_PRELIM           (BR_PHYS_ADDR(PIXIS_BASE)       \
 193                                          | 0x00000801) /* port size 8bit */
 194 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 195
 196
 197 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 198 #define PIXIS_BASE      (CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */
 199 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 200 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 201 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 202 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 203 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 204 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 205 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 206 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 207 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 208 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 209 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 210 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 211 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 212 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 213 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 214
 215 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 216 #define CF_BASE                 (PIXIS_BASE + 0x00100000)
 217
 218 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 219 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 220
 221 #undef  CONFIG_SYS_FLASH_CHECKSUM
 222 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 223 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 224 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 225
 226 #define CONFIG_FLASH_CFI_DRIVER
 227 #define CONFIG_SYS_FLASH_CFI
 228 #define CONFIG_SYS_FLASH_EMPTY_INFO
 229
 230 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 231 #define CONFIG_SYS_RAMBOOT
 232 #else
 233 #undef  CONFIG_SYS_RAMBOOT
 234 #endif
 235
 236 #if defined(CONFIG_SYS_RAMBOOT)
 237 #undef CONFIG_SPD_EEPROM
 238 #define CONFIG_SYS_SDRAM_SIZE   256
 239 #endif
 240
 241 #undef CONFIG_CLOCKS_IN_MHZ
 242
 243 #define CONFIG_L1_INIT_RAM
 244 #define CONFIG_SYS_INIT_RAM_LOCK        1
 245 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 246 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 247 #else
 248 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 249 #endif
 250 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 251
 252 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 253 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 254 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 255
 256 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 257 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 258
 259 /* Serial Port */
 260 #define CONFIG_CONS_INDEX     1
 261 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 262 #define CONFIG_SYS_NS16550
 263 #define CONFIG_SYS_NS16550_SERIAL
 264 #define CONFIG_SYS_NS16550_REG_SIZE     1
 265 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 266
 267 #define CONFIG_SYS_BAUDRATE_TABLE  \
 268         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 269
 270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 272
 273 /* Use the HUSH parser */
 274 #define CONFIG_SYS_HUSH_PARSER
 275 #ifdef  CONFIG_SYS_HUSH_PARSER
 276 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 277 #endif
 278
 279 /*
 280  * Pass open firmware flat tree to kernel
 281  */
 282 #define CONFIG_OF_LIBFDT                1
 283 #define CONFIG_OF_BOARD_SETUP           1
 284 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 285
 286
 287 #define CONFIG_SYS_64BIT_VSPRINTF       1
 288 #define CONFIG_SYS_64BIT_STRTOUL        1
 289
 290 /*
 291  * I2C
 292  */
 293 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 294 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 295 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 296 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 297 #define CONFIG_SYS_I2C_SLAVE            0x7F
 298 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 299 #define CONFIG_SYS_I2C_OFFSET           0x3100
 300
 301 /*
 302  * RapidIO MMU
 303  */
 304 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address */
 305 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 306 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 307
 308 /*
 309  * General PCI
 310  * Addresses are mapped 1-1.
 311  */
 312 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 313 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 314 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 315 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 316 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 317 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 318
 319 /* For RTL8139 */
 320 #define KSEG1ADDR(x)            ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 321 #define _IO_BASE                0x00000000
 322
 323 #define CONFIG_SYS_PCI2_MEM_BASE        (CONFIG_SYS_PCI1_MEM_BASE \
 324                                          + CONFIG_SYS_PCI1_MEM_SIZE)
 325 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 326 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 327 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 328 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
 329                                  + CONFIG_SYS_PCI1_IO_SIZE)
 330 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 331
 332 #if defined(CONFIG_PCI)
 333
 334 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 335
 336 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 337
 338 #define CONFIG_NET_MULTI
 339 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 340
 341 #define CONFIG_RTL8139
 342
 343 #undef CONFIG_EEPRO100
 344 #undef CONFIG_TULIP
 345
 346 /************************************************************
 347  * USB support
 348  ************************************************************/
 349 #define CONFIG_PCI_OHCI                 1
 350 #define CONFIG_USB_OHCI_NEW             1
 351 #define CONFIG_USB_KEYBOARD             1
 352 #define CONFIG_SYS_DEVICE_DEREGISTER
 353 #define CONFIG_SYS_USB_EVENT_POLL               1
 354 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 355 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 356 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 357
 358 /*PCIE video card used*/
 359 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCI2_IO_PHYS
 360
 361 /*PCI video card used*/
 362 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_PHYS*/
 363
 364 /* video */
 365 #define CONFIG_VIDEO
 366
 367 #if defined(CONFIG_VIDEO)
 368 #define CONFIG_BIOSEMU
 369 #define CONFIG_CFB_CONSOLE
 370 #define CONFIG_VIDEO_SW_CURSOR
 371 #define CONFIG_VGA_AS_SINGLE_DEVICE
 372 #define CONFIG_ATI_RADEON_FB
 373 #define CONFIG_VIDEO_LOGO
 374 /*#define CONFIG_CONSOLE_CURSOR*/
 375 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
 376 #endif
 377
 378 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 379
 380 #define CONFIG_DOS_PARTITION
 381 #define CONFIG_SCSI_AHCI
 382
 383 #ifdef CONFIG_SCSI_AHCI
 384 #define CONFIG_SATA_ULI5288
 385 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 386 #define CONFIG_SYS_SCSI_MAX_LUN 1
 387 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 388 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 389 #endif
 390
 391 #define CONFIG_MPC86XX_PCI2
 392
 393 #endif  /* CONFIG_PCI */
 394
 395 #if defined(CONFIG_TSEC_ENET)
 396
 397 #ifndef CONFIG_NET_MULTI
 398 #define CONFIG_NET_MULTI        1
 399 #endif
 400
 401 #define CONFIG_MII              1       /* MII PHY management */
 402
 403 #define CONFIG_TSEC1            1
 404 #define CONFIG_TSEC1_NAME       "eTSEC1"
 405 #define CONFIG_TSEC2            1
 406 #define CONFIG_TSEC2_NAME       "eTSEC2"
 407 #define CONFIG_TSEC3            1
 408 #define CONFIG_TSEC3_NAME       "eTSEC3"
 409 #define CONFIG_TSEC4            1
 410 #define CONFIG_TSEC4_NAME       "eTSEC4"
 411
 412 #define TSEC1_PHY_ADDR          0
 413 #define TSEC2_PHY_ADDR          1
 414 #define TSEC3_PHY_ADDR          2
 415 #define TSEC4_PHY_ADDR          3
 416 #define TSEC1_PHYIDX            0
 417 #define TSEC2_PHYIDX            0
 418 #define TSEC3_PHYIDX            0
 419 #define TSEC4_PHYIDX            0
 420 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 421 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 422 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 423 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 424
 425 #define CONFIG_ETHPRIME         "eTSEC1"
 426
 427 #endif  /* CONFIG_TSEC_ENET */
 428
 429 /*
 430  * BAT0         2G     Cacheable, non-guarded
 431  * 0x0000_0000  2G     DDR
 432  */
 433 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 434 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 435 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 436 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 437
 438 /*
 439  * BAT1         unused
 440  */
 441 #define CONFIG_SYS_DBAT1L       0
 442 #define CONFIG_SYS_DBAT1U       0
 443 #define CONFIG_SYS_IBAT1L       0
 444 #define CONFIG_SYS_IBAT1U       0
 445
 446 /* if CONFIG_PCI:
 447  * BAT2         1G     Cache-inhibited, guarded
 448  * 0x8000_0000  512M   PCI-Express 1 Memory
 449  * 0xa000_0000  512M   PCI-Express 2 Memory
 450  *      Changed it for operating from 0xd0000000
 451  *
 452  * if CONFIG_RIO
 453  * BAT2         512M   Cache-inhibited, guarded
 454  * 0xc000_0000  512M   RapidIO Memory
 455  */
 456 #ifdef CONFIG_PCI
 457 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
 458                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 459 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
 460                                  | BATU_VS | BATU_VP)
 461 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
 462                                  | BATL_CACHEINHIBIT)
 463 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 464 #else /* CONFIG_RIO */
 465 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 466                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 467 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 468 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 469 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 470 #endif
 471
 472 /*
 473  * BAT3         4M     Cache-inhibited, guarded
 474  * 0xf800_0000  4M     CCSR
 475  */
 476 #define CONFIG_SYS_DBAT3L       ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 477                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 478 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 479 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 480 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 481
 482 /*
 483  * BAT4         32M    Cache-inhibited, guarded
 484  * 0xe200_0000  16M    PCI-Express 1 I/O
 485  * 0xe300_0000  16M    PCI-Express 2 I/0
 486  *    Note that this is at 0xe0000000
 487  */
 488 #define CONFIG_SYS_DBAT4L       ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
 489                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 490 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 491 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 492 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 493
 494 /*
 495  * BAT5         128K   Cacheable, non-guarded
 496  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 497  */
 498 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 499 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 500 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 501 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 502
 503 /*
 504  * BAT6         32M    Cache-inhibited, guarded
 505  * 0xfe00_0000  32M    FLASH
 506  */
 507 #define CONFIG_SYS_DBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 508                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 509 #define CONFIG_SYS_DBAT6U       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 510 #define CONFIG_SYS_IBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 511 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 512
 513 #define CONFIG_SYS_DBAT7L 0x00000000
 514 #define CONFIG_SYS_DBAT7U 0x00000000
 515 #define CONFIG_SYS_IBAT7L 0x00000000
 516 #define CONFIG_SYS_IBAT7U 0x00000000
 517
 518 /*
 519  * Environment
 520  */
 521 #ifndef CONFIG_SYS_RAMBOOT
 522     #define CONFIG_ENV_IS_IN_FLASH      1
 523     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE + 0x60000)
 524     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 525     #define CONFIG_ENV_SIZE             0x2000
 526 #else
 527     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 528     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 529     #define CONFIG_ENV_SIZE             0x2000
 530 #endif
 531
 532 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 533 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 534
 535
 536 /*
 537  * BOOTP options
 538  */
 539 #define CONFIG_BOOTP_BOOTFILESIZE
 540 #define CONFIG_BOOTP_BOOTPATH
 541 #define CONFIG_BOOTP_GATEWAY
 542 #define CONFIG_BOOTP_HOSTNAME
 543
 544
 545 /*
 546  * Command line configuration.
 547  */
 548 #include <config_cmd_default.h>
 549
 550 #define CONFIG_CMD_PING
 551 #define CONFIG_CMD_I2C
 552 #define CONFIG_CMD_REGINFO
 553
 554 #if defined(CONFIG_SYS_RAMBOOT)
 555     #undef CONFIG_CMD_ENV
 556 #endif
 557
 558 #if defined(CONFIG_PCI)
 559     #define CONFIG_CMD_PCI
 560     #define CONFIG_CMD_SCSI
 561     #define CONFIG_CMD_EXT2
 562     #define CONFIG_CMD_USB
 563 #endif
 564
 565
 566 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 567
 568 /*
 569  * Miscellaneous configurable options
 570  */
 571 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 572 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 573 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 574 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 575
 576 #if defined(CONFIG_CMD_KGDB)
 577     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 578 #else
 579     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 580 #endif
 581
 582 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 583 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 584 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 585 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 586
 587 /*
 588  * For booting Linux, the board info and command line data
 589  * have to be in the first 8 MB of memory, since this is
 590  * the maximum mapped by the Linux kernel during initialization.
 591  */
 592 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 593
 594 /*
 595  * Internal Definitions
 596  *
 597  * Boot Flags
 598  */
 599 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 600 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 601
 602 #if defined(CONFIG_CMD_KGDB)
 603     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 604     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 605 #endif
 606
 607 /*
 608  * Environment Configuration
 609  */
 610
 611 /* The mac addresses for all ethernet interface */
 612 #if defined(CONFIG_TSEC_ENET)
 613 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 614 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 615 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 616 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 617 #endif
 618
 619 #define CONFIG_HAS_ETH0         1
 620 #define CONFIG_HAS_ETH1         1
 621 #define CONFIG_HAS_ETH2         1
 622 #define CONFIG_HAS_ETH3         1
 623
 624 #define CONFIG_IPADDR           192.168.1.100
 625
 626 #define CONFIG_HOSTNAME         unknown
 627 #define CONFIG_ROOTPATH         /opt/nfsroot
 628 #define CONFIG_BOOTFILE         uImage
 629 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 630
 631 #define CONFIG_SERVERIP         192.168.1.1
 632 #define CONFIG_GATEWAYIP        192.168.1.1
 633 #define CONFIG_NETMASK          255.255.255.0
 634
 635 /* default location for tftp and bootm */
 636 #define CONFIG_LOADADDR         1000000
 637
 638 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 639 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 640
 641 #define CONFIG_BAUDRATE 115200
 642
 643 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 644         "netdev=eth0\0"                                                 \
 645         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 646         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 647                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 648                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 649                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 650                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 651                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 652         "consoledev=ttyS0\0"                                            \
 653         "ramdiskaddr=2000000\0"                                         \
 654         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 655         "fdtaddr=c00000\0"                                              \
 656         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 657         "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 658         "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 659         "maxcpus=2"
 660
 661
 662 #define CONFIG_NFSBOOTCOMMAND                                           \
 663         "setenv bootargs root=/dev/nfs rw "                             \
 664               "nfsroot=$serverip:$rootpath "                            \
 665               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 666               "console=$consoledev,$baudrate $othbootargs;"             \
 667         "tftp $loadaddr $bootfile;"                                     \
 668         "tftp $fdtaddr $fdtfile;"                                       \
 669         "bootm $loadaddr - $fdtaddr"
 670
 671 #define CONFIG_RAMBOOTCOMMAND                                           \
 672         "setenv bootargs root=/dev/ram rw "                             \
 673               "console=$consoledev,$baudrate $othbootargs;"             \
 674         "tftp $ramdiskaddr $ramdiskfile;"                               \
 675         "tftp $loadaddr $bootfile;"                                     \
 676         "tftp $fdtaddr $fdtfile;"                                       \
 677         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 678
 679 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 680
 681 #endif  /* __CONFIG_H */