include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  40 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  41
  42 #ifdef RUN_DIAG
  43 #define CONFIG_SYS_DIAG_ADDR         0xff800000
  44 #endif
  45
  46 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
  47
  48 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  49 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  50 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  51 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  52 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  53 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  54
  55 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  56 #define CONFIG_ENV_OVERWRITE
  57
  58 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  59
  60 #define CONFIG_ALTIVEC          1
  61
  62 /*
  63  * L2CR setup -- make sure this is right for your board!
  64  */
  65 #define CONFIG_SYS_L2
  66 #define L2_INIT         0
  67 #define L2_ENABLE       (L2CR_L2E)
  68
  69 #ifndef CONFIG_SYS_CLK_FREQ
  70 #ifndef __ASSEMBLY__
  71 extern unsigned long get_board_sys_clk(unsigned long dummy);
  72 #endif
  73 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  74 #endif
  75
  76 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  77
  78 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  79 #define CONFIG_SYS_MEMTEST_END          0x00400000
  80
  81 /*
  82  * Base addresses -- Note these are effective addresses where the
  83  * actual resources get mapped (not physical addresses)
  84  */
  85 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  86 #define CONFIG_SYS_CCSRBAR              0xf8000000      /* relocated CCSRBAR */
  87 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  88
  89 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
  90 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR+0x9000)
  91
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_FSL_DDR2
  96 #undef CONFIG_FSL_DDR_INTERACTIVE
  97 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  98 #define CONFIG_DDR_SPD
  99
 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 101 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 102
 103 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 104 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 105 #define CONFIG_VERY_BIG_RAM
 106
 107 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 108
 109 #define CONFIG_NUM_DDR_CONTROLLERS      2
 110 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 111 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 112
 113 /*
 114  * I2C addresses of SPD EEPROMs
 115  */
 116 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 117 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 118 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 119 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 120
 121
 122 /*
 123  * These are used when DDR doesn't use SPD.
 124  */
 125 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 126 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 127 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 128 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 129 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 130 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 131 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 132 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 133 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 134 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 135 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 136 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 137 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 138 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 139 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 140 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 141
 142 #define CONFIG_ID_EEPROM
 143 #define CONFIG_SYS_I2C_EEPROM_NXID
 144 #define CONFIG_ID_EEPROM
 145 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 147
 148 /*
 149  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
 150  * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
 151  * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
 152  * However, when u-boot comes up, the flash_init needs hard start addresses
 153  * to build its info table.  For user convenience, the flash addresses is
 154  * fe800000 and ff800000.  That way, u-boot knows where the flash is
 155  * and the user can download u-boot code from promjet to fef00000, a
 156  * more intuitive location than fe700000.
 157  *
 158  * Note that, on switching the boot location, fef00000 becomes fff00000.
 159  */
 160 #define CONFIG_SYS_FLASH_BASE           0xfe800000     /* start of FLASH 32M */
 161 #define CONFIG_SYS_FLASH_BASE2          0xff800000
 162
 163 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 164
 165 #define CONFIG_SYS_BR0_PRELIM           0xff001001      /* port size 16bit */
 166 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Boot Flash area*/
 167
 168 #define CONFIG_SYS_BR1_PRELIM           0xfe001001      /* port size 16bit */
 169 #define CONFIG_SYS_OR1_PRELIM           0xff006ff7      /* 16MB Alternate Boot Flash area*/
 170
 171 #define CONFIG_SYS_BR2_PRELIM           0xf8201001      /* port size 16bit */
 172 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 173
 174 #define CONFIG_SYS_BR3_PRELIM           0xf8100801      /* port size 8bit */
 175 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 176
 177
 178 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 179 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 180 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 181 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 182 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 183 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 184 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 185 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 186 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 187 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 188 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 189 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 190 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 191 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 192 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 193 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 194 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 195
 196 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 197 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 198
 199 #undef  CONFIG_SYS_FLASH_CHECKSUM
 200 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 201 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 202 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 203
 204 #define CONFIG_FLASH_CFI_DRIVER
 205 #define CONFIG_SYS_FLASH_CFI
 206 #define CONFIG_SYS_FLASH_EMPTY_INFO
 207
 208 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 209 #define CONFIG_SYS_RAMBOOT
 210 #else
 211 #undef  CONFIG_SYS_RAMBOOT
 212 #endif
 213
 214 #if defined(CONFIG_SYS_RAMBOOT)
 215 #undef CONFIG_SPD_EEPROM
 216 #define CONFIG_SYS_SDRAM_SIZE   256
 217 #endif
 218
 219 #undef CONFIG_CLOCKS_IN_MHZ
 220
 221 #define CONFIG_L1_INIT_RAM
 222 #define CONFIG_SYS_INIT_RAM_LOCK        1
 223 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 225 #else
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 227 #endif
 228 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 229
 230 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 232 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 233
 234 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 235 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 236
 237 /* Serial Port */
 238 #define CONFIG_CONS_INDEX     1
 239 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 240 #define CONFIG_SYS_NS16550
 241 #define CONFIG_SYS_NS16550_SERIAL
 242 #define CONFIG_SYS_NS16550_REG_SIZE     1
 243 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 244
 245 #define CONFIG_SYS_BAUDRATE_TABLE  \
 246         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 247
 248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 250
 251 /* Use the HUSH parser */
 252 #define CONFIG_SYS_HUSH_PARSER
 253 #ifdef  CONFIG_SYS_HUSH_PARSER
 254 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 255 #endif
 256
 257 /*
 258  * Pass open firmware flat tree to kernel
 259  */
 260 #define CONFIG_OF_LIBFDT                1
 261 #define CONFIG_OF_BOARD_SETUP           1
 262 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 263
 264
 265 #define CONFIG_SYS_64BIT_VSPRINTF       1
 266 #define CONFIG_SYS_64BIT_STRTOUL        1
 267
 268 /*
 269  * I2C
 270  */
 271 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 272 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 273 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 274 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 275 #define CONFIG_SYS_I2C_SLAVE            0x7F
 276 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 277 #define CONFIG_SYS_I2C_OFFSET           0x3100
 278
 279 /*
 280  * RapidIO MMU
 281  */
 282 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address */
 283 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 284 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 285
 286 /*
 287  * General PCI
 288  * Addresses are mapped 1-1.
 289  */
 290 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 291 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 292 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 293 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 294 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 295 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 296
 297 /* For RTL8139 */
 298 #define KSEG1ADDR(x)            ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 299 #define _IO_BASE                0x00000000
 300
 301 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 302 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 303 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 304 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 305 #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
 306 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 307
 308 #if defined(CONFIG_PCI)
 309
 310 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 311
 312 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 313
 314 #define CONFIG_NET_MULTI
 315 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 316
 317 #define CONFIG_RTL8139
 318
 319 #undef CONFIG_EEPRO100
 320 #undef CONFIG_TULIP
 321
 322 /************************************************************
 323  * USB support
 324  ************************************************************/
 325 #define CONFIG_PCI_OHCI                 1
 326 #define CONFIG_USB_OHCI_NEW             1
 327 #define CONFIG_USB_KEYBOARD             1
 328 #define CONFIG_SYS_DEVICE_DEREGISTER
 329 #define CONFIG_SYS_USB_EVENT_POLL               1
 330 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 331 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 332 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 333
 334 #if !defined(CONFIG_PCI_PNP)
 335     #define PCI_ENET0_IOADDR    0xe0000000
 336     #define PCI_ENET0_MEMADDR   0xe0000000
 337     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 338 #endif
 339
 340 /*PCIE video card used*/
 341 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCI2_IO_PHYS
 342
 343 /*PCI video card used*/
 344 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_PHYS*/
 345
 346 /* video */
 347 #define CONFIG_VIDEO
 348
 349 #if defined(CONFIG_VIDEO)
 350 #define CONFIG_BIOSEMU
 351 #define CONFIG_CFB_CONSOLE
 352 #define CONFIG_VIDEO_SW_CURSOR
 353 #define CONFIG_VGA_AS_SINGLE_DEVICE
 354 #define CONFIG_ATI_RADEON_FB
 355 #define CONFIG_VIDEO_LOGO
 356 /*#define CONFIG_CONSOLE_CURSOR*/
 357 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
 358 #endif
 359
 360 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 361
 362 #define CONFIG_DOS_PARTITION
 363 #define CONFIG_SCSI_AHCI
 364
 365 #ifdef CONFIG_SCSI_AHCI
 366 #define CONFIG_SATA_ULI5288
 367 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 368 #define CONFIG_SYS_SCSI_MAX_LUN 1
 369 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 370 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 371 #endif
 372
 373 #define CONFIG_MPC86XX_PCI2
 374
 375 #endif  /* CONFIG_PCI */
 376
 377 #if defined(CONFIG_TSEC_ENET)
 378
 379 #ifndef CONFIG_NET_MULTI
 380 #define CONFIG_NET_MULTI        1
 381 #endif
 382
 383 #define CONFIG_MII              1       /* MII PHY management */
 384
 385 #define CONFIG_TSEC1            1
 386 #define CONFIG_TSEC1_NAME       "eTSEC1"
 387 #define CONFIG_TSEC2            1
 388 #define CONFIG_TSEC2_NAME       "eTSEC2"
 389 #define CONFIG_TSEC3            1
 390 #define CONFIG_TSEC3_NAME       "eTSEC3"
 391 #define CONFIG_TSEC4            1
 392 #define CONFIG_TSEC4_NAME       "eTSEC4"
 393
 394 #define TSEC1_PHY_ADDR          0
 395 #define TSEC2_PHY_ADDR          1
 396 #define TSEC3_PHY_ADDR          2
 397 #define TSEC4_PHY_ADDR          3
 398 #define TSEC1_PHYIDX            0
 399 #define TSEC2_PHYIDX            0
 400 #define TSEC3_PHYIDX            0
 401 #define TSEC4_PHYIDX            0
 402 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 403 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 404 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 405 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 406
 407 #define CONFIG_ETHPRIME         "eTSEC1"
 408
 409 #endif  /* CONFIG_TSEC_ENET */
 410
 411 /*
 412  * BAT0         2G     Cacheable, non-guarded
 413  * 0x0000_0000  2G     DDR
 414  */
 415 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 416 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 417 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 418 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 419
 420 /*
 421  * BAT1         1G     Cache-inhibited, guarded
 422  * 0x8000_0000  512M   PCI-Express 1 Memory
 423  * 0xa000_0000  512M   PCI-Express 2 Memory
 424  *      Changed it for operating from 0xd0000000
 425  */
 426 #define CONFIG_SYS_DBAT1L       ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
 427                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 428 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
 429 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 430 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 431
 432 /*
 433  * BAT2         512M   Cache-inhibited, guarded
 434  * 0xc000_0000  512M   RapidIO Memory
 435  */
 436 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 437                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 438 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 439 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 440 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 441
 442 /*
 443  * BAT3         4M     Cache-inhibited, guarded
 444  * 0xf800_0000  4M     CCSR
 445  */
 446 #define CONFIG_SYS_DBAT3L       ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 447                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 449 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 450 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 451
 452 /*
 453  * BAT4         32M    Cache-inhibited, guarded
 454  * 0xe200_0000  16M    PCI-Express 1 I/O
 455  * 0xe300_0000  16M    PCI-Express 2 I/0
 456  *    Note that this is at 0xe0000000
 457  */
 458 #define CONFIG_SYS_DBAT4L       ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
 459                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 460 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 461 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 462 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 463
 464 /*
 465  * BAT5         128K   Cacheable, non-guarded
 466  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 467  */
 468 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 469 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 470 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 471 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 472
 473 /*
 474  * BAT6         32M    Cache-inhibited, guarded
 475  * 0xfe00_0000  32M    FLASH
 476  */
 477 #define CONFIG_SYS_DBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 478                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 479 #define CONFIG_SYS_DBAT6U       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 480 #define CONFIG_SYS_IBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 481 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 482
 483 #define CONFIG_SYS_DBAT7L 0x00000000
 484 #define CONFIG_SYS_DBAT7U 0x00000000
 485 #define CONFIG_SYS_IBAT7L 0x00000000
 486 #define CONFIG_SYS_IBAT7U 0x00000000
 487
 488 /*
 489  * Environment
 490  */
 491 #ifndef CONFIG_SYS_RAMBOOT
 492     #define CONFIG_ENV_IS_IN_FLASH      1
 493     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE + 0x60000)
 494     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 495     #define CONFIG_ENV_SIZE             0x2000
 496 #else
 497     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 498     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 499     #define CONFIG_ENV_SIZE             0x2000
 500 #endif
 501
 502 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 503 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 504
 505
 506 /*
 507  * BOOTP options
 508  */
 509 #define CONFIG_BOOTP_BOOTFILESIZE
 510 #define CONFIG_BOOTP_BOOTPATH
 511 #define CONFIG_BOOTP_GATEWAY
 512 #define CONFIG_BOOTP_HOSTNAME
 513
 514
 515 /*
 516  * Command line configuration.
 517  */
 518 #include <config_cmd_default.h>
 519
 520 #define CONFIG_CMD_PING
 521 #define CONFIG_CMD_I2C
 522 #define CONFIG_CMD_REGINFO
 523
 524 #if defined(CONFIG_SYS_RAMBOOT)
 525     #undef CONFIG_CMD_ENV
 526 #endif
 527
 528 #if defined(CONFIG_PCI)
 529     #define CONFIG_CMD_PCI
 530     #define CONFIG_CMD_SCSI
 531     #define CONFIG_CMD_EXT2
 532     #define CONFIG_CMD_USB
 533 #endif
 534
 535
 536 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 537
 538 /*
 539  * Miscellaneous configurable options
 540  */
 541 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 542 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 543 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 544 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 545
 546 #if defined(CONFIG_CMD_KGDB)
 547     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 548 #else
 549     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 550 #endif
 551
 552 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 553 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 554 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 555 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 556
 557 /*
 558  * For booting Linux, the board info and command line data
 559  * have to be in the first 8 MB of memory, since this is
 560  * the maximum mapped by the Linux kernel during initialization.
 561  */
 562 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 563
 564 /*
 565  * Internal Definitions
 566  *
 567  * Boot Flags
 568  */
 569 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 570 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 571
 572 #if defined(CONFIG_CMD_KGDB)
 573     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 574     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 575 #endif
 576
 577 /*
 578  * Environment Configuration
 579  */
 580
 581 /* The mac addresses for all ethernet interface */
 582 #if defined(CONFIG_TSEC_ENET)
 583 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 584 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 585 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 586 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 587 #endif
 588
 589 #define CONFIG_HAS_ETH0         1
 590 #define CONFIG_HAS_ETH1         1
 591 #define CONFIG_HAS_ETH2         1
 592 #define CONFIG_HAS_ETH3         1
 593
 594 #define CONFIG_IPADDR           192.168.1.100
 595
 596 #define CONFIG_HOSTNAME         unknown
 597 #define CONFIG_ROOTPATH         /opt/nfsroot
 598 #define CONFIG_BOOTFILE         uImage
 599 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 600
 601 #define CONFIG_SERVERIP         192.168.1.1
 602 #define CONFIG_GATEWAYIP        192.168.1.1
 603 #define CONFIG_NETMASK          255.255.255.0
 604
 605 /* default location for tftp and bootm */
 606 #define CONFIG_LOADADDR         1000000
 607
 608 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 609 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 610
 611 #define CONFIG_BAUDRATE 115200
 612
 613 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 614         "netdev=eth0\0"                                                 \
 615         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 616         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 617                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 618                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 619                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 620                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 621                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 622         "consoledev=ttyS0\0"                                            \
 623         "ramdiskaddr=2000000\0"                                         \
 624         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 625         "fdtaddr=c00000\0"                                              \
 626         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 627         "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 628         "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 629         "maxcpus=2"
 630
 631
 632 #define CONFIG_NFSBOOTCOMMAND                                           \
 633         "setenv bootargs root=/dev/nfs rw "                             \
 634               "nfsroot=$serverip:$rootpath "                            \
 635               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 636               "console=$consoledev,$baudrate $othbootargs;"             \
 637         "tftp $loadaddr $bootfile;"                                     \
 638         "tftp $fdtaddr $fdtfile;"                                       \
 639         "bootm $loadaddr - $fdtaddr"
 640
 641 #define CONFIG_RAMBOOTCOMMAND                                           \
 642         "setenv bootargs root=/dev/ram rw "                             \
 643               "console=$consoledev,$baudrate $othbootargs;"             \
 644         "tftp $ramdiskaddr $ramdiskfile;"                               \
 645         "tftp $loadaddr $bootfile;"                                     \
 646         "tftp $fdtaddr $fdtfile;"                                       \
 647         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 648
 649 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 650
 651 #endif  /* __CONFIG_H */