include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  40 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  41
  42 #ifdef RUN_DIAG
  43 #define CFG_DIAG_ADDR        0xff800000
  44 #endif
  45
  46 #define CFG_RESET_ADDRESS    0xfff00100
  47
  48 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  49 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  50 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  51 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  52 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  53
  54 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  58
  59 #define CONFIG_ALTIVEC          1
  60
  61 /*
  62  * L2CR setup -- make sure this is right for your board!
  63  */
  64 #define CFG_L2
  65 #define L2_INIT         0
  66 #define L2_ENABLE       (L2CR_L2E)
  67
  68 #ifndef CONFIG_SYS_CLK_FREQ
  69 #ifndef __ASSEMBLY__
  70 extern unsigned long get_board_sys_clk(unsigned long dummy);
  71 #endif
  72 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  73 #endif
  74
  75 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  76
  77 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  78 #define CFG_MEMTEST_END         0x00400000
  79
  80 /*
  81  * Base addresses -- Note these are effective addresses where the
  82  * actual resources get mapped (not physical addresses)
  83  */
  84 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  85 #define CFG_CCSRBAR             0xf8000000      /* relocated CCSRBAR */
  86 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  87
  88 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
  89 #define CFG_PCI2_ADDR           (CFG_CCSRBAR+0x9000)
  90
  91 /*
  92  * DDR Setup
  93  */
  94 #define CONFIG_FSL_DDR2
  95 #undef CONFIG_FSL_DDR_INTERACTIVE
  96 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  97 #define CONFIG_DDR_SPD
  98
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 100 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 101
 102 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 103 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 104 #define CONFIG_VERY_BIG_RAM
 105
 106 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 107
 108 #define CONFIG_NUM_DDR_CONTROLLERS      2
 109 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 110 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 111
 112 /*
 113  * I2C addresses of SPD EEPROMs
 114  */
 115 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 116 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 117 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 118 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 119
 120
 121 /*
 122  * These are used when DDR doesn't use SPD.
 123  */
 124 #define CFG_SDRAM_SIZE          256             /* DDR is 256MB */
 125 #define CFG_DDR_CS0_BNDS        0x0000000F
 126 #define CFG_DDR_CS0_CONFIG      0x80010102      /* Enable, no interleaving */
 127 #define CFG_DDR_TIMING_3        0x00000000
 128 #define CFG_DDR_TIMING_0        0x00260802
 129 #define CFG_DDR_TIMING_1        0x39357322
 130 #define CFG_DDR_TIMING_2        0x14904cc8
 131 #define CFG_DDR_MODE_1          0x00480432
 132 #define CFG_DDR_MODE_2          0x00000000
 133 #define CFG_DDR_INTERVAL        0x06090100
 134 #define CFG_DDR_DATA_INIT       0xdeadbeef
 135 #define CFG_DDR_CLK_CTRL        0x03800000
 136 #define CFG_DDR_OCD_CTRL        0x00000000
 137 #define CFG_DDR_OCD_STATUS      0x00000000
 138 #define CFG_DDR_CONTROL         0xe3008000      /* Type = DDR2 */
 139 #define CFG_DDR_CONTROL2        0x04400000
 140
 141 /*
 142  * FIXME: Not used in fixed_sdram function
 143  */
 144 #define CFG_DDR_MODE            0x00000022
 145 #define CFG_DDR_CS1_BNDS        0x00000000
 146 #define CFG_DDR_CS2_BNDS        0x00000FFF      /* Not done */
 147 #define CFG_DDR_CS3_BNDS        0x00000FFF      /* Not done */
 148 #define CFG_DDR_CS4_BNDS        0x00000FFF      /* Not done */
 149 #define CFG_DDR_CS5_BNDS        0x00000FFF      /* Not done */
 150
 151
 152 #define CONFIG_ID_EEPROM
 153 #define CFG_I2C_EEPROM_NXID
 154 #define CONFIG_ID_EEPROM
 155 #define CFG_I2C_EEPROM_ADDR     0x57
 156 #define CFG_I2C_EEPROM_ADDR_LEN 1
 157
 158 /*
 159  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
 160  * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
 161  * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
 162  * However, when u-boot comes up, the flash_init needs hard start addresses
 163  * to build its info table.  For user convenience, the flash addresses is
 164  * fe800000 and ff800000.  That way, u-boot knows where the flash is
 165  * and the user can download u-boot code from promjet to fef00000, a
 166  * more intuitive location than fe700000.
 167  *
 168  * Note that, on switching the boot location, fef00000 becomes fff00000.
 169  */
 170 #define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
 171 #define CFG_FLASH_BASE2         0xff800000
 172
 173 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
 174
 175 #define CFG_BR0_PRELIM          0xff001001      /* port size 16bit */
 176 #define CFG_OR0_PRELIM          0xff006ff7      /* 16MB Boot Flash area*/
 177
 178 #define CFG_BR1_PRELIM          0xfe001001      /* port size 16bit */
 179 #define CFG_OR1_PRELIM          0xff006ff7      /* 16MB Alternate Boot Flash area*/
 180
 181 #define CFG_BR2_PRELIM          0xf8201001      /* port size 16bit */
 182 #define CFG_OR2_PRELIM          0xfff06ff7      /* 1MB Compact Flash area*/
 183
 184 #define CFG_BR3_PRELIM          0xf8100801      /* port size 8bit */
 185 #define CFG_OR3_PRELIM          0xfff06ff7      /* 1MB PIXIS area*/
 186
 187
 188 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 189 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 190 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 191 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 192 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 193 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 194 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 195 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 196 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 197 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 198 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 199 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 200 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 201 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 202 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 203 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 204 #define CFG_PIXIS_VBOOT_MASK    0x40    /* Reset altbank mask*/
 205
 206 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 207 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 208
 209 #undef  CFG_FLASH_CHECKSUM
 210 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 211 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 212 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 213
 214 #define CONFIG_FLASH_CFI_DRIVER
 215 #define CFG_FLASH_CFI
 216 #define CFG_FLASH_EMPTY_INFO
 217
 218 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 219 #define CFG_RAMBOOT
 220 #else
 221 #undef  CFG_RAMBOOT
 222 #endif
 223
 224 #if defined(CFG_RAMBOOT)
 225 #undef CONFIG_SPD_EEPROM
 226 #define CFG_SDRAM_SIZE  256
 227 #endif
 228
 229 #undef CONFIG_CLOCKS_IN_MHZ
 230
 231 #define CONFIG_L1_INIT_RAM
 232 #define CFG_INIT_RAM_LOCK       1
 233 #ifndef CFG_INIT_RAM_LOCK
 234 #define CFG_INIT_RAM_ADDR       0x0fd00000      /* Initial RAM address */
 235 #else
 236 #define CFG_INIT_RAM_ADDR       0xf8400000      /* Initial RAM address */
 237 #endif
 238 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 239
 240 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 241 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 242 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 243
 244 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 245 #define CFG_MALLOC_LEN          (1024 * 1024)    /* Reserved for malloc */
 246
 247 /* Serial Port */
 248 #define CONFIG_CONS_INDEX     1
 249 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 250 #define CFG_NS16550
 251 #define CFG_NS16550_SERIAL
 252 #define CFG_NS16550_REG_SIZE    1
 253 #define CFG_NS16550_CLK         get_bus_freq(0)
 254
 255 #define CFG_BAUDRATE_TABLE  \
 256         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 257
 258 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 259 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 260
 261 /* Use the HUSH parser */
 262 #define CFG_HUSH_PARSER
 263 #ifdef  CFG_HUSH_PARSER
 264 #define CFG_PROMPT_HUSH_PS2 "> "
 265 #endif
 266
 267 /*
 268  * Pass open firmware flat tree to kernel
 269  */
 270 #define CONFIG_OF_LIBFDT                1
 271 #define CONFIG_OF_BOARD_SETUP           1
 272 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 273
 274
 275 #define CFG_64BIT_VSPRINTF      1
 276 #define CFG_64BIT_STRTOUL       1
 277
 278 /*
 279  * I2C
 280  */
 281 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 282 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 283 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 284 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 285 #define CFG_I2C_SLAVE           0x7F
 286 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 287 #define CFG_I2C_OFFSET          0x3100
 288
 289 /*
 290  * RapidIO MMU
 291  */
 292 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 293 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 294 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 295
 296 /*
 297  * General PCI
 298  * Addresses are mapped 1-1.
 299  */
 300 #define CFG_PCI1_MEM_BASE       0x80000000
 301 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 302 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 303 #define CFG_PCI1_IO_BASE        0x00000000
 304 #define CFG_PCI1_IO_PHYS        0xe2000000
 305 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 306
 307 /* PCI view of System Memory */
 308 #define CFG_PCI_MEMORY_BUS      0x00000000
 309 #define CFG_PCI_MEMORY_PHYS     0x00000000
 310 #define CFG_PCI_MEMORY_SIZE     0x80000000
 311
 312 /* For RTL8139 */
 313 #define KSEG1ADDR(x)            ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 314 #define _IO_BASE                0x00000000
 315
 316 #define CFG_PCI2_MEM_BASE       0xa0000000
 317 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 318 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 319 #define CFG_PCI2_IO_BASE        0x00000000
 320 #define CFG_PCI2_IO_PHYS        0xe3000000
 321 #define CFG_PCI2_IO_SIZE        0x00100000      /* 1M */
 322
 323 #if defined(CONFIG_PCI)
 324
 325 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 326
 327 #undef CFG_SCSI_SCAN_BUS_REVERSE
 328
 329 #define CONFIG_NET_MULTI
 330 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 331
 332 #define CONFIG_RTL8139
 333
 334 #undef CONFIG_EEPRO100
 335 #undef CONFIG_TULIP
 336
 337 /************************************************************
 338  * USB support
 339  ************************************************************/
 340 #define CONFIG_PCI_OHCI                 1
 341 #define CONFIG_USB_OHCI_NEW             1
 342 #define CONFIG_USB_KEYBOARD             1
 343 #define CFG_DEVICE_DEREGISTER
 344 #define CFG_USB_EVENT_POLL              1
 345 #define CFG_USB_OHCI_SLOT_NAME          "ohci_pci"
 346 #define CFG_USB_OHCI_MAX_ROOT_PORTS     15
 347 #define CFG_OHCI_SWAP_REG_ACCESS        1
 348
 349 #if !defined(CONFIG_PCI_PNP)
 350     #define PCI_ENET0_IOADDR    0xe0000000
 351     #define PCI_ENET0_MEMADDR   0xe0000000
 352     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 353 #endif
 354
 355 /*PCIE video card used*/
 356 #define VIDEO_IO_OFFSET         CFG_PCI2_IO_PHYS
 357
 358 /*PCI video card used*/
 359 /*#define VIDEO_IO_OFFSET       CFG_PCI1_IO_PHYS*/
 360
 361 /* video */
 362 #define CONFIG_VIDEO
 363
 364 #if defined(CONFIG_VIDEO)
 365 #define CONFIG_BIOSEMU
 366 #define CONFIG_CFB_CONSOLE
 367 #define CONFIG_VIDEO_SW_CURSOR
 368 #define CONFIG_VGA_AS_SINGLE_DEVICE
 369 #define CONFIG_ATI_RADEON_FB
 370 #define CONFIG_VIDEO_LOGO
 371 /*#define CONFIG_CONSOLE_CURSOR*/
 372 #define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS
 373 #endif
 374
 375 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 376
 377 #define CONFIG_DOS_PARTITION
 378 #define CONFIG_SCSI_AHCI
 379
 380 #ifdef CONFIG_SCSI_AHCI
 381 #define CONFIG_SATA_ULI5288
 382 #define CFG_SCSI_MAX_SCSI_ID    4
 383 #define CFG_SCSI_MAX_LUN        1
 384 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 385 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 386 #endif
 387
 388 #define CONFIG_MPC86XX_PCI2
 389
 390 #endif  /* CONFIG_PCI */
 391
 392 #if defined(CONFIG_TSEC_ENET)
 393
 394 #ifndef CONFIG_NET_MULTI
 395 #define CONFIG_NET_MULTI        1
 396 #endif
 397
 398 #define CONFIG_MII              1       /* MII PHY management */
 399
 400 #define CONFIG_TSEC1            1
 401 #define CONFIG_TSEC1_NAME       "eTSEC1"
 402 #define CONFIG_TSEC2            1
 403 #define CONFIG_TSEC2_NAME       "eTSEC2"
 404 #define CONFIG_TSEC3            1
 405 #define CONFIG_TSEC3_NAME       "eTSEC3"
 406 #define CONFIG_TSEC4            1
 407 #define CONFIG_TSEC4_NAME       "eTSEC4"
 408
 409 #define TSEC1_PHY_ADDR          0
 410 #define TSEC2_PHY_ADDR          1
 411 #define TSEC3_PHY_ADDR          2
 412 #define TSEC4_PHY_ADDR          3
 413 #define TSEC1_PHYIDX            0
 414 #define TSEC2_PHYIDX            0
 415 #define TSEC3_PHYIDX            0
 416 #define TSEC4_PHYIDX            0
 417 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 418 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 419 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 420 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 421
 422 #define CONFIG_ETHPRIME         "eTSEC1"
 423
 424 #endif  /* CONFIG_TSEC_ENET */
 425
 426 /*
 427  * BAT0         2G     Cacheable, non-guarded
 428  * 0x0000_0000  2G     DDR
 429  */
 430 #define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
 431 #define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
 432 #define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
 433 #define CFG_IBAT0U      CFG_DBAT0U
 434
 435 /*
 436  * BAT1         1G     Cache-inhibited, guarded
 437  * 0x8000_0000  512M   PCI-Express 1 Memory
 438  * 0xa000_0000  512M   PCI-Express 2 Memory
 439  *      Changed it for operating from 0xd0000000
 440  */
 441 #define CFG_DBAT1L      ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
 442                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 443 #define CFG_DBAT1U      (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
 444 #define CFG_IBAT1L      (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 445 #define CFG_IBAT1U      CFG_DBAT1U
 446
 447 /*
 448  * BAT2         512M   Cache-inhibited, guarded
 449  * 0xc000_0000  512M   RapidIO Memory
 450  */
 451 #define CFG_DBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW \
 452                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 453 #define CFG_DBAT2U      (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 454 #define CFG_IBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 455 #define CFG_IBAT2U      CFG_DBAT2U
 456
 457 /*
 458  * BAT3         4M     Cache-inhibited, guarded
 459  * 0xf800_0000  4M     CCSR
 460  */
 461 #define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
 462                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 463 #define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 464 #define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 465 #define CFG_IBAT3U      CFG_DBAT3U
 466
 467 /*
 468  * BAT4         32M    Cache-inhibited, guarded
 469  * 0xe200_0000  16M    PCI-Express 1 I/O
 470  * 0xe300_0000  16M    PCI-Express 2 I/0
 471  *    Note that this is at 0xe0000000
 472  */
 473 #define CFG_DBAT4L      ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
 474                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 475 #define CFG_DBAT4U      (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 476 #define CFG_IBAT4L      (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 477 #define CFG_IBAT4U      CFG_DBAT4U
 478
 479 /*
 480  * BAT5         128K   Cacheable, non-guarded
 481  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 482  */
 483 #define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 484 #define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 485 #define CFG_IBAT5L      CFG_DBAT5L
 486 #define CFG_IBAT5U      CFG_DBAT5U
 487
 488 /*
 489  * BAT6         32M    Cache-inhibited, guarded
 490  * 0xfe00_0000  32M    FLASH
 491  */
 492 #define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 493                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 494 #define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 495 #define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 496 #define CFG_IBAT6U      CFG_DBAT6U
 497
 498 #define CFG_DBAT7L 0x00000000
 499 #define CFG_DBAT7U 0x00000000
 500 #define CFG_IBAT7L 0x00000000
 501 #define CFG_IBAT7U 0x00000000
 502
 503 /*
 504  * Environment
 505  */
 506 #ifndef CFG_RAMBOOT
 507     #define CONFIG_ENV_IS_IN_FLASH      1
 508     #define CONFIG_ENV_ADDR             (CFG_MONITOR_BASE + 0x60000)
 509     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 510     #define CONFIG_ENV_SIZE             0x2000
 511 #else
 512     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 513     #define CONFIG_ENV_ADDR             (CFG_MONITOR_BASE - 0x1000)
 514     #define CONFIG_ENV_SIZE             0x2000
 515 #endif
 516
 517 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 518 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 519
 520
 521 /*
 522  * BOOTP options
 523  */
 524 #define CONFIG_BOOTP_BOOTFILESIZE
 525 #define CONFIG_BOOTP_BOOTPATH
 526 #define CONFIG_BOOTP_GATEWAY
 527 #define CONFIG_BOOTP_HOSTNAME
 528
 529
 530 /*
 531  * Command line configuration.
 532  */
 533 #include <config_cmd_default.h>
 534
 535 #define CONFIG_CMD_PING
 536 #define CONFIG_CMD_I2C
 537 #define CONFIG_CMD_REGINFO
 538
 539 #if defined(CFG_RAMBOOT)
 540     #undef CONFIG_CMD_ENV
 541 #endif
 542
 543 #if defined(CONFIG_PCI)
 544     #define CONFIG_CMD_PCI
 545     #define CONFIG_CMD_SCSI
 546     #define CONFIG_CMD_EXT2
 547     #define CONFIG_CMD_USB
 548 #endif
 549
 550
 551 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 552
 553 /*
 554  * Miscellaneous configurable options
 555  */
 556 #define CFG_LONGHELP                    /* undef to save memory */
 557 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 558 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 559 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 560
 561 #if defined(CONFIG_CMD_KGDB)
 562     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 563 #else
 564     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 565 #endif
 566
 567 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 568 #define CFG_MAXARGS     16              /* max number of command args */
 569 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 570 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 571
 572 /*
 573  * For booting Linux, the board info and command line data
 574  * have to be in the first 8 MB of memory, since this is
 575  * the maximum mapped by the Linux kernel during initialization.
 576  */
 577 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 578
 579 /*
 580  * Internal Definitions
 581  *
 582  * Boot Flags
 583  */
 584 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 585 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 586
 587 #if defined(CONFIG_CMD_KGDB)
 588     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 589     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 590 #endif
 591
 592 /*
 593  * Environment Configuration
 594  */
 595
 596 /* The mac addresses for all ethernet interface */
 597 #if defined(CONFIG_TSEC_ENET)
 598 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 599 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 600 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 601 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 602 #endif
 603
 604 #define CONFIG_HAS_ETH0         1
 605 #define CONFIG_HAS_ETH1         1
 606 #define CONFIG_HAS_ETH2         1
 607 #define CONFIG_HAS_ETH3         1
 608
 609 #define CONFIG_IPADDR           192.168.1.100
 610
 611 #define CONFIG_HOSTNAME         unknown
 612 #define CONFIG_ROOTPATH         /opt/nfsroot
 613 #define CONFIG_BOOTFILE         uImage
 614 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 615
 616 #define CONFIG_SERVERIP         192.168.1.1
 617 #define CONFIG_GATEWAYIP        192.168.1.1
 618 #define CONFIG_NETMASK          255.255.255.0
 619
 620 /* default location for tftp and bootm */
 621 #define CONFIG_LOADADDR         1000000
 622
 623 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 624 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 625
 626 #define CONFIG_BAUDRATE 115200
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 629         "netdev=eth0\0"                                                 \
 630         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 631         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 632                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 633                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 634                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 635                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 636                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 637         "consoledev=ttyS0\0"                                            \
 638         "ramdiskaddr=2000000\0"                                         \
 639         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 640         "fdtaddr=c00000\0"                                              \
 641         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 642         "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 643         "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 644         "maxcpus=2"
 645
 646
 647 #define CONFIG_NFSBOOTCOMMAND                                           \
 648         "setenv bootargs root=/dev/nfs rw "                             \
 649               "nfsroot=$serverip:$rootpath "                            \
 650               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 651               "console=$consoledev,$baudrate $othbootargs;"             \
 652         "tftp $loadaddr $bootfile;"                                     \
 653         "tftp $fdtaddr $fdtfile;"                                       \
 654         "bootm $loadaddr - $fdtaddr"
 655
 656 #define CONFIG_RAMBOOTCOMMAND                                           \
 657         "setenv bootargs root=/dev/ram rw "                             \
 658               "console=$consoledev,$baudrate $othbootargs;"             \
 659         "tftp $ramdiskaddr $ramdiskfile;"                               \
 660         "tftp $loadaddr $bootfile;"                                     \
 661         "tftp $fdtaddr $fdtfile;"                                       \
 662         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 663
 664 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 665
 666 #endif  /* __CONFIG_H */