include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MPC8641HPCN board configuration file
  27  *
  28  * Make sure you change the MAC address and other network params first,
  29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_MPC86xx          1       /* MPC86xx */
  37 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  38 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  39 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  40 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  41 #undef DEBUG
  42
  43 #ifdef RUN_DIAG
  44 #define CFG_DIAG_ADDR        0xff800000
  45 #endif
  46
  47 #define CFG_RESET_ADDRESS    0xfff00100
  48
  49 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  50 #define CONFIG_PCI1             1       /* PCIE controler 1 (ULI bridge) */
  51 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot) */
  52 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  53
  54 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  58 #undef CONFIG_DDR_DLL                   /* possible DLL fix needed */
  59 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  60 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  61 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  62 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  63 #define CONFIG_NUM_DDR_CONTROLLERS     2
  64 /* #define CONFIG_DDR_INTERLEAVE               1 */
  65 #define CACHE_LINE_INTERLEAVING         0x20000000
  66 #define PAGE_INTERLEAVING               0x21000000
  67 #define BANK_INTERLEAVING               0x22000000
  68 #define SUPER_BANK_INTERLEAVING         0x23000000
  69
  70
  71 #define CONFIG_ALTIVEC          1
  72
  73 /*
  74  * L2CR setup -- make sure this is right for your board!
  75  */
  76 #define CFG_L2
  77 #define L2_INIT         0
  78 #define L2_ENABLE       (L2CR_L2E)
  79
  80 #ifndef CONFIG_SYS_CLK_FREQ
  81 #ifndef __ASSEMBLY__
  82 extern unsigned long get_board_sys_clk(unsigned long dummy);
  83 #endif
  84 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  85 #endif
  86
  87 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  88
  89 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  90 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  91 #define CFG_MEMTEST_END         0x00400000
  92
  93 /*
  94  * Base addresses -- Note these are effective addresses where the
  95  * actual resources get mapped (not physical addresses)
  96  */
  97 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  98 #define CFG_CCSRBAR             0xf8000000      /* relocated CCSRBAR */
  99 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
 100
 101 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 102 #define CFG_PCI2_ADDR           (CFG_CCSRBAR+0x9000)
 103
 104 /*
 105  * DDR Setup
 106  */
 107 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 108 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 109 #define CONFIG_VERY_BIG_RAM
 110
 111 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 112
 113 #if defined(CONFIG_SPD_EEPROM)
 114     /*
 115      * Determine DDR configuration from I2C interface.
 116      */
 117     #define SPD_EEPROM_ADDRESS1         0x51            /* DDR DIMM */
 118     #define SPD_EEPROM_ADDRESS2         0x52            /* DDR DIMM */
 119     #define SPD_EEPROM_ADDRESS3         0x53            /* DDR DIMM */
 120     #define SPD_EEPROM_ADDRESS4         0x54            /* DDR DIMM */
 121
 122 #else
 123     /*
 124      * Manually set up DDR1 parameters
 125      */
 126
 127     #define CFG_SDRAM_SIZE      256             /* DDR is 256MB */
 128
 129     #define CFG_DDR_CS0_BNDS    0x0000000F
 130     #define CFG_DDR_CS0_CONFIG  0x80010102      /* Enable, no interleaving */
 131     #define CFG_DDR_EXT_REFRESH 0x00000000
 132     #define CFG_DDR_TIMING_0    0x00260802
 133     #define CFG_DDR_TIMING_1    0x39357322
 134     #define CFG_DDR_TIMING_2    0x14904cc8
 135     #define CFG_DDR_MODE_1      0x00480432
 136     #define CFG_DDR_MODE_2      0x00000000
 137     #define CFG_DDR_INTERVAL    0x06090100
 138     #define CFG_DDR_DATA_INIT   0xdeadbeef
 139     #define CFG_DDR_CLK_CTRL    0x03800000
 140     #define CFG_DDR_OCD_CTRL    0x00000000
 141     #define CFG_DDR_OCD_STATUS  0x00000000
 142     #define CFG_DDR_CONTROL     0xe3008000      /* Type = DDR2 */
 143     #define CFG_DDR_CONTROL2    0x04400000
 144
 145     /* Not used in fixed_sdram function */
 146
 147     #define CFG_DDR_MODE        0x00000022
 148     #define CFG_DDR_CS1_BNDS    0x00000000
 149     #define CFG_DDR_CS2_BNDS    0x00000FFF      /* Not done */
 150     #define CFG_DDR_CS3_BNDS    0x00000FFF      /* Not done */
 151     #define CFG_DDR_CS4_BNDS    0x00000FFF      /* Not done */
 152     #define CFG_DDR_CS5_BNDS    0x00000FFF      /* Not done */
 153 #endif
 154
 155 #define CFG_ID_EEPROM   1
 156 #define ID_EEPROM_ADDR 0x57
 157
 158 /*
 159  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
 160  * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
 161  * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
 162  * However, when u-boot comes up, the flash_init needs hard start addresses
 163  * to build its info table.  For user convenience, the flash addresses is
 164  * fe800000 and ff800000.  That way, u-boot knows where the flash is
 165  * and the user can download u-boot code from promjet to fef00000, a
 166  * more intuitive location than fe700000.
 167  *
 168  * Note that, on switching the boot location, fef00000 becomes fff00000.
 169  */
 170 #define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
 171 #define CFG_FLASH_BASE2         0xff800000
 172
 173 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
 174
 175 #define CFG_BR0_PRELIM          0xff001001      /* port size 16bit */
 176 #define CFG_OR0_PRELIM          0xff006ff7      /* 16MB Boot Flash area*/
 177
 178 #define CFG_BR1_PRELIM          0xfe001001      /* port size 16bit */
 179 #define CFG_OR1_PRELIM          0xff006ff7      /* 16MB Alternate Boot Flash area*/
 180
 181 #define CFG_BR2_PRELIM          0xf8201001      /* port size 16bit */
 182 #define CFG_OR2_PRELIM          0xfff06ff7      /* 1MB Compact Flash area*/
 183
 184 #define CFG_BR3_PRELIM          0xf8100801      /* port size 8bit */
 185 #define CFG_OR3_PRELIM          0xfff06ff7      /* 1MB PIXIS area*/
 186
 187
 188 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 189 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 190 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 191 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 192 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 193 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 194 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 195 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 196 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 197 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 198 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 199 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 200 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 201 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 202 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 203
 204 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 205 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 206
 207 #undef  CFG_FLASH_CHECKSUM
 208 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 209 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 210 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 211
 212 #define CFG_FLASH_CFI_DRIVER
 213 #define CFG_FLASH_CFI
 214 #define CFG_FLASH_EMPTY_INFO
 215
 216 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 217 #define CFG_RAMBOOT
 218 #else
 219 #undef  CFG_RAMBOOT
 220 #endif
 221
 222 #if defined(CFG_RAMBOOT)
 223 #undef CONFIG_SPD_EEPROM
 224 #define CFG_SDRAM_SIZE  256
 225 #endif
 226
 227 #undef CONFIG_CLOCKS_IN_MHZ
 228
 229 #define CONFIG_L1_INIT_RAM
 230 #define CFG_INIT_RAM_LOCK       1
 231 #ifndef CFG_INIT_RAM_LOCK
 232 #define CFG_INIT_RAM_ADDR       0x0fd00000      /* Initial RAM address */
 233 #else
 234 #define CFG_INIT_RAM_ADDR       0xf8400000      /* Initial RAM address */
 235 #endif
 236 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 237
 238 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 239 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 240 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 241
 242 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 243 #define CFG_MALLOC_LEN          (1024 * 1024)    /* Reserved for malloc */
 244
 245 /* Serial Port */
 246 #define CONFIG_CONS_INDEX     1
 247 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 248 #define CFG_NS16550
 249 #define CFG_NS16550_SERIAL
 250 #define CFG_NS16550_REG_SIZE    1
 251 #define CFG_NS16550_CLK         get_bus_freq(0)
 252
 253 #define CFG_BAUDRATE_TABLE  \
 254         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 255
 256 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 257 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 258
 259 /* Use the HUSH parser */
 260 #define CFG_HUSH_PARSER
 261 #ifdef  CFG_HUSH_PARSER
 262 #define CFG_PROMPT_HUSH_PS2 "> "
 263 #endif
 264
 265 /*
 266  * Pass open firmware flat tree to kernel
 267  */
 268 #define CONFIG_OF_FLAT_TREE     1
 269 #define CONFIG_OF_BOARD_SETUP   1
 270
 271 /* maximum size of the flat tree (8K) */
 272 #define OF_FLAT_TREE_MAX_SIZE   8192
 273
 274 #define OF_CPU          "PowerPC,8641@0"
 275 #define OF_SOC          "soc8641@f8000000"
 276 #define OF_TBCLK        (bd->bi_busfreq / 4)
 277 #define OF_STDOUT_PATH  "/soc8641@f8000000/serial@4500"
 278
 279 #define CFG_64BIT_VSPRINTF      1
 280 #define CFG_64BIT_STRTOUL       1
 281
 282 /*
 283  * I2C
 284  */
 285 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 286 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 287 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 288 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 289 #define CFG_I2C_SLAVE           0x7F
 290 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 291 #define CFG_I2C_OFFSET          0x3100
 292
 293 /*
 294  * RapidIO MMU
 295  */
 296 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 297 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 298 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 299
 300 /*
 301  * General PCI
 302  * Addresses are mapped 1-1.
 303  */
 304 #define CFG_PCI1_MEM_BASE       0x80000000
 305 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 306 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 307 #define CFG_PCI1_IO_BASE        0x00000000
 308 #define CFG_PCI1_IO_PHYS        0xe2000000
 309 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 310
 311 /* PCI view of System Memory */
 312 #define CFG_PCI_MEMORY_BUS      0x00000000
 313 #define CFG_PCI_MEMORY_PHYS     0x00000000
 314 #define CFG_PCI_MEMORY_SIZE     0x80000000
 315
 316 /* For RTL8139 */
 317 #define KSEG1ADDR(x)            ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 318 #define _IO_BASE                0x00000000
 319
 320 #define CFG_PCI2_MEM_BASE       0xa0000000
 321 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 322 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 323 #define CFG_PCI2_IO_BASE        0x00000000
 324 #define CFG_PCI2_IO_PHYS        0xe3000000
 325 #define CFG_PCI2_IO_SIZE        0x00100000      /* 1M */
 326
 327 #if defined(CONFIG_PCI)
 328
 329 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 330
 331 #undef CFG_SCSI_SCAN_BUS_REVERSE
 332
 333 #define CONFIG_NET_MULTI
 334 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 335
 336 #define CONFIG_RTL8139
 337
 338 #undef CONFIG_EEPRO100
 339 #undef CONFIG_TULIP
 340
 341 #if !defined(CONFIG_PCI_PNP)
 342     #define PCI_ENET0_IOADDR    0xe0000000
 343     #define PCI_ENET0_MEMADDR   0xe0000000
 344     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 345 #endif
 346
 347 /*PCIE video card used*/
 348 #define VIDEO_IO_OFFSET         CFG_PCI2_IO_PHYS
 349
 350 /*PCI video card used*/
 351 /*#define VIDEO_IO_OFFSET       CFG_PCI1_IO_PHYS*/
 352
 353 /* video */
 354 #define CONFIG_VIDEO
 355
 356 #if defined(CONFIG_VIDEO)
 357 #define CONFIG_BIOSEMU
 358 #define CONFIG_CFB_CONSOLE
 359 #define CONFIG_VIDEO_SW_CURSOR
 360 #define CONFIG_VGA_AS_SINGLE_DEVICE
 361 #define CONFIG_ATI_RADEON_FB
 362 #define CONFIG_VIDEO_LOGO
 363 /*#define CONFIG_CONSOLE_CURSOR*/
 364 #define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS
 365 #endif
 366
 367 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 368
 369 #define CONFIG_DOS_PARTITION
 370 #define CONFIG_SCSI_AHCI
 371
 372 #ifdef CONFIG_SCSI_AHCI
 373 #define CONFIG_SATA_ULI5288
 374 #define CFG_SCSI_MAX_SCSI_ID    4
 375 #define CFG_SCSI_MAX_LUN        1
 376 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 377 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 378 #endif
 379
 380 #define CONFIG_MPC86XX_PCI2
 381
 382 #endif  /* CONFIG_PCI */
 383
 384 #if defined(CONFIG_TSEC_ENET)
 385
 386 #ifndef CONFIG_NET_MULTI
 387 #define CONFIG_NET_MULTI        1
 388 #endif
 389
 390 #define CONFIG_MII              1       /* MII PHY management */
 391
 392 #define CONFIG_TSEC1    1
 393 #define CONFIG_TSEC1_NAME       "eTSEC1"
 394 #define CONFIG_TSEC2    1
 395 #define CONFIG_TSEC2_NAME       "eTSEC2"
 396 #define CONFIG_TSEC3    1
 397 #define CONFIG_TSEC3_NAME       "eTSEC3"
 398 #define CONFIG_TSEC4    1
 399 #define CONFIG_TSEC4_NAME       "eTSEC4"
 400
 401 #define TSEC1_PHY_ADDR          0
 402 #define TSEC2_PHY_ADDR          1
 403 #define TSEC3_PHY_ADDR          2
 404 #define TSEC4_PHY_ADDR          3
 405 #define TSEC1_PHYIDX            0
 406 #define TSEC2_PHYIDX            0
 407 #define TSEC3_PHYIDX            0
 408 #define TSEC4_PHYIDX            0
 409
 410 #define CONFIG_ETHPRIME         "eTSEC1"
 411
 412 #endif  /* CONFIG_TSEC_ENET */
 413
 414 /*
 415  * BAT0         2G     Cacheable, non-guarded
 416  * 0x0000_0000  2G     DDR
 417  */
 418 #define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
 419 #define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
 420 #define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
 421 #define CFG_IBAT0U      CFG_DBAT0U
 422
 423 /*
 424  * BAT1         1G     Cache-inhibited, guarded
 425  * 0x8000_0000  512M   PCI-Express 1 Memory
 426  * 0xa000_0000  512M   PCI-Express 2 Memory
 427  *      Changed it for operating from 0xd0000000
 428  */
 429 #define CFG_DBAT1L      ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
 430                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 431 #define CFG_DBAT1U      (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
 432 #define CFG_IBAT1L      (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 433 #define CFG_IBAT1U      CFG_DBAT1U
 434
 435 /*
 436  * BAT2         512M   Cache-inhibited, guarded
 437  * 0xc000_0000  512M   RapidIO Memory
 438  */
 439 #define CFG_DBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW \
 440                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 441 #define CFG_DBAT2U      (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 442 #define CFG_IBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 443 #define CFG_IBAT2U      CFG_DBAT2U
 444
 445 /*
 446  * BAT3         4M     Cache-inhibited, guarded
 447  * 0xf800_0000  4M     CCSR
 448  */
 449 #define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
 450                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 451 #define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 452 #define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 453 #define CFG_IBAT3U      CFG_DBAT3U
 454
 455 /*
 456  * BAT4         32M    Cache-inhibited, guarded
 457  * 0xe200_0000  16M    PCI-Express 1 I/O
 458  * 0xe300_0000  16M    PCI-Express 2 I/0
 459  *    Note that this is at 0xe0000000
 460  */
 461 #define CFG_DBAT4L      ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
 462                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 463 #define CFG_DBAT4U      (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 464 #define CFG_IBAT4L      (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 465 #define CFG_IBAT4U      CFG_DBAT4U
 466
 467 /*
 468  * BAT5         128K   Cacheable, non-guarded
 469  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 470  */
 471 #define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 472 #define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 473 #define CFG_IBAT5L      CFG_DBAT5L
 474 #define CFG_IBAT5U      CFG_DBAT5U
 475
 476 /*
 477  * BAT6         32M    Cache-inhibited, guarded
 478  * 0xfe00_0000  32M    FLASH
 479  */
 480 #define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 481                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 482 #define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 483 #define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 484 #define CFG_IBAT6U      CFG_DBAT6U
 485
 486 #define CFG_DBAT7L 0x00000000
 487 #define CFG_DBAT7U 0x00000000
 488 #define CFG_IBAT7L 0x00000000
 489 #define CFG_IBAT7U 0x00000000
 490
 491 /*
 492  * Environment
 493  */
 494 #ifndef CFG_RAMBOOT
 495     #define CFG_ENV_IS_IN_FLASH 1
 496     #define CFG_ENV_ADDR                (CFG_MONITOR_BASE + 0x60000)
 497     #define CFG_ENV_SECT_SIZE           0x10000 /* 64K(one sector) for env */
 498     #define CFG_ENV_SIZE                0x2000
 499 #else
 500     #define CFG_ENV_IS_NOWHERE  1       /* Store ENV in memory only */
 501     #define CFG_ENV_ADDR                (CFG_MONITOR_BASE - 0x1000)
 502     #define CFG_ENV_SIZE                0x2000
 503 #endif
 504
 505 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 506 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 507
 508
 509 /*
 510  * BOOTP options
 511  */
 512 #define CONFIG_BOOTP_BOOTFILESIZE
 513 #define CONFIG_BOOTP_BOOTPATH
 514 #define CONFIG_BOOTP_GATEWAY
 515 #define CONFIG_BOOTP_HOSTNAME
 516
 517
 518 /*
 519  * Command line configuration.
 520  */
 521 #include <config_cmd_default.h>
 522
 523 #define CONFIG_CMD_PING
 524 #define CONFIG_CMD_I2C
 525
 526 #if defined(CFG_RAMBOOT)
 527     #undef CONFIG_CMD_ENV
 528 #endif
 529
 530 #if defined(CONFIG_PCI)
 531     #define CONFIG_CMD_PCI
 532     #define CONFIG_CMD_SCSI
 533     #define CONFIG_CMD_EXT2
 534 #endif
 535
 536
 537 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 538
 539 /*
 540  * Miscellaneous configurable options
 541  */
 542 #define CFG_LONGHELP                    /* undef to save memory */
 543 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 544 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 545
 546 #if defined(CONFIG_CMD_KGDB)
 547     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 548 #else
 549     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 550 #endif
 551
 552 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 553 #define CFG_MAXARGS     16              /* max number of command args */
 554 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 555 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 556
 557 /*
 558  * For booting Linux, the board info and command line data
 559  * have to be in the first 8 MB of memory, since this is
 560  * the maximum mapped by the Linux kernel during initialization.
 561  */
 562 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 563
 564 /* Cache Configuration */
 565 #define CFG_DCACHE_SIZE         32768
 566 #define CFG_CACHELINE_SIZE      32
 567 #if defined(CONFIG_CMD_KGDB)
 568     #define CFG_CACHELINE_SHIFT 5       /*log base 2 of the above value*/
 569 #endif
 570
 571 /*
 572  * Internal Definitions
 573  *
 574  * Boot Flags
 575  */
 576 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 577 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 578
 579 #if defined(CONFIG_CMD_KGDB)
 580     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 581     #define CONFIG_KGDB_SER_INDEX       2       /* which serial port to use */
 582 #endif
 583
 584 /*
 585  * Environment Configuration
 586  */
 587
 588 /* The mac addresses for all ethernet interface */
 589 #if defined(CONFIG_TSEC_ENET)
 590 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 591 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 592 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 593 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 594 #endif
 595
 596 #define CONFIG_HAS_ETH1         1
 597 #define CONFIG_HAS_ETH2         1
 598 #define CONFIG_HAS_ETH3         1
 599
 600 #define CONFIG_IPADDR           192.168.1.100
 601
 602 #define CONFIG_HOSTNAME         unknown
 603 #define CONFIG_ROOTPATH         /opt/nfsroot
 604 #define CONFIG_BOOTFILE         uImage
 605 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 606
 607 #define CONFIG_SERVERIP         192.168.1.1
 608 #define CONFIG_GATEWAYIP        192.168.1.1
 609 #define CONFIG_NETMASK          255.255.255.0
 610
 611 /* default location for tftp and bootm */
 612 #define CONFIG_LOADADDR         1000000
 613
 614 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 615 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 616
 617 #define CONFIG_BAUDRATE 115200
 618
 619 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 620    "netdev=eth0\0"                                                      \
 621    "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                               \
 622    "tftpflash=tftpboot $loadaddr $uboot; "                      \
 623         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 624         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 625         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 626         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 627         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 628    "consoledev=ttyS0\0"                                                 \
 629    "ramdiskaddr=2000000\0"                                              \
 630    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 631    "dtbaddr=c00000\0"                                           \
 632    "dtbfile=mpc8641_hpcn.dtb\0"                                  \
 633    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 634    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 635    "maxcpus=2"
 636
 637
 638 #define CONFIG_NFSBOOTCOMMAND                                           \
 639    "setenv bootargs root=/dev/nfs rw "                                  \
 640       "nfsroot=$serverip:$rootpath "                                    \
 641       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 642       "console=$consoledev,$baudrate $othbootargs;"                     \
 643    "tftp $loadaddr $bootfile;"                                          \
 644    "tftp $dtbaddr $dtbfile;"                                          \
 645    "bootm $loadaddr - $dtbaddr"
 646
 647 #define CONFIG_RAMBOOTCOMMAND \
 648    "setenv bootargs root=/dev/ram rw "                                  \
 649       "console=$consoledev,$baudrate $othbootargs;"                     \
 650    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 651    "tftp $loadaddr $bootfile;"                                          \
 652    "tftp $dtbaddr $dtbfile;"                                          \
 653    "bootm $loadaddr $ramdiskaddr $dtbaddr"
 654
 655 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 656
 657 #endif  /* __CONFIG_H */