include/configs/MPC86xADS.h

   1 /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola MPC8xxADS board.  Copied from the FADS config.
   4   *
   5   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
   6   */
   7
   8 /*
   9  * 1999-nov-26: The FADS is using the following physical memorymap:
  10  *
  11  * ff020000 -> ff02ffff : pcmcia
  12  * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
  13  * ff000000 -> ff00ffff : IMAP       internal in the cpu
  14  * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
  15  * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
  16  */
  17
  18 /* ------------------------------------------------------------------------- */
  19
  20 /*
  21  * board/config.h - configuration options, board specific
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31 #include <mpc8xx_irq.h>
  32
  33 /* board type */
  34 #define CONFIG_MPC86xADS        1       /* new ADS */
  35 #define CONFIG_FADS             1       /* We are FADS compatible (more or less) */
  36
  37 /* new 86xADS only - pick one of these */
  38 #define CONFIG_MPC866T          1
  39 #undef CONFIG_MPC866P
  40 #undef CONFIG_MPC859T
  41 #undef CONFIG_MPC859DSL
  42 #undef CONFIG_MPC852T
  43
  44 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  45 #undef  CONFIG_8xx_CONS_SMC2
  46 #undef  CONFIG_8xx_CONS_NONE
  47 #define CONFIG_BAUDRATE         38400
  48 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  49
  50 #ifdef CONFIG_MPC86xADS
  51 # define CFG_8XX_FACT           5               /* Multiply by 5        */
  52 # define CFG_8XX_XIN            10000000        /* 10 MHz in    */
  53 #else /* ! CONFIG_MPC86xADS */
  54 # if 0 /* old FADS */
  55 #  define CFG_8XX_FACT          12              /* Multiply by 12 */
  56 #  define CFG_8XX_XIN           4000000         /* 4 MHz in     */
  57 # else /* new FADS */
  58 #  define CFG_8XX_FACT          10              /* Multiply by 10 */
  59 #  define CFG_8XX_XIN           5000000         /* 5 MHz in     */
  60 # endif
  61 #endif /* ! CONFIG_MPC86xADS */
  62
  63 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
  64
  65 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
  66 /* in general, we always know this for FADS+new ADS anyway */
  67 #define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
  68
  69 /* most vanilla kernels do not like this, set to 0 if in doubt */
  70 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  71
  72 #if 1
  73 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  74 #else
  75 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  76 #endif
  77
  78 #undef  CONFIG_BOOTARGS
  79 #define CONFIG_BOOTCOMMAND                          \
  80     "bootp; "                               \
  81     "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  82     "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  83     "bootm"
  84
  85 /* #include "local.h" */
  86
  87 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  88
  89 /* ATA / IDE and partition support */
  90 #define CONFIG_MAC_PARTITION    1
  91 #define CONFIG_DOS_PARTITION    1
  92 #define CONFIG_ISO_PARTITION    1
  93 #undef  CONFIG_ATAPI
  94 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
  95 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
  96 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
  97 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
  98
  99 /* choose SCC1 ethernet (10BASET on motherboard)
 100  * or FEC ethernet (10/100 on daughterboard)
 101  */
 102 #if 0
 103 #define CONFIG_SCC1_ENET        1       /* use SCC1 ethernet */
 104 #undef  CONFIG_FEC_ENET                 /* disable FEC ethernet  */
 105 #else   /* all 86x cores have FECs, if in doubt, use it */
 106 #undef  CONFIG_SCC1_ENET                /* disable SCC1 ethernet */
 107 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 108 #define CFG_DISCOVER_PHY
 109 #endif
 110 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 111 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 112 #endif
 113
 114 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 115 #include <cmd_confdefs.h>
 116
 117 /*
 118  * Miscellaneous configurable options
 119  */
 120 #undef  CFG_LONGHELP                    /* undef to save memory         */
 121 #define CFG_PROMPT              "=>"    /* Monitor Command Prompt       */
 122 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 123 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 124 #else
 125 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 126 #endif
 127 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 128 #define CFG_MAXARGS     16              /* max number of command args   */
 129 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 130
 131 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 132 #if (CFG_SDRAM_SIZE)
 133 #define CFG_MEMTEST_END         CFG_SDRAM_SIZE  /* 1 ... SDRAM_SIZE     */
 134 #else
 135 #define CFG_MEMTEST_END         0x0400000       /* 1 ... 4 MB in DRAM   */
 136 #endif
 137
 138 #define CFG_LOAD_ADDR           0x00100000
 139
 140 #define CFG_HZ                  1000            /* decr freq: 1 ms ticks */
 141
 142 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 143
 144 /*
 145  * Low Level Configuration Settings
 146  * (address mappings, register initial values, etc.)
 147  * You should know what you are doing if you make changes here.
 148  */
 149 /*-----------------------------------------------------------------------
 150  * Internal Memory Mapped Register
 151  */
 152 #define CFG_IMMR                0xFF000000
 153 #define CFG_IMMR_SIZE           ((uint)(64 * 1024))
 154
 155 /*-----------------------------------------------------------------------
 156  * Definitions for initial stack pointer and data area (in DPRAM)
 157  */
 158 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 159 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 160 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 161 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 162 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 163
 164 /*-----------------------------------------------------------------------
 165  * Start addresses for the final memory configuration
 166  * (Set up by the startup code)
 167  * Please note that CFG_SDRAM_BASE _must_ start at 0
 168  */
 169 #define CFG_SDRAM_BASE          0x00000000
 170 #ifdef CONFIG_FADS
 171 # ifdef CONFIG_MPC86xADS /* new ADS */
 172 #  define       CFG_SDRAM_SIZE  0x00800000      /* 8 meg */
 173 # else                   /* old/new FADS */
 174 #  define       CFG_SDRAM_SIZE  0x00400000      /* 4 meg */
 175 # endif
 176 #else   /* !CONFIG_FADS */ /* old ADS */
 177 # define        CFG_SDRAM_SIZE  0x00000000      /* NO SDRAM */
 178 #endif
 179
 180 #define CFG_FLASH_BASE          0x02800000
 181
 182 #define CFG_FLASH_SIZE          ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 183
 184 #define CFG_MONITOR_LEN         (272 << 10)     /* Reserve 272 kB for Monitor   */
 185 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 186 #define CFG_MALLOC_LEN          (384 << 10)     /* Reserve 384 kB for malloc()  */
 187
 188 /*
 189  * For booting Linux, the board info and command line data
 190  * have to be in the first 8 MB of memory, since this is
 191  * the maximum mapped by the Linux kernel during initialization.
 192  */
 193 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 194 /*-----------------------------------------------------------------------
 195  * FLASH organization
 196  */
 197 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 198 #define CFG_MAX_FLASH_SECT      16      /* max number of sectors on one chip    */
 199
 200 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 201 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 202
 203 #define CFG_ENV_IS_IN_FLASH     1
 204 #define CFG_ENV_OFFSET          0x00040000
 205 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 206
 207 #define CFG_ENV_SECT_SIZE       0x40000 /* see README - env sector total size   */
 208
 209 /*-----------------------------------------------------------------------
 210  * Cache Configuration
 211  */
 212 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 213 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 214 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * SYPCR - System Protection Control                                    11-9
 219  * SYPCR can only be written once after reset!
 220  *-----------------------------------------------------------------------
 221  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 222  */
 223 #if defined(CONFIG_WATCHDOG)
 224 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 225                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 226 #else
 227 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 228 #endif
 229
 230 /*-----------------------------------------------------------------------
 231  * SIUMCR - SIU Module Configuration                                    11-6
 232  *-----------------------------------------------------------------------
 233  * PCMCIA config., multi-function pin tri-state
 234  */
 235 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 236
 237 /*-----------------------------------------------------------------------
 238  * TBSCR - Time Base Status and Control                                 11-26
 239  *-----------------------------------------------------------------------
 240  * Clear Reference Interrupt Status, Timebase freezing enabled
 241  */
 242 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 243
 244 /*-----------------------------------------------------------------------
 245  * PISCR - Periodic Interrupt Status and Control                11-31
 246  *-----------------------------------------------------------------------
 247  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 248  */
 249 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 250
 251 /*-----------------------------------------------------------------------
 252  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 253  *-----------------------------------------------------------------------
 254  * set the PLL, the low-power modes and the reset control (15-29)
 255  */
 256 #define CFG_PLPRCR      ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |   \
 257                                 PLPRCR_SPLSS | PLPRCR_TEXPS)
 258
 259 /*-----------------------------------------------------------------------
 260  * SCCR - System Clock and reset Control Register               15-27
 261  *-----------------------------------------------------------------------
 262  * Set clock output, timebase and RTC source and divider,
 263  * power management and some other internal clocks
 264  */
 265 #define SCCR_MASK       SCCR_EBDF11
 266 #define CFG_SCCR        (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 267
 268  /*-----------------------------------------------------------------------
 269  *
 270  *-----------------------------------------------------------------------
 271  *
 272  */
 273 #define CFG_DER          0
 274
 275 /* Because of the way the 860 starts up and assigns CS0 the
 276 * entire address space, we have to set the memory controller
 277 * differently.  Normally, you write the option register
 278 * first, and then enable the chip select by writing the
 279 * base register.  For CS0, you must write the base register
 280 * first, followed by the option register.
 281 */
 282
 283 /*
 284  * Init Memory Controller:
 285  *
 286  * BR0/1 and OR0/1 (FLASH)
 287  */
 288 /* the other CS:s are determined by looking at parameters in BCSRx */
 289
 290 #define BCSR_ADDR               ((uint) 0xFF010000)
 291 #define BCSR_SIZE               ((uint)(64 * 1024))
 292
 293 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 294 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 295
 296 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 297 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 298
 299 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 300
 301 #ifdef USE_REAL_FLASH_VALUES
 302 /*
 303  * The "default" behaviour with 1Mbyte initial doesn't work for us!
 304  */
 305 #define CFG_OR0_PRELIM  0x0FFC00D34 /* Real values for the board */
 306 #define CFG_BR0_PRELIM  0x02800001  /* Real values for the board */
 307 #else
 308 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
 309 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
 310 #endif
 311
 312 /* BCSRx - Board Control and Status Registers */
 313 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 314 #define CFG_OR1_PRELIM  0xffff8110              /* 64Kbyte address space */
 315 #define CFG_BR1_PRELIM  ((BCSR_ADDR) | BR_V )
 316
 317 /*
 318  * Internal Definitions
 319  *
 320  * Boot Flags
 321  */
 322 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 323 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 324
 325 /* values according to the manual */
 326
 327 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 328 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 329
 330 #define BCSR0                   ((uint) (BCSR_ADDR + 00))
 331 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 332 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 333 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 334 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 335
 336 /* FADS bitvalues by Helmut Buchsbaum
 337  * see MPC8xxADS User's Manual for a proper description
 338  * of the following structures
 339  */
 340
 341 #define BCSR0_ERB       ((uint)0x80000000)
 342 #define BCSR0_IP        ((uint)0x40000000)
 343 #define BCSR0_BDIS      ((uint)0x10000000)
 344 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 345 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 346 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 347 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 348 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 349
 350 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 351 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 352 #define BCSR1_ETHEN              ((uint)0x20000000)
 353 #define BCSR1_IRDEN              ((uint)0x10000000)
 354 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 355 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 356 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 357 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 358 #define BCSR1_PCCEN              ((uint)0x00800000)
 359 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 360 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 361 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 362 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 363 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 364 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 365
 366 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 367 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 368 #define BCSR2_DRAM_PD_SHIFT      (23)
 369 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 370 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 371
 372 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 373 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 374 #define BCSR3_BREVNR0            ((ushort)0x0080)
 375 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 376 #define BCSR3_BREVN1             ((ushort)0x0008)
 377 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 378
 379 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 380 #define BCSR4_TFPLDL             ((uint)0x40000000)
 381 #define BCSR4_TPSQEL             ((uint)0x20000000)
 382 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 383 #define BCSR4_FETH_EN            ((uint)0x08000000)
 384 #define BCSR4_FETHCFG0           ((uint)0x04000000)
 385 #define BCSR4_FETHFDE            ((uint)0x02000000)
 386 #define BCSR4_FETHCFG1           ((uint)0x00400000)
 387 #define BCSR4_FETHRST            ((uint)0x00200000)
 388
 389 #define CONFIG_DRAM_50MHZ               1
 390 #define CONFIG_SDRAM_50MHZ              1
 391
 392 /* Interrupt level assignments.
 393 */
 394 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 395
 396 /* We don't use the 8259.
 397 */
 398 #define NR_8259_INTS    0
 399
 400 /* Machine type
 401 */
 402 #define _MACH_8xx (_MACH_fads)
 403
 404 #define CONFIG_DISK_SPINUP_TIME 1000000
 405
 406
 407 /* PCMCIA configuration */
 408
 409 #define PCMCIA_MAX_SLOTS    2
 410
 411 #ifdef CONFIG_MPC860
 412 #define PCMCIA_SLOT_A 1
 413 #endif
 414 /*#define CFG_PCMCIA_MEM_SIZE     ( 64 << 20) */
 415 #define CFG_PCMCIA_MEM_ADDR     (0x50000000)
 416 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 417 #define CFG_PCMCIA_DMA_ADDR     (0x54000000)
 418 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 419 #define CFG_PCMCIA_ATTRB_ADDR   (0x58000000)
 420 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 421 #define CFG_PCMCIA_IO_ADDR      (0x5C000000)
 422 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 423 /* we have 8 windows, we take everything up to 60000000 */
 424
 425 #define CFG_ATA_IDE0_OFFSET     0x0000
 426
 427 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 428
 429 /* Offset for data I/O                  */
 430 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 431 /* Offset for normal register accesses  */
 432 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 433 /* Offset for alternate registers       */
 434 #define CFG_ATA_ALT_OFFSET      0x0000
 435 /*#define CFG_ATA_ALT_OFFSET    0x0100 */
 436
 437
 438 #endif  /* __CONFIG_H */