include/configs/MVBLUE.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define MV_VERSION      "v0.2.0"
  13
  14 /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
  15 #define ERR_NONE                0
  16 #define ERR_ENV                 1
  17 #define ERR_BOOTM_BADMAGIC      2
  18 #define ERR_BOOTM_BADCRC        3
  19 #define ERR_BOOTM_GUNZIP        4
  20 #define ERR_BOOTP_TIMEOUT       5
  21 #define ERR_DHCP                6
  22 #define ERR_TFTP                7
  23 #define ERR_NOLAN               8
  24 #define ERR_LANDRV              9
  25
  26 #define CONFIG_BOARD_TYPES      1
  27 #define MVBLUE_BOARD_BOX        1
  28 #define MVBLUE_BOARD_LYNX       2
  29
  30 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  31 #define CONFIG_SYS_LDSCRIPT     "board/mvblue/u-boot.lds"
  32
  33 #if 0
  34 #define ERR_LED(code)   do { if (code) \
  35                 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
  36         else \
  37                 *(volatile char *)(0xff000003) = ( 1 ); \
  38 } while(0)
  39 #else
  40 #define ERR_LED(code)
  41 #endif
  42
  43 #define CONFIG_MPC824X          1
  44 #define CONFIG_MPC8245          1
  45 #define CONFIG_MVBLUE           1
  46
  47 #define CONFIG_CLOCKS_IN_MHZ    1
  48
  49 #define CONFIG_BOARD_TYPES      1
  50
  51 #define CONFIG_CONS_INDEX       1
  52 #define CONFIG_BAUDRATE         115200
  53
  54 #define CONFIG_BOOTDELAY        3
  55 #define CONFIG_BOOT_RETRY_TIME  -1
  56
  57 #define CONFIG_AUTOBOOT_KEYED
  58 #define CONFIG_AUTOBOOT_PROMPT          \
  59         "autoboot in %d seconds (stop with 's')...\n", bootdelay
  60 #define CONFIG_AUTOBOOT_STOP_STR        "s"
  61 #define CONFIG_ZERO_BOOTDELAY_CHECK
  62 #define CONFIG_RESET_TO_RETRY           60
  63
  64
  65 /*
  66  * Command line configuration.
  67  */
  68
  69 #define CONFIG_CMD_ASKENV
  70 #define CONFIG_CMD_BOOTD
  71 #define CONFIG_CMD_CACHE
  72 #define CONFIG_CMD_DHCP
  73 #define CONFIG_CMD_ECHO
  74 #define CONFIG_CMD_SAVEENV
  75 #define CONFIG_CMD_FLASH
  76 #define CONFIG_CMD_IMI
  77 #define CONFIG_CMD_NET
  78 #define CONFIG_CMD_PCI
  79 #define CONFIG_CMD_RUN
  80
  81
  82 /*
  83  * BOOTP options
  84  */
  85 #define CONFIG_BOOTP_SUBNETMASK
  86 #define CONFIG_BOOTP_GATEWAY
  87 #define CONFIG_BOOTP_HOSTNAME
  88 #define CONFIG_BOOTP_BOOTPATH
  89 #define CONFIG_BOOTP_BOOTFILESIZE
  90 #define CONFIG_BOOTP_SUBNETMASK
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93 #define CONFIG_BOOTP_NISDOMAIN
  94 #define CONFIG_BOOTP_BOOTPATH
  95 #define CONFIG_BOOTP_DNS
  96 #define CONFIG_BOOTP_DNS2
  97 #define CONFIG_BOOTP_SEND_HOSTNAME
  98 #define CONFIG_BOOTP_NTPSERVER
  99 #define CONFIG_BOOTP_TIMEOFFSET
 100
 101
 102 /*
 103  * Miscellaneous configurable options
 104  */
 105 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 106 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 107
 108 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 109 #define CONFIG_SYS_MAXARGS      16              /* Max number of command args   */
 110 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 111 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address                 */
 112
 113 #define CONFIG_BOOTCOMMAND      "run nfsboot"
 114 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock5 ro rootfstype=jffs2"
 115
 116 #define CONFIG_NFSBOOTCOMMAND   "bootp; run nfsargs addcons;bootm"
 117
 118 #define CONFIG_EXTRA_ENV_SETTINGS                       \
 119         "console_nr=0\0"                                \
 120     "dhcp_client_id=mvBOX-XP\0"                         \
 121     "dhcp_vendor-class-identifier=mvBOX\0"              \
 122     "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"    \
 123     "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"    \
 124     "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"    \
 125     "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"        \
 126         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 127                         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"   \
 128         "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
 129     "mv_version=" MV_VERSION "\0"       \
 130         "bootretry=30\0"
 131
 132 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 133
 134 /*-----------------------------------------------------------------------
 135  * PCI stuff
 136  *-----------------------------------------------------------------------
 137  */
 138
 139 #define CONFIG_PCI
 140 #define CONFIG_PCI_INDIRECT_BRIDGE
 141 #define CONFIG_PCI_PNP
 142 #define CONFIG_PCI_SCAN_SHOW
 143
 144 #define CONFIG_NET_RETRY_COUNT          5
 145
 146 #define CONFIG_TULIP
 147 #define CONFIG_TULIP_FIX_DAVICOM        1
 148 #define CONFIG_ETHADDR                  b6:b4:45:eb:fb:c0
 149
 150 #define CONFIG_HW_WATCHDOG
 151
 152 /*-----------------------------------------------------------------------
 153  * Start addresses for the final memory configuration
 154  * (Set up by the startup code)
 155  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 156  */
 157 #define CONFIG_SYS_SDRAM_BASE       0x00000000
 158
 159 #define CONFIG_SYS_FLASH_BASE      0xFFF00000
 160 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 161
 162 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 163 #define CONFIG_SYS_EUMB_ADDR        0xFC000000
 164
 165 #define CONFIG_SYS_MONITOR_LEN     0x00100000
 166 #define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
 167
 168 #define CONFIG_SYS_MEMTEST_START   0x00100000   /* memtest works on             */
 169 #define CONFIG_SYS_MEMTEST_END      0x00800000  /* 1M ... 8M in DRAM            */
 170
 171 /* Maximum amount of RAM.  */
 172 #define CONFIG_SYS_MAX_RAM_SIZE    0x10000000   /* 0 .. 256MB of (S)DRAM */
 173
 174
 175 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 176 #undef CONFIG_SYS_RAMBOOT
 177 #else
 178 #define CONFIG_SYS_RAMBOOT
 179 #endif
 180
 181 #define CONFIG_SYS_ISA_IO      0xFE000000
 182
 183 /*
 184  * serial configuration
 185  */
 186 #define CONFIG_SYS_NS16550
 187 #define CONFIG_SYS_NS16550_SERIAL
 188
 189 #define CONFIG_SYS_NS16550_REG_SIZE    1
 190
 191 #define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)
 192
 193 #define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
 194 #define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)
 195
 196 /*-----------------------------------------------------------------------
 197  * Definitions for initial stack pointer and data area
 198  */
 199 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 200 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 201 #define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 202
 203 /*
 204  * Low Level Configuration Settings
 205  * (address mappings, register initial values, etc.)
 206  * You should know what you are doing if you make changes here.
 207  * For the detail description refer to the MPC8240 user's manual.
 208  */
 209
 210 #define CONFIG_SYS_CLK_FREQ  33000000
 211
 212 /* Bit-field values for MCCR1.  */
 213 #define CONFIG_SYS_ROMNAL      7
 214 #define CONFIG_SYS_ROMFAL      11
 215
 216 /* Bit-field values for MCCR2.  */
 217 #define CONFIG_SYS_TSWAIT      0x5
 218 #define CONFIG_SYS_REFINT      430
 219
 220 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
 221 #define CONFIG_SYS_BSTOPRE     121
 222
 223 /* Bit-field values for MCCR3.  */
 224 #define CONFIG_SYS_REFREC      8
 225
 226 /* Bit-field values for MCCR4.  */
 227 #define CONFIG_SYS_PRETOACT    3
 228 #define CONFIG_SYS_ACTTOPRE    5
 229 #define CONFIG_SYS_ACTORW      3
 230 #define CONFIG_SYS_SDMODE_CAS_LAT  3
 231 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 232 #define CONFIG_SYS_EXTROM      1
 233 #define CONFIG_SYS_REGDIMM     0
 234 #define CONFIG_SYS_DBUS_SIZE2  1
 235 #define CONFIG_SYS_SDMODE_WRAP 0
 236
 237 #define CONFIG_SYS_PGMAX       0x32
 238 #define CONFIG_SYS_SDRAM_DSCD  0x20
 239
 240 /* Memory bank settings.
 241  * Only bits 20-29 are actually used from these vales to set the
 242  * start/end addresses. The upper two bits will always be 0, and the lower
 243  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 244  * address. Refer to the MPC8240 book.
 245  */
 246
 247 #define CONFIG_SYS_BANK0_START      0x00000000
 248 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 249 #define CONFIG_SYS_BANK0_ENABLE    1
 250 #define CONFIG_SYS_BANK1_START     0x3ff00000
 251 #define CONFIG_SYS_BANK1_END       0x3fffffff
 252 #define CONFIG_SYS_BANK1_ENABLE    0
 253 #define CONFIG_SYS_BANK2_START     0x3ff00000
 254 #define CONFIG_SYS_BANK2_END       0x3fffffff
 255 #define CONFIG_SYS_BANK2_ENABLE    0
 256 #define CONFIG_SYS_BANK3_START     0x3ff00000
 257 #define CONFIG_SYS_BANK3_END       0x3fffffff
 258 #define CONFIG_SYS_BANK3_ENABLE    0
 259 #define CONFIG_SYS_BANK4_START     0x3ff00000
 260 #define CONFIG_SYS_BANK4_END       0x3fffffff
 261 #define CONFIG_SYS_BANK4_ENABLE    0
 262 #define CONFIG_SYS_BANK5_START     0x3ff00000
 263 #define CONFIG_SYS_BANK5_END       0x3fffffff
 264 #define CONFIG_SYS_BANK5_ENABLE    0
 265 #define CONFIG_SYS_BANK6_START     0x3ff00000
 266 #define CONFIG_SYS_BANK6_END       0x3fffffff
 267 #define CONFIG_SYS_BANK6_ENABLE    0
 268 #define CONFIG_SYS_BANK7_START     0x3ff00000
 269 #define CONFIG_SYS_BANK7_END       0x3fffffff
 270 #define CONFIG_SYS_BANK7_ENABLE    0
 271
 272 #define CONFIG_SYS_ODCR     0xff
 273
 274 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 275 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 276
 277 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 278 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 279
 280 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 281 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 282
 283 #define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 284 #define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 285
 286 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 287 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 288 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 289 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 290 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 291 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 292 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 293 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 294
 295 /*
 296  * For booting Linux, the board info and command line data
 297  * have to be in the first 8 MB of memory, since this is
 298  * the maximum mapped by the Linux kernel during initialization.
 299  */
 300 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 301
 302 /*-----------------------------------------------------------------------
 303  * FLASH organization
 304  */
 305 #undef  CONFIG_SYS_FLASH_PROTECTION
 306 #define CONFIG_SYS_MAX_FLASH_BANKS              1       /* Max number of flash banks            */
 307 #define CONFIG_SYS_MAX_FLASH_SECT               63      /* Max number of sectors per flash      */
 308
 309 #define CONFIG_SYS_FLASH_ERASE_TOUT     12000
 310 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000
 311
 312
 313 #define CONFIG_ENV_IS_IN_FLASH
 314
 315 #define CONFIG_ENV_OFFSET               0x00010000
 316 #define CONFIG_ENV_SIZE         0x00010000
 317 #define CONFIG_ENV_SECT_SIZE    0x00010000
 318
 319 /*-----------------------------------------------------------------------
 320  * Cache Configuration
 321  */
 322 #define CONFIG_SYS_CACHELINE_SIZE       32
 323 #if defined(CONFIG_CMD_KGDB)
 324 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value        */
 325 #endif
 326 #endif  /* __CONFIG_H */