include/configs/MVS1.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  21 #define CONFIG_MVS              1       /* ...on a MVsensor module      */
  22 #define CONFIG_MVS_16BIT_FLASH          /* ...with 16-bit flash access  */
  23 #define CONFIG_8xx_GCLK_FREQ    50000000/* ... and a 50 MHz CPU         */
  24
  25 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  26
  27 #undef  CONFIG_8xx_CONS_SMC1            /* Console is *NOT* on SMC1     */
  28 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  29 #undef  CONFIG_8xx_CONS_NONE
  30 #define CONFIG_BAUDRATE         115200  /* console baudrate             */
  31 #define CONFIG_BOOTDELAY        5       /* autoboot after this many seconds     */
  32
  33 #define CONFIG_PREBOOT          "echo;" \
  34                                 "echo To mount root over NFS use \"run bootnet\";" \
  35                                 "echo To mount root from FLASH use  \"run bootflash\";" \
  36                                 "echo"
  37 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rw"
  38 #define CONFIG_BOOTCOMMAND                                                      \
  39         "bootp; "                                                               \
  40         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  41         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  42         "bootm"
  43
  44 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  45 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  46
  47 #define CONFIG_WATCHDOG                 /* watchdog disabled/enabled    */
  48
  49 #undef  CONFIG_STATUS_LED               /* Status LED disabled/enabled  */
  50
  51 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  52
  53
  54 /*
  55  * BOOTP options
  56  */
  57 #define CONFIG_BOOTP_SUBNETMASK
  58 #define CONFIG_BOOTP_GATEWAY
  59 #define CONFIG_BOOTP_HOSTNAME
  60 #define CONFIG_BOOTP_BOOTPATH
  61 #define CONFIG_BOOTP_VENDOREX
  62
  63 #undef CONFIG_MAC_PARTITION
  64 #undef CONFIG_DOS_PARTITION
  65
  66 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  67
  68
  69 /*
  70  * Command line configuration.
  71  */
  72 #define CONFIG_CMD_LOADS
  73 #define CONFIG_CMD_LOADB
  74 #define CONFIG_CMD_IMI
  75 #define CONFIG_CMD_FLASH
  76 #define CONFIG_CMD_MEMORY
  77 #define CONFIG_CMD_NET
  78 #define CONFIG_CMD_DHCP
  79 #define CONFIG_CMD_SAVEENV
  80 #define CONFIG_CMD_BOOTD
  81 #define CONFIG_CMD_RUN
  82
  83
  84 /*
  85  * Miscellaneous configurable options
  86  */
  87 #undef  CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  88
  89 #undef  CONFIG_SYS_HUSH_PARSER                  /* Hush parse for U-Boot ?? */
  90
  91 #if defined(CONFIG_CMD_KGDB)
  92 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  93 #else
  94 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  95 #endif
  96 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  97 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  98 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  99
 100 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 101 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 102
 103 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 104
 105 /*
 106  * Low Level Configuration Settings
 107  * (address mappings, register initial values, etc.)
 108  * You should know what you are doing if you make changes here.
 109  */
 110 /*-----------------------------------------------------------------------
 111  * Internal Memory Mapped Register
 112  */
 113 #define CONFIG_SYS_IMMR         0xFFF00000
 114
 115 /*-----------------------------------------------------------------------
 116  * Definitions for initial stack pointer and data area (in DPRAM)
 117  */
 118 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 119 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 120 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 121 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 122
 123 /*-----------------------------------------------------------------------
 124  * Start addresses for the final memory configuration
 125  * (Set up by the startup code)
 126  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 127  */
 128 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 129 #define CONFIG_SYS_FLASH_BASE           0x40000000
 130
 131 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 192 kB for Monitor   */
 132
 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 134 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 135
 136 /*
 137  * For booting Linux, the board info and command line data
 138  * have to be in the first 8 MB of memory, since this is
 139  * the maximum mapped by the Linux kernel during initialization.
 140  */
 141 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 142
 143 /*-----------------------------------------------------------------------
 144  * FLASH organization
 145  */
 146 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 147 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip (for AMD320DB chip)        */
 148
 149 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 150 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 151
 152 #define CONFIG_ENV_IS_IN_FLASH  1
 153
 154 /* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
 155 #define CONFIG_ENV_OFFSET               0x8000  /* Offset of Environment Sector (bottom boot sector) */
 156 #define CONFIG_ENV_SIZE         0x2000  /* Used Size of Environment Sector 8k   */
 157
 158 /*-----------------------------------------------------------------------
 159  * Cache Configuration
 160  */
 161 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 162 #if defined(CONFIG_CMD_KGDB)
 163 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 164 #endif
 165
 166 /*-----------------------------------------------------------------------
 167  * SYPCR - System Protection Control                            11-9
 168  * SYPCR can only be written once after reset!
 169  *-----------------------------------------------------------------------
 170  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 171  */
 172 #if defined(CONFIG_WATCHDOG)
 173 #define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 174              SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 175 #else
 176 #define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 177 #endif
 178
 179 /*-----------------------------------------------------------------------
 180  * SIUMCR - SIU Module Configuration                            11-6
 181  *-----------------------------------------------------------------------
 182  * PCMCIA config., multi-function pin tri-state
 183  */
 184 #define CONFIG_SYS_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 185
 186 /*-----------------------------------------------------------------------
 187  * TBSCR - Time Base Status and Control                         11-26
 188  *-----------------------------------------------------------------------
 189  * Clear Reference Interrupt Status, Timebase freezing enabled
 190  */
 191 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 192
 193 /*-----------------------------------------------------------------------
 194  * RTCSC - Real-Time Clock Status and Control Register          11-27
 195  *-----------------------------------------------------------------------
 196  */
 197 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 198
 199 /*-----------------------------------------------------------------------
 200  * PISCR - Periodic Interrupt Status and Control                11-31
 201  *-----------------------------------------------------------------------
 202  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 203  */
 204 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 205
 206 /*-----------------------------------------------------------------------
 207  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 208  *-----------------------------------------------------------------------
 209  * Reset PLL lock status sticky bit, timer expired status bit and timer
 210  * interrupt status bit
 211  *
 212  */
 213 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 214
 215 /*-----------------------------------------------------------------------
 216  * SCCR - System Clock and reset Control Register               15-27
 217  *-----------------------------------------------------------------------
 218  * Set clock output, timebase and RTC source and divider,
 219  * power management and some other internal clocks
 220  */
 221 #define SCCR_MASK       SCCR_EBDF11
 222 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 223                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 224                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 225                          SCCR_DFALCD00)
 226
 227 /*-----------------------------------------------------------------------
 228  * PCMCIA stuff
 229  *-----------------------------------------------------------------------
 230  *
 231  */
 232 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 233 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 234 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 235 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 236 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 237 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 238 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 239 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 240
 241 /*-----------------------------------------------------------------------
 242  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 243  *-----------------------------------------------------------------------
 244  */
 245
 246 #define CONFIG_IDE_PCCARD       0       /* **DON'T** Use IDE with PC Card Adapter       */
 247
 248 #undef  CONFIG_IDE_PCMCIA               /* Direct IDE    not supported  */
 249 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 250 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 251
 252 #define CONFIG_SYS_IDE_MAXBUS           0       /* max. no. of IDE buses                        */
 253 #define CONFIG_SYS_IDE_MAXDEVICE        0       /* max. no. of drives per IDE bus       */
 254
 255
 256 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 257
 258 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 259
 260 /* Offset for data I/O                  */
 261 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 262
 263 /* Offset for normal register accesses  */
 264 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 265
 266 /* Offset for alternate registers       */
 267 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 268
 269 /*-----------------------------------------------------------------------
 270  *
 271  *-----------------------------------------------------------------------
 272  *
 273  */
 274 /*#define       CONFIG_SYS_DER  0x2002000F*/
 275 #define CONFIG_SYS_DER  0
 276
 277 /*
 278  * Init Memory Controller:
 279  *
 280  * BR0/1 and OR0/1 (FLASH)
 281  */
 282
 283 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 284 #undef FLASH_BASE1_PRELIM
 285
 286 /* used to re-map FLASH both when starting from SRAM or FLASH:
 287  * restrict access enough to keep SRAM working (if any)
 288  * but not too much to meddle with FLASH accesses
 289  */
 290 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 291 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 292
 293
 294 /*
 295  * FLASH timing:
 296  */
 297 /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
 298 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 299                                  OR_SCY_2_CLK | OR_EHTR | OR_BI)
 300 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 301 /*
 302 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 303                                  OR_SCY_5_CLK | OR_EHTR)
 304 */
 305
 306 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 307 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 308 #ifdef CONFIG_MVS_16BIT_FLASH
 309 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 310 #else
 311 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 312 #endif
 313
 314 #undef CONFIG_SYS_OR1_REMAP
 315 #undef CONFIG_SYS_OR1_PRELIM
 316 #undef CONFIG_SYS_BR1_PRELIM
 317 /*
 318  * BR2/3 and OR2/3 (SDRAM)
 319  *
 320  */
 321 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 322 #undef SDRAM_BASE3_PRELIM
 323 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 324
 325 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 326 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 327
 328 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 329 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 330
 331 #undef CONFIG_SYS_OR3_PRELIM
 332 #undef CONFIG_SYS_BR3_PRELIM
 333
 334
 335 /*
 336  * Memory Periodic Timer Prescaler
 337  *
 338  * The Divider for PTA (refresh timer) configuration is based on an
 339  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 340  * the number of chip selects (NCS) and the actually needed refresh
 341  * rate is done by setting MPTPR.
 342  *
 343  * PTA is calculated from
 344  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 345  *
 346  *      gclk      CPU clock (not bus clock!)
 347  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 348  *
 349  * 4096  Rows from SDRAM example configuration
 350  * 1000  factor s -> ms
 351  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 352  *    4  Number of refresh cycles per period
 353  *   64  Refresh cycle in ms per number of rows
 354  * --------------------------------------------
 355  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 356  *
 357  * 50 MHz => 50.000.000 / Divider =  98
 358  * 66 Mhz => 66.000.000 / Divider = 129
 359  * 80 Mhz => 80.000.000 / Divider = 156
 360  */
 361 #define CONFIG_SYS_MAMR_PTA              98
 362
 363 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 364 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 365 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 366
 367 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 368 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 369 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 370
 371 /*
 372  * MAMR settings for SDRAM
 373  */
 374
 375 /* 8 column SDRAM */
 376 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 377                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 378                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 379 /* 9 column SDRAM */
 380 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 381                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 |    \
 382                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 383
 384 #endif  /* __CONFIG_H */