include/configs/MVSMR.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2010
   6  * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <version.h>
  15
  16 #define CONFIG_MPC5200  1
  17
  18 #ifndef CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  20 #endif
  21 #define CONFIG_SYS_LDSCRIPT     "board/matrix_vision/mvsmr/u-boot.lds"
  22
  23 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  24
  25 #define CONFIG_MISC_INIT_R      1
  26
  27 #define CONFIG_SYS_CACHELINE_SIZE       32
  28 #ifdef CONFIG_CMD_KGDB
  29 #define CONFIG_SYS_CACHELINE_SHIFT      5
  30 #endif
  31
  32 #define CONFIG_PSC_CONSOLE      1
  33 #define CONFIG_BAUDRATE         115200
  34 #define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200,\
  35                                                 230400}
  36
  37 #define CONFIG_PCI              1
  38 #define CONFIG_PCI_PNP          1
  39 #undef  CONFIG_PCI_SCAN_SHOW
  40 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  41
  42 #define CONFIG_PCI_MEM_BUS      0x40000000
  43 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  44 #define CONFIG_PCI_MEM_SIZE     0x10000000
  45
  46 #define CONFIG_PCI_IO_BUS       0x50000000
  47 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  48 #define CONFIG_PCI_IO_SIZE      0x01000000
  49
  50 #define CONFIG_SYS_XLB_PIPELINING       1
  51 #define CONFIG_HIGH_BATS        1
  52
  53 #define MV_CI                   mvSMR
  54 #define MV_VCI                  mvSMR
  55 #define MV_FPGA_DATA            0xff840000
  56 #define MV_FPGA_SIZE            0x1ff88
  57 #define MV_KERNEL_ADDR          0xfff00000
  58 #define MV_SCRIPT_ADDR          0xff806000
  59 #define MV_INITRD_ADDR          0xff880000
  60 #define MV_INITRD_LENGTH        0x00240000
  61 #define MV_SCRATCH_ADDR         0xffcc0000
  62 #define MV_SCRATCH_LENGTH       MV_INITRD_LENGTH
  63
  64 #define CONFIG_SHOW_BOOT_PROGRESS 1
  65
  66 #define MV_KERNEL_ADDR_RAM      0x00100000
  67 #define MV_INITRD_ADDR_RAM      0x00400000
  68
  69 /*
  70  * Supported commands
  71  */
  72 #include <config_cmd_default.h>
  73
  74 #define CONFIG_CMD_CACHE
  75 #define CONFIG_CMD_DHCP
  76 #define CONFIG_CMD_FPGA
  77 #define CONFIG_CMD_I2C
  78 #define CONFIG_CMD_MII
  79 #define CONFIG_CMD_NET
  80 #define CONFIG_CMD_PCI
  81 #define CONFIG_CMD_PING
  82 #define CONFIG_CMD_SDRAM
  83
  84 #define CONFIG_BOOTP_BOOTFILESIZE
  85 #define CONFIG_BOOTP_BOOTPATH
  86 #define CONFIG_BOOTP_DNS
  87 #define CONFIG_BOOTP_DNS2
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90 #define CONFIG_BOOTP_NTPSERVER
  91 #define CONFIG_BOOTP_RANDOM_DELAY
  92 #define CONFIG_BOOTP_SEND_HOSTNAME
  93 #define CONFIG_BOOTP_SUBNETMASK
  94 #define CONFIG_BOOTP_VENDOREX
  95
  96 /*
  97  * Autoboot
  98  */
  99 #define CONFIG_BOOTDELAY                1
 100 #define CONFIG_AUTOBOOT_KEYED
 101 #define CONFIG_AUTOBOOT_STOP_STR        "abcdefg"
 102 #define CONFIG_ZERO_BOOTDELAY_CHECK
 103
 104 #define CONFIG_BOOTCOMMAND      "source ${script_addr}"
 105 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs" \
 106                                         " allocate=6M"
 107
 108 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 109         "console_nr=0\0"                                        \
 110         "console=no\0"                                          \
 111         "stdin=serial\0"                                        \
 112         "stdout=serial\0"                                       \
 113         "stderr=serial\0"                                       \
 114         "fpga=0\0"                                              \
 115         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"                      \
 116         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"          \
 117         "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"              \
 118         "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"      \
 119         "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"         \
 120         "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"              \
 121         "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"      \
 122         "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"  \
 123         "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"            \
 124         "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"        \
 125         "mv_version=" U_BOOT_VERSION "\0"                       \
 126         "dhcp_client_id=" __stringify(MV_CI) "\0"                       \
 127         "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"        \
 128         "netretry=no\0"                                         \
 129         "use_static_ipaddr=no\0"                                \
 130         "static_ipaddr=192.168.0.101\0"                         \
 131         "static_netmask=255.255.255.0\0"                        \
 132         "static_gateway=0.0.0.0\0"                              \
 133         "initrd_name=uInitrd.mvsmr-rfs\0"                       \
 134         "zcip=yes\0"                                            \
 135         "netboot=no\0"                                          \
 136         ""
 137
 138 /*
 139  * IPB Bus clocking configuration.
 140  */
 141 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
 142
 143 /*
 144  * Flash configuration
 145  */
 146 #undef  CONFIG_FLASH_16BIT
 147 #define CONFIG_SYS_FLASH_CFI
 148 #define CONFIG_FLASH_CFI_DRIVER
 149 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
 150 #define CONFIG_SYS_FLASH_EMPTY_INFO
 151
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     50000
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 156 #define CONFIG_SYS_MAX_FLASH_SECT       256
 157
 158 #define CONFIG_SYS_LOWBOOT
 159 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE
 160 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 161
 162 /*
 163  * Environment settings
 164  */
 165 #define CONFIG_ENV_IS_IN_FLASH
 166 #undef  CONFIG_SYS_FLASH_PROTECTION
 167 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 168
 169 #define CONFIG_ENV_OFFSET       0x8000
 170 #define CONFIG_ENV_SIZE         0x2000
 171 #define CONFIG_ENV_SECT_SIZE    0x2000
 172
 173 /* used by linker script to wrap code around */
 174 #define CONFIG_SCRIPT_OFFSET    0x6000
 175 #define CONFIG_SCRIPT_SECT_SIZE 0x2000
 176
 177 /*
 178  * Memory map
 179  */
 180 #define CONFIG_SYS_MBAR         0xF0000000
 181 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 182 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 183
 184 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 185 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 186
 187 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 188                                                 GENERATED_GBL_DATA_SIZE)
 189 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 190
 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 192 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 193 #define CONFIG_SYS_RAMBOOT              1
 194 #endif
 195
 196 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 197 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
 198 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 199 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 200
 201 /*
 202  * I2C configuration
 203  */
 204 #define CONFIG_HARD_I2C         1
 205 #define CONFIG_SYS_I2C_MODULE   1
 206 #define CONFIG_SYS_I2C_SPEED    86000
 207 #define CONFIG_SYS_I2C_SLAVE    0x7F
 208
 209 /*
 210  * Ethernet configuration
 211  */
 212 #define CONFIG_NET_RETRY_COUNT 5
 213
 214 #define CONFIG_MPC5xxx_FEC
 215 #define CONFIG_MPC5xxx_FEC_MII100
 216 #define CONFIG_PHY_ADDR         0x00
 217 #define CONFIG_NETDEV           eth0
 218
 219 /*
 220  * Miscellaneous configurable options
 221  */
 222 #define CONFIG_SYS_HUSH_PARSER
 223 #define CONFIG_CMDLINE_EDITING
 224 #undef  CONFIG_SYS_LONGHELP
 225 #ifdef CONFIG_CMD_KGDB
 226 #define CONFIG_SYS_CBSIZE               1024
 227 #else
 228 #define CONFIG_SYS_CBSIZE               256
 229 #endif
 230 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 231 #define CONFIG_SYS_MAXARGS              16
 232 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 233
 234 #define CONFIG_SYS_MEMTEST_START        0x00800000
 235 #define CONFIG_SYS_MEMTEST_END          0x02f00000
 236
 237 /* default load address */
 238 #define CONFIG_SYS_LOAD_ADDR            0x02000000
 239 /* default location for tftp and bootm */
 240 #define CONFIG_LOADADDR                 0x00200000
 241
 242 /*
 243  * Various low-level settings
 244  */
 245 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00050044
 246
 247 #define CONFIG_SYS_HID0_INIT            (HID0_ICE | HID0_ICFI)
 248 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 249
 250 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 251 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 252 #define CONFIG_SYS_BOOTCS_CFG           0x00047800
 253 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 254 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 255
 256 #define CONFIG_SYS_CS_BURST             0x000000f0
 257 #define CONFIG_SYS_CS_DEADCYCLE         0x33333303
 258
 259 #define CONFIG_SYS_RESET_ADDRESS        0x00000100
 260
 261 #undef FPGA_DEBUG
 262 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
 263 #define CONFIG_FPGA
 264 #define CONFIG_FPGA_XILINX      1
 265 #define CONFIG_FPGA_SPARTAN2    1
 266 #define CONFIG_FPGA_COUNT       1
 267
 268 #endif