include/configs/NC650.h

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35 #define CONFIG_MPC852T          1
  36 #define CONFIG_NC650            1
  37
  38 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  39 #undef  CONFIG_8xx_CONS_SMC2
  40 #undef  CONFIG_8xx_CONS_NONE
  41 #define CONFIG_BAUDRATE         115200
  42 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  43
  44 /*
  45  * 10 MHz - PLL input clock
  46  */
  47 #define CONFIG_8xx_OSCLK                10000000
  48
  49 /*
  50  * 50 MHz - default CPU clock
  51  */
  52 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  53
  54 /*
  55  * 15 MHz - CPU minimum clock
  56  */
  57 #define CFG_8xx_CPUCLK_MIN              15000000
  58
  59 /*
  60  * 133 MHz - CPU maximum clock
  61  */
  62 #define CFG_8xx_CPUCLK_MAX              133000000
  63
  64 #define CFG_MEASURE_CPUCLK
  65 #define CFG_8XX_XIN                     CONFIG_8xx_OSCLK
  66
  67 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  68
  69 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  70
  71 #undef  CONFIG_BOOTARGS
  72 #define CONFIG_BOOTCOMMAND                                                      \
  73         "bootp;"                                                                \
  74         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  75         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
  76         "bootm"
  77
  78 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  79
  80 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
  81
  82 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  83
  84 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
  85 #define FEC_ENET
  86 #define CONFIG_MII
  87 #define CFG_DISCOVER_PHY        1
  88
  89
  90 /* enable I2C and select the hardware/software driver */
  91 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  92 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  93 #define CFG_I2C_SPEED           100000  /* 100 kHz                      */
  94 #define CFG_I2C_SLAVE           0x7f
  95
  96 /*
  97  * Software (bit-bang) I2C driver configuration
  98  */
  99 #define SCL             0x1000          /* PA 3 */
 100 #define SDA             0x2000          /* PA 2 */
 101
 102 #define PAR             immr->im_ioport.iop_papar
 103 #define DIR             immr->im_ioport.iop_padir
 104 #define DAT             immr->im_ioport.iop_padat
 105
 106 #define I2C_INIT        {PAR &= ~(SCL | SDA); DIR |=  SCL;}
 107 #define I2C_ACTIVE      (DIR |=  SDA)
 108 #define I2C_TRISTATE    (DIR &= ~SDA)
 109 #define I2C_READ        ((DAT & SDA) != 0)
 110 #define I2C_SDA(bit)    if (bit) DAT |=  SDA; \
 111                         else DAT &= ~SDA
 112 #define I2C_SCL(bit)    if (bit) DAT |=  SCL; \
 113                         else DAT &= ~SCL
 114 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 115
 116 #define CONFIG_RTC_PCF8563
 117 #define CFG_I2C_RTC_ADDR                0x51
 118
 119 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 120                                 CFG_CMD_ASKENV  | \
 121                                 CFG_CMD_DATE    | \
 122                                 CFG_CMD_DHCP    | \
 123                                 CFG_CMD_I2C     | \
 124                                 CFG_CMD_NAND    | \
 125                                 CFG_CMD_JFFS2   | \
 126                                 CFG_CMD_NFS     | \
 127                                 CFG_CMD_SNTP    )
 128
 129 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 130 #include <cmd_confdefs.h>
 131
 132 /*
 133  * Miscellaneous configurable options
 134  */
 135 #define CFG_LONGHELP                    /* undef to save memory         */
 136 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 137 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 138 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 139 #else
 140 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 141 #endif
 142 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 143 #define CFG_MAXARGS     16              /* max number of command args   */
 144 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 145
 146 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 147 #define CFG_MEMTEST_END         0x0400000       /* 1 ... 4 MB in DRAM   */
 148
 149 #define CFG_LOAD_ADDR           0x00100000
 150
 151 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 152
 153 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 154
 155 /*
 156  * Low Level Configuration Settings
 157  * (address mappings, register initial values, etc.)
 158  * You should know what you are doing if you make changes here.
 159  */
 160 /*-----------------------------------------------------------------------
 161  * Internal Memory Mapped Register
 162  */
 163 #define CFG_IMMR                0xF0000000
 164 #define CFG_IMMR_SIZE           ((uint)(64 * 1024))
 165
 166 /*-----------------------------------------------------------------------
 167  * Definitions for initial stack pointer and data area (in DPRAM)
 168  */
 169 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 170 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 171 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 172 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 173 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 174
 175 /*-----------------------------------------------------------------------
 176  * Start addresses for the final memory configuration
 177  * (Set up by the startup code)
 178  * Please note that CFG_SDRAM_BASE _must_ start at 0
 179  */
 180 #define CFG_SDRAM_BASE          0x00000000
 181 #define CFG_FLASH_BASE          0x40000000
 182
 183 #define CFG_RESET_ADDRESS       0xFFF00100
 184
 185 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 186 #define CFG_MONITOR_BASE        TEXT_BASE
 187 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc()  */
 188
 189 /*
 190  * For booting Linux, the board info and command line data
 191  * have to be in the first 8 MB of memory, since this is
 192  * the maximum mapped by the Linux kernel during initialization.
 193  */
 194 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 195 /*-----------------------------------------------------------------------
 196  * FLASH organization
 197  */
 198 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 199 #define CFG_MAX_FLASH_SECT      64      /* max number of sectors on one chip    */
 200
 201 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 202 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 203
 204
 205 #define CFG_ENV_IS_IN_FLASH     1
 206 #define CFG_ENV_OFFSET          0x00740000
 207
 208 #define CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment sector     */
 209 #define CFG_ENV_SIZE            0x4000  /* Used Size of Environment Sector      */
 210
 211 /*-----------------------------------------------------------------------
 212  * Cache Configuration
 213  */
 214 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 215 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 216 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 217 #endif
 218
 219 /*
 220  * NAND flash support
 221  */
 222 #define CFG_MAX_NAND_DEVICE     1
 223 #define NAND_ChipID_UNKNOWN     0x00
 224 #define SECTORSIZE              512
 225 #define NAND_MAX_FLOORS         1
 226 #define NAND_MAX_CHIPS          1
 227 #define ADDR_PAGE               2
 228 #define ADDR_COLUMN_PAGE        3
 229 #define ADDR_COLUMN             1
 230 #define NAND_NO_RB
 231
 232 #define NAND_WAIT_READY(nand)           udelay(12)
 233 #define WRITE_NAND_COMMAND(d, adr)      WRITE_NAND(d, adr + 2)
 234 #define WRITE_NAND_ADDRESS(d, adr)      WRITE_NAND(d, adr + 1)
 235 #define WRITE_NAND(d, adr)              (*(volatile uint8_t *)(adr) = (uint8_t)(d))
 236 #define READ_NAND(adr)                  (*(volatile uint8_t *)(adr))
 237 #define NAND_DISABLE_CE(nand)           /* nop */
 238 #define NAND_ENABLE_CE(nand)            /* nop */
 239 #define NAND_CTL_CLRALE(nandptr)        /* nop */
 240 #define NAND_CTL_SETALE(nandptr)        /* nop */
 241 #define NAND_CTL_CLRCLE(nandptr)        /* nop */
 242 #define NAND_CTL_SETCLE(nandptr)        /* nop */
 243
 244 /*-----------------------------------------------------------------------
 245  * SYPCR - System Protection Control                                    11-9
 246  * SYPCR can only be written once after reset!
 247  *-----------------------------------------------------------------------
 248  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 249  */
 250 #if defined(CONFIG_WATCHDOG)
 251 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 252                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 253 #else
 254 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 255 #endif
 256
 257 /*-----------------------------------------------------------------------
 258  * SIUMCR - SIU Module Configuration                                    11-6
 259  *-----------------------------------------------------------------------
 260  */
 261 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 262
 263 /*-----------------------------------------------------------------------
 264  * TBSCR - Time Base Status and Control                                 11-26
 265  *-----------------------------------------------------------------------
 266  * Clear Reference Interrupt Status, Timebase freezing enabled
 267  */
 268 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 269
 270 /*-----------------------------------------------------------------------
 271  * PISCR - Periodic Interrupt Status and Control                11-31
 272  *-----------------------------------------------------------------------
 273  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 274  */
 275 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 276
 277 /*-----------------------------------------------------------------------
 278  * SCCR - System Clock and reset Control Register               15-27
 279  *-----------------------------------------------------------------------
 280  * Set clock output, timebase and RTC source and divider,
 281  * power management and some other internal clocks
 282  */
 283 #define SCCR_MASK       SCCR_EBDF11
 284 #define CFG_SCCR        (SCCR_COM00     | SCCR_DFSYNC00 | \
 285                          SCCR_DFBRG00   | SCCR_DFNL000  | SCCR_DFNH000  | \
 286                          SCCR_DFLCD000  | SCCR_DFALCD00)
 287
 288  /*-----------------------------------------------------------------------
 289  *
 290  *-----------------------------------------------------------------------
 291  *
 292  */
 293 #define CFG_DER         0
 294
 295 /*
 296  * Init Memory Controller:
 297  *
 298  * BR0 and OR0 (FLASH)
 299  */
 300
 301 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 302
 303 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 304 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 305
 306 /* FLASH timing: Default value of OR0 after reset */
 307 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
 308                                  OR_SCY_15_CLK | OR_TRLX)
 309
 310 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 311 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 312 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 313
 314 /*
 315  * BR2 and OR2 (NAND Flash) - now addressed through UPMB
 316  */
 317 #define CFG_NAND_BASE           0x50000000
 318 #define CFG_NAND_SIZE           0x04000000
 319
 320 #define CFG_OR_TIMING_NAND      (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 321                                  OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
 322
 323 #define CFG_BR2_PRELIM  ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
 324 #define CFG_OR2_PRELIM  (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
 325
 326 /*
 327  * BR3 and OR3 (SDRAM)
 328  */
 329 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank           */
 330 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 331
 332  /*
 333   * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 334   */
 335 #define CFG_OR_TIMING_SDRAM     0x00000A00
 336
 337 #define CFG_OR3_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
 338 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 339
 340 /*
 341  * BR5 and OR5 (SRAM)
 342  */
 343 #define CFG_SRAM_BASE           0x60000000
 344 #define CFG_SRAM_SIZE           0x00080000
 345
 346 #define CFG_OR_TIMING_SRAM      (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 347                                  OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
 348
 349 #define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 350 #define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
 351
 352
 353 /*
 354  * 4096 Rows from SDRAM example configuration
 355  * 1000 factor s -> ms
 356  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 357  * 4    Number of refresh cycles per period
 358  * 64   Refresh cycle in ms per number of rows
 359  */
 360 #define CFG_PTA_PER_CLK         ((4096 * 64 * 1000) / (4 * 64))
 361
 362 /*
 363  * Memory Periodic Timer Prescaler
 364  */
 365
 366 /* periodic timer for refresh */
 367 #define CFG_MAMR_PTA            39
 368
 369 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 370 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 371 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 372
 373 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 374 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 375 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 376
 377 /*
 378  * MAMR settings for SDRAM
 379  */
 380
 381 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 382                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
 383                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 384 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 385                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
 386                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 387
 388 /*
 389  * MBMR settings for NAND flash
 390  */
 391
 392 #define CFG_MBMR_NAND ( MBMR_WLFB_5X )
 393
 394 /*
 395  * Internal Definitions
 396  *
 397  * Boot Flags
 398  */
 399 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 400 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 401
 402 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 403 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
 404
 405 /*
 406  * JFFS2 partitions
 407  */
 408
 409 /* No command line, one static partition */
 410 #undef CONFIG_JFFS2_CMDLINE
 411 #define CONFIG_JFFS2_DEV                "nand0"
 412 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 413 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 414
 415 /* mtdparts command line support */
 416 /*
 417 #define CONFIG_JFFS2_CMDLINE
 418 #define MTDIDS_DEFAULT          "nor0=nc650-0,nand0=nc650-nand"
 419
 420 #define MTDPARTS_DEFAULT        "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
 421                                         "2560k(cramfs1),2560k(cramfs2)," \
 422                                         "256k(u-boot),256k(env);" \
 423                                 "nc650-nand:4m(nand1),28m(nand2)"
 424 */
 425
 426 #endif  /* __CONFIG_H */