include/configs/NETVIA.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26  * U-Boot port on NetVia board
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  38 #define CONFIG_NETVIA           1       /* ...on a NetVia board         */
  39 #undef  CONFIG_NETVIA_PLL_CLOCK         /* PLL or fixed crystal clock   */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  45
  46 #ifdef CONFIG_NETVIA_PLL_CLOCK
  47 /* XXX make sure that you calculate these two correctly */
  48 #define CFG_GCLK_MF             1350
  49 #define CONFIG_8xx_GCLK_FREQ    44236800
  50 #else
  51 #define CFG_GCLK_MF             1
  52 #define CONFIG_8xx_GCLK_FREQ    50000000
  53 #endif
  54
  55 #if 0
  56 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  57 #else
  58 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  59 #endif
  60
  61 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  62
  63 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  64
  65 #undef  CONFIG_BOOTARGS
  66 #define CONFIG_BOOTCOMMAND                                                      \
  67         "tftpboot; "                                                            \
  68         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  69         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  70         "bootm"
  71
  72 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  73 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  78
  79 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  80
  81 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  82
  83 #undef CONFIG_MAC_PARTITION
  84 #undef CONFIG_DOS_PARTITION
  85
  86 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  87
  88 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  89                                 CFG_CMD_DHCP    )
  90
  91 #define CONFIG_BOARD_PRE_INIT
  92 #define CONFIG_MISC_INIT_R
  93
  94 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  95 #include <cmd_confdefs.h>
  96
  97 /*
  98  * Miscellaneous configurable options
  99  */
 100 #define CFG_LONGHELP                    /* undef to save memory         */
 101 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 102 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 103 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 104 #else
 105 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 106 #endif
 107 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 108 #define CFG_MAXARGS     16              /* max number of command args   */
 109 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 110
 111 #define CFG_MEMTEST_START       0x0300000       /* memtest works on     */
 112 #define CFG_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
 113
 114 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 115
 116 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 117
 118 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 119
 120 /*
 121  * Low Level Configuration Settings
 122  * (address mappings, register initial values, etc.)
 123  * You should know what you are doing if you make changes here.
 124  */
 125 /*-----------------------------------------------------------------------
 126  * Internal Memory Mapped Register
 127  */
 128 #define CFG_IMMR                0xFF000000
 129
 130 /*-----------------------------------------------------------------------
 131  * Definitions for initial stack pointer and data area (in DPRAM)
 132  */
 133 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 134 #define CFG_INIT_RAM_END        0x3000  /* End of used area in DPRAM    */
 135 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 136 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 137 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 138
 139 /*-----------------------------------------------------------------------
 140  * Start addresses for the final memory configuration
 141  * (Set up by the startup code)
 142  * Please note that CFG_SDRAM_BASE _must_ start at 0
 143  */
 144 #define CFG_SDRAM_BASE          0x00000000
 145 #define CFG_FLASH_BASE          0x40000000
 146 #if defined(DEBUG)
 147 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 148 #else
 149 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 150 #endif
 151 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 152 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 153
 154 /*
 155  * For booting Linux, the board info and command line data
 156  * have to be in the first 8 MB of memory, since this is
 157  * the maximum mapped by the Linux kernel during initialization.
 158  */
 159 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 160
 161 /*-----------------------------------------------------------------------
 162  * FLASH organization
 163  */
 164 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 165 #define CFG_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
 166
 167 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 168 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 169
 170 #define CFG_ENV_IS_IN_FLASH     1
 171 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 172 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector     */
 173 #define CFG_ENV_SECT_SIZE       0x10000
 174
 175 /*-----------------------------------------------------------------------
 176  * Cache Configuration
 177  */
 178 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 179 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 180 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 181 #endif
 182
 183 /*-----------------------------------------------------------------------
 184  * SYPCR - System Protection Control                            11-9
 185  * SYPCR can only be written once after reset!
 186  *-----------------------------------------------------------------------
 187  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 188  */
 189 #if defined(CONFIG_WATCHDOG)
 190 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 191                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 192 #else
 193 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 194 #endif
 195
 196 /*-----------------------------------------------------------------------
 197  * SIUMCR - SIU Module Configuration                            11-6
 198  *-----------------------------------------------------------------------
 199  * PCMCIA config., multi-function pin tri-state
 200  */
 201 #ifndef CONFIG_CAN_DRIVER
 202 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 203 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 204 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 205 #endif  /* CONFIG_CAN_DRIVER */
 206
 207 /*-----------------------------------------------------------------------
 208  * TBSCR - Time Base Status and Control                         11-26
 209  *-----------------------------------------------------------------------
 210  * Clear Reference Interrupt Status, Timebase freezing enabled
 211  */
 212 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 213
 214 /*-----------------------------------------------------------------------
 215  * RTCSC - Real-Time Clock Status and Control Register          11-27
 216  *-----------------------------------------------------------------------
 217  */
 218 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 219
 220 /*-----------------------------------------------------------------------
 221  * PISCR - Periodic Interrupt Status and Control                11-31
 222  *-----------------------------------------------------------------------
 223  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 224  */
 225 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 226
 227 /*-----------------------------------------------------------------------
 228  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 229  *-----------------------------------------------------------------------
 230  * Reset PLL lock status sticky bit, timer expired status bit and timer
 231  * interrupt status bit
 232  *
 233  */
 234
 235 #define CFG_PLPRCR      ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 236
 237 /*-----------------------------------------------------------------------
 238  * SCCR - System Clock and reset Control Register               15-27
 239  *-----------------------------------------------------------------------
 240  * Set clock output, timebase and RTC source and divider,
 241  * power management and some other internal clocks
 242  */
 243 #define SCCR_MASK       SCCR_EBDF11
 244 #define CFG_SCCR        (SCCR_TBS     | \
 245                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 246                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 247                          SCCR_DFALCD00)
 248
 249 /*-----------------------------------------------------------------------
 250  *
 251  *-----------------------------------------------------------------------
 252  *
 253  */
 254 /*#define       CFG_DER 0x2002000F*/
 255 #define CFG_DER 0
 256
 257 /*
 258  * Init Memory Controller:
 259  *
 260  * BR0/1 and OR0/1 (FLASH)
 261  */
 262
 263 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 264
 265 /* used to re-map FLASH both when starting from SRAM or FLASH:
 266  * restrict access enough to keep SRAM working (if any)
 267  * but not too much to meddle with FLASH accesses
 268  */
 269 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 270 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 271
 272 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 273 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 274
 275 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 276 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 277 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 278
 279 /*
 280  * BR1/2 and OR1/2 (4MByte Flash Bank x 2)
 281  *
 282  */
 283 #define FLASH0_SIZE     0x00400000      /* 4MByte */
 284 #define FLASH0_BASE     0xF0000000
 285
 286 #define CFG_OR1_PRELIM  ((0xFFFFFFFFLU & ~(FLASH0_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 287 #define CFG_BR1_PRELIM  ((FLASH0_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
 288
 289 #define FLASH1_SIZE     0x00400000
 290 #define FLASH1_BASE     0xF0400000
 291
 292 #define CFG_OR2_PRELIM  ((0xFFFFFFFFLU & ~(FLASH1_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 293 #define CFG_BR2_PRELIM  ((FLASH1_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
 294
 295 /*
 296  * BR3 and OR3 (SDRAM)
 297  *
 298  */
 299 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
 300 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 301
 302 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 303 #define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
 304
 305 #define CFG_OR3_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
 306 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 307
 308 /*
 309  * BR6 (External register)
 310  * 16 bit port size - leds are at high 8 bits
 311  */
 312 #define EXTREG_BASE                     0x30000000      /* external register                            */
 313 #define EXTREG_SIZE                     0x00010000      /* max 64K                                                      */
 314
 315 #define CFG_OR6_PRELIM          ((0xFFFFFFFFLU & ~(EXTREG_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX)
 316 #define CFG_BR6_PRELIM          ((EXTREG_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
 317
 318 /*
 319  * Memory Periodic Timer Prescaler
 320  */
 321
 322 /* periodic timer for refresh */
 323 #define CFG_MAMR_PTA    208
 324
 325 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 326 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 327
 328 /*
 329  * MAMR settings for SDRAM
 330  */
 331
 332 /* 9 column SDRAM */
 333 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 334                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 335                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 336
 337 /*
 338  * Internal Definitions
 339  *
 340  * Boot Flags
 341  */
 342 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 343 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 344
 345 /* Ethernet at SCC2 */
 346 #define CONFIG_SCC2_ENET
 347
 348 #define CONFIG_ARTOS                    /* include ARTOS support */
 349
 350 #endif  /* __CONFIG_H */