include/configs/NX823.h

   1 /*
   2  * (C) Copyright 2001
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2001
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * board/config.h - configuration options, board specific
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  * (easy to change)
  21  */
  22
  23 #define CONFIG_MPC823           1       /* This is a MPC823 CPU     */
  24 #define CONFIG_NX823            1       /* ...on a NEXUS 823  module    */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0x40000000
  27
  28 /*#define  CONFIG_VIDEO         1 */
  29
  30 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_SPEED
  31 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1       */
  32 #undef  CONFIG_8xx_CONS_SMC2
  33 #undef  CONFIG_8xx_CONS_NONE
  34 #define CONFIG_BAUDRATE 57600   /* console baudrate = 115kbps   */
  35 #define CONFIG_BOOTDELAY        2       /* autoboot after 2 seconds */
  36 #define CONFIG_BOOTARGS         "ramdisk_size=8000 "\
  37                                 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
  38                                 "nfsaddrs=10.77.77.20:10.77.77.250"
  39 #define CONFIG_BOOTCOMMAND      "bootm 400e0000"
  40
  41 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  42 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  43 #undef  CONFIG_WATCHDOG                 /* watchdog disabled, for now       */
  44 #define CONFIG_SOURCE
  45
  46 /*
  47  * BOOTP options
  48  */
  49 #define CONFIG_BOOTP_SUBNETMASK
  50 #define CONFIG_BOOTP_GATEWAY
  51 #define CONFIG_BOOTP_HOSTNAME
  52 #define CONFIG_BOOTP_BOOTPATH
  53 #define CONFIG_BOOTP_BOOTFILESIZE
  54
  55
  56 /*
  57  * Command line configuration.
  58  */
  59 #include <config_cmd_default.h>
  60
  61 #define CONFIG_CMD_SOURCE
  62
  63
  64 /* call various generic functions */
  65 #define CONFIG_MISC_INIT_R
  66
  67 /*
  68  * Miscellaneous configurable options
  69  */
  70 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
  71 #if defined(CONFIG_CMD_KGDB)
  72 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
  73 #else
  74 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
  75 #endif
  76 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
  77 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
  78 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  79
  80 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on */
  81 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  82
  83 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
  84
  85 /*
  86  * Low Level Configuration Settings
  87  * (address mappings, register initial values, etc.)
  88  * You should know what you are doing if you make changes here.
  89  */
  90 /*-----------------------------------------------------------------------
  91  * Internal Memory Mapped Register
  92  */
  93 #define CONFIG_SYS_IMMR         0xFFF00000
  94
  95 /*-----------------------------------------------------------------------
  96  * Definitions for initial stack pointer and data area (in DPRAM)
  97  */
  98 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
  99 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 100 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 101 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 102
 103 /*-----------------------------------------------------------------------
 104  * Start addresses for the final memory configuration
 105  * (Set up by the startup code)
 106  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 107  */
 108 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 109 #define CONFIG_SYS_FLASH_BASE           0x40000000
 110 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 112 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 113
 114 /*
 115  * For booting Linux, the board info and command line data
 116  * have to be in the first 8 MB of memory, since this is
 117  * the maximum mapped by the Linux kernel during initialization.
 118  */
 119 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 120
 121 /*-----------------------------------------------------------------------
 122  * FLASH organization
 123  */
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks       */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 126
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)  */
 128 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)  */
 129
 130 #define CONFIG_ENV_IS_IN_FLASH  1
 131 #define xEMBED
 132 #ifdef  EMBED
 133 #define CONFIG_ENV_SIZE         0x200   /* FIXME How big when embedded?? */
 134 #define CONFIG_ENV_ADDR         CONFIG_SYS_MONITOR_BASE
 135 #else
 136 #define CONFIG_ENV_ADDR         0x40020000      /* absolute address for now   */
 137 #define CONFIG_ENV_SIZE         0x20000 /* 8K ouch, this may later be */
 138 #endif
 139
 140 #define CONFIG_SYS_FLASH_SN_BASE        0x4001fff0      /* programmer automagically puts    */
 141 #define CONFIG_SYS_FLASH_SN_SECTOR      0x40000000      /* a serial number here             */
 142 #define CONFIG_SYS_FLASH_SN_BYTES       8
 143
 144 /*-----------------------------------------------------------------------
 145  * Cache Configuration
 146  */
 147 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs          */
 148 #if defined(CONFIG_CMD_KGDB)
 149 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value    */
 150 #endif
 151
 152 /*-----------------------------------------------------------------------
 153  * SYPCR - System Protection Control                            11-9
 154  * SYPCR can only be written once after reset!
 155  *-----------------------------------------------------------------------
 156  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 157  */
 158 #if defined(CONFIG_WATCHDOG)
 159 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 160                          SYPCR_SWE  | SYPCR_SWP)
 161 #else
 162 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 163 #endif
 164
 165 /*-----------------------------------------------------------------------
 166  * SIUMCR - SIU Module Configuration                            12-30
 167  *-----------------------------------------------------------------------
 168  * PCMCIA config., multi-function pin tri-state
 169  */
 170 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00)
 171
 172 /*-----------------------------------------------------------------------
 173  * TBSCR - Time Base Status and Control                         12-16
 174  *-----------------------------------------------------------------------
 175  * Clear Reference Interrupt Status, Timebase freezing enabled
 176  */
 177 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 178
 179 /*-----------------------------------------------------------------------
 180  * RTCSC - Real-Time Clock Status and Control Register          12-18
 181  *-----------------------------------------------------------------------
 182  */
 183 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 184
 185 /*-----------------------------------------------------------------------
 186  * PISCR - Periodic Interrupt Status and Control                12-23
 187  *-----------------------------------------------------------------------
 188  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 189  */
 190 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 191
 192 /*-----------------------------------------------------------------------
 193  * PLPRCR - PLL, Low-Power, and Reset Control Register          5-7
 194  *-----------------------------------------------------------------------
 195  * Reset PLL lock status sticky bit, timer expired status bit and timer
 196  * interrupt status bit
 197  */
 198 #define MPC8XX_SPEED    66666666L
 199 #define MPC8XX_XIN      32768   /* 32.768 kHz crystal */
 200 #define MPC8XX_FACT             (MPC8XX_SPEED/MPC8XX_XIN)
 201 #define CONFIG_SYS_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
 202 #define CONFIG_SYS_PLPRCR               (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
 203
 204 /*-----------------------------------------------------------------------
 205  * SCCR - System Clock and reset Control Register               5-3
 206  *-----------------------------------------------------------------------
 207  * Set clock output, timebase and RTC source and divider,
 208  * power management and some other internal clocks
 209  */
 210 #define SCCR_MASK       SCCR_EBDF11
 211 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 212                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 213                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 214                          SCCR_DFALCD00)
 215
 216 /*-----------------------------------------------------------------------
 217  *
 218  *-----------------------------------------------------------------------
 219  *
 220  */
 221 #define CONFIG_SYS_DER          0
 222
 223 /*
 224  * Init Memory Controller:
 225  *
 226  * BR0 and OR0 (FLASH)
 227  */
 228
 229 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0    */
 230
 231 /* used to re-map FLASH both when starting from SRAM or FLASH:
 232  * restrict access enough to keep SRAM working (if any)
 233  * but not too much to meddle with FLASH accesses
 234  */
 235 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 236 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 237
 238 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0        */
 239 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
 240                                  OR_SCY_8_CLK )
 241
 242 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 243 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 244 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 245
 246 /*
 247  * BR1/2 and OR1/2 (SDRAM)
 248  */
 249 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0    */
 250 #define SDRAM_BASE2_PRELIM      0x20000000      /* SDRAM bank #1    */
 251 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 252
 253 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
 254 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_G5LS | OR_CSNT_SAM)
 255
 256 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 257 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 258 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR1_PRELIM
 259 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 260
 261 /* IO and memory mapped stuff */
 262 #define NX823_IO_OR_AM          0xFFFF0000      /* mask for IO addresses */
 263 #define NX823_IO_BASE           0xFF000000      /* start of IO  */
 264 #define GPOUT_OFFSET            (3<<16)
 265 #define QUART_OFFSET            (4<<16)
 266 #define VIDAC_OFFSET            (5<<16)
 267 #define CPLD_OFFSET             (6<<16)
 268 #define SED1386_OFFSET          (7<<16)
 269
 270 /*
 271  * BR3 and OR3 (general purpose output latches)
 272  */
 273 #define GPOUT_BASE      (NX823_IO_BASE + GPOUT_OFFSET)
 274 #define GPOUT_TIMING    (OR_CSNT_SAM | OR_TRLX | OR_BI)
 275 #define CONFIG_SYS_OR3_PRELIM   (NX823_IO_OR_AM | GPOUT_TIMING)
 276 #define CONFIG_SYS_BR3_PRELIM   (GPOUT_BASE | BR_V)
 277
 278 /*
 279  * BR4 and OR4 (QUART)
 280  */
 281 #define QUART_BASE      (NX823_IO_BASE + QUART_OFFSET)
 282 #define QUART_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
 283 #define CONFIG_SYS_OR4_PRELIM   (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
 284 #define CONFIG_SYS_BR4_PRELIM   (QUART_BASE | BR_PS_8 | BR_V)
 285
 286 /*
 287  * BR5 and OR5 (Video DAC)
 288  */
 289 #define VIDAC_BASE      (NX823_IO_BASE + VIDAC_OFFSET)
 290 #define VIDAC_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
 291 #define CONFIG_SYS_OR5_PRELIM   (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
 292 #define CONFIG_SYS_BR5_PRELIM   (VIDAC_BASE | BR_PS_8 | BR_V)
 293
 294 /*
 295  * BR6 and OR6 (CPLD)
 296  * FIXME timing not verified for CPLD
 297  */
 298 #define CPLD_BASE       (NX823_IO_BASE + CPLD_OFFSET)
 299 #define CPLD_TIMING     (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
 300 #define CONFIG_SYS_OR6_PRELIM   (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
 301 #define CONFIG_SYS_BR6_PRELIM   (CPLD_BASE | BR_PS_8 | BR_V )
 302
 303 /*
 304  * BR7 and OR7 (SED1386)
 305  * FIXME timing not verified for SED controller
 306  */
 307 #define SED1386_BASE    0xF7000000
 308 #define CONFIG_SYS_OR7_PRELIM   (0xFF000000 | OR_BI | OR_SETA)
 309 #define CONFIG_SYS_BR7_PRELIM   (SED1386_BASE | BR_PS_16 | BR_V )
 310
 311 /*
 312  * Memory Periodic Timer Prescaler
 313  */
 314
 315 /* periodic timer for refresh */
 316 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz   */
 317
 318 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 319 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks  */
 320 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank   */
 321
 322 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 323 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8  /* setting for 2 banks  */
 324 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank   */
 325
 326 /*
 327  * MAMR settings for SDRAM
 328  */
 329
 330 /* 8 column SDRAM */
 331 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 332                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 333                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 334 /* 9 column SDRAM */
 335 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 336                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 337                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 338
 339 #define CONFIG_ENV_OVERWRITE    /* allow changes to ethaddr (for now)   */
 340 #define CONFIG_ETHADDR          00:10:20:30:40:50
 341 #define CONFIG_IPADDR           10.77.77.20
 342 #define CONFIG_SERVERIP         10.77.77.250
 343
 344 #endif /* __CONFIG_H */