include/configs/NX823.h

   1 /*
   2  * (C) Copyright 2001
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2001
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC823           1       /* This is a MPC823 CPU     */
  40 #define CONFIG_NX823            1       /* ...on a NEXUS 823  module    */
  41
  42 #define CONFIG_SYS_TEXT_BASE    0x40000000
  43
  44 /*#define  CONFIG_VIDEO         1 */
  45
  46 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_SPEED
  47 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1       */
  48 #undef  CONFIG_8xx_CONS_SMC2
  49 #undef  CONFIG_8xx_CONS_NONE
  50 #define CONFIG_BAUDRATE 57600   /* console baudrate = 115kbps   */
  51 #define CONFIG_BOOTDELAY        2       /* autoboot after 2 seconds */
  52 #define CONFIG_BOOTARGS         "ramdisk_size=8000 "\
  53                                 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
  54                                 "nfsaddrs=10.77.77.20:10.77.77.250"
  55 #define CONFIG_BOOTCOMMAND      "bootm 400e0000"
  56
  57 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  58 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  59 #undef  CONFIG_WATCHDOG                 /* watchdog disabled, for now       */
  60 #define CONFIG_SOURCE
  61
  62 /*
  63  * BOOTP options
  64  */
  65 #define CONFIG_BOOTP_SUBNETMASK
  66 #define CONFIG_BOOTP_GATEWAY
  67 #define CONFIG_BOOTP_HOSTNAME
  68 #define CONFIG_BOOTP_BOOTPATH
  69 #define CONFIG_BOOTP_BOOTFILESIZE
  70
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #define CONFIG_CMD_SOURCE
  78
  79
  80 /* call various generic functions */
  81 #define CONFIG_MISC_INIT_R
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
  87 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
  88 #if defined(CONFIG_CMD_KGDB)
  89 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
  90 #else
  91 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
  92 #endif
  93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
  94 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
  95 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  96
  97 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on */
  98 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  99
 100 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 101
 102 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 103
 104 /*
 105  * Low Level Configuration Settings
 106  * (address mappings, register initial values, etc.)
 107  * You should know what you are doing if you make changes here.
 108  */
 109 /*-----------------------------------------------------------------------
 110  * Internal Memory Mapped Register
 111  */
 112 #define CONFIG_SYS_IMMR         0xFFF00000
 113
 114 /*-----------------------------------------------------------------------
 115  * Definitions for initial stack pointer and data area (in DPRAM)
 116  */
 117 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 118 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 120 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 121
 122 /*-----------------------------------------------------------------------
 123  * Start addresses for the final memory configuration
 124  * (Set up by the startup code)
 125  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 126  */
 127 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 128 #define CONFIG_SYS_FLASH_BASE           0x40000000
 129 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 131 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 132
 133 /*
 134  * For booting Linux, the board info and command line data
 135  * have to be in the first 8 MB of memory, since this is
 136  * the maximum mapped by the Linux kernel during initialization.
 137  */
 138 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 139
 140 /*-----------------------------------------------------------------------
 141  * FLASH organization
 142  */
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks       */
 144 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 145
 146 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)  */
 147 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)  */
 148
 149 #define CONFIG_ENV_IS_IN_FLASH  1
 150 #define xEMBED
 151 #ifdef  EMBED
 152 #define CONFIG_ENV_SIZE         0x200   /* FIXME How big when embedded?? */
 153 #define CONFIG_ENV_ADDR         CONFIG_SYS_MONITOR_BASE
 154 #else
 155 #define CONFIG_ENV_ADDR         0x40020000      /* absolute address for now   */
 156 #define CONFIG_ENV_SIZE         0x20000 /* 8K ouch, this may later be */
 157 #endif
 158
 159 #define CONFIG_SYS_FLASH_SN_BASE        0x4001fff0      /* programmer automagically puts    */
 160 #define CONFIG_SYS_FLASH_SN_SECTOR      0x40000000      /* a serial number here             */
 161 #define CONFIG_SYS_FLASH_SN_BYTES       8
 162
 163 /*-----------------------------------------------------------------------
 164  * Cache Configuration
 165  */
 166 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs          */
 167 #if defined(CONFIG_CMD_KGDB)
 168 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value    */
 169 #endif
 170
 171 /*-----------------------------------------------------------------------
 172  * SYPCR - System Protection Control                            11-9
 173  * SYPCR can only be written once after reset!
 174  *-----------------------------------------------------------------------
 175  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 176  */
 177 #if defined(CONFIG_WATCHDOG)
 178 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 179                          SYPCR_SWE  | SYPCR_SWP)
 180 #else
 181 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 182 #endif
 183
 184 /*-----------------------------------------------------------------------
 185  * SIUMCR - SIU Module Configuration                            12-30
 186  *-----------------------------------------------------------------------
 187  * PCMCIA config., multi-function pin tri-state
 188  */
 189 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00)
 190
 191 /*-----------------------------------------------------------------------
 192  * TBSCR - Time Base Status and Control                         12-16
 193  *-----------------------------------------------------------------------
 194  * Clear Reference Interrupt Status, Timebase freezing enabled
 195  */
 196 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 197
 198 /*-----------------------------------------------------------------------
 199  * RTCSC - Real-Time Clock Status and Control Register          12-18
 200  *-----------------------------------------------------------------------
 201  */
 202 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 203
 204 /*-----------------------------------------------------------------------
 205  * PISCR - Periodic Interrupt Status and Control                12-23
 206  *-----------------------------------------------------------------------
 207  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 208  */
 209 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 210
 211 /*-----------------------------------------------------------------------
 212  * PLPRCR - PLL, Low-Power, and Reset Control Register          5-7
 213  *-----------------------------------------------------------------------
 214  * Reset PLL lock status sticky bit, timer expired status bit and timer
 215  * interrupt status bit
 216  */
 217 #define MPC8XX_SPEED    66666666L
 218 #define MPC8XX_XIN      32768   /* 32.768 kHz crystal */
 219 #define MPC8XX_FACT             (MPC8XX_SPEED/MPC8XX_XIN)
 220 #define CONFIG_SYS_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
 221 #define CONFIG_SYS_PLPRCR               (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
 222
 223 /*-----------------------------------------------------------------------
 224  * SCCR - System Clock and reset Control Register               5-3
 225  *-----------------------------------------------------------------------
 226  * Set clock output, timebase and RTC source and divider,
 227  * power management and some other internal clocks
 228  */
 229 #define SCCR_MASK       SCCR_EBDF11
 230 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 231                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 232                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 233                          SCCR_DFALCD00)
 234
 235 /*-----------------------------------------------------------------------
 236  *
 237  *-----------------------------------------------------------------------
 238  *
 239  */
 240 #define CONFIG_SYS_DER          0
 241
 242 /*
 243  * Init Memory Controller:
 244  *
 245  * BR0 and OR0 (FLASH)
 246  */
 247
 248 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0    */
 249
 250 /* used to re-map FLASH both when starting from SRAM or FLASH:
 251  * restrict access enough to keep SRAM working (if any)
 252  * but not too much to meddle with FLASH accesses
 253  */
 254 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 255 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 256
 257 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0        */
 258 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
 259                                  OR_SCY_8_CLK )
 260
 261 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 262 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 263 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 264
 265 /*
 266  * BR1/2 and OR1/2 (SDRAM)
 267  */
 268 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0    */
 269 #define SDRAM_BASE2_PRELIM      0x20000000      /* SDRAM bank #1    */
 270 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 271
 272 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
 273 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_G5LS | OR_CSNT_SAM)
 274
 275 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 276 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 277 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR1_PRELIM
 278 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 279
 280 /* IO and memory mapped stuff */
 281 #define NX823_IO_OR_AM          0xFFFF0000      /* mask for IO addresses */
 282 #define NX823_IO_BASE           0xFF000000      /* start of IO  */
 283 #define GPOUT_OFFSET            (3<<16)
 284 #define QUART_OFFSET            (4<<16)
 285 #define VIDAC_OFFSET            (5<<16)
 286 #define CPLD_OFFSET             (6<<16)
 287 #define SED1386_OFFSET          (7<<16)
 288
 289 /*
 290  * BR3 and OR3 (general purpose output latches)
 291  */
 292 #define GPOUT_BASE      (NX823_IO_BASE + GPOUT_OFFSET)
 293 #define GPOUT_TIMING    (OR_CSNT_SAM | OR_TRLX | OR_BI)
 294 #define CONFIG_SYS_OR3_PRELIM   (NX823_IO_OR_AM | GPOUT_TIMING)
 295 #define CONFIG_SYS_BR3_PRELIM   (GPOUT_BASE | BR_V)
 296
 297 /*
 298  * BR4 and OR4 (QUART)
 299  */
 300 #define QUART_BASE      (NX823_IO_BASE + QUART_OFFSET)
 301 #define QUART_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
 302 #define CONFIG_SYS_OR4_PRELIM   (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
 303 #define CONFIG_SYS_BR4_PRELIM   (QUART_BASE | BR_PS_8 | BR_V)
 304
 305 /*
 306  * BR5 and OR5 (Video DAC)
 307  */
 308 #define VIDAC_BASE      (NX823_IO_BASE + VIDAC_OFFSET)
 309 #define VIDAC_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
 310 #define CONFIG_SYS_OR5_PRELIM   (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
 311 #define CONFIG_SYS_BR5_PRELIM   (VIDAC_BASE | BR_PS_8 | BR_V)
 312
 313 /*
 314  * BR6 and OR6 (CPLD)
 315  * FIXME timing not verified for CPLD
 316  */
 317 #define CPLD_BASE       (NX823_IO_BASE + CPLD_OFFSET)
 318 #define CPLD_TIMING     (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
 319 #define CONFIG_SYS_OR6_PRELIM   (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
 320 #define CONFIG_SYS_BR6_PRELIM   (CPLD_BASE | BR_PS_8 | BR_V )
 321
 322 /*
 323  * BR7 and OR7 (SED1386)
 324  * FIXME timing not verified for SED controller
 325  */
 326 #define SED1386_BASE    0xF7000000
 327 #define CONFIG_SYS_OR7_PRELIM   (0xFF000000 | OR_BI | OR_SETA)
 328 #define CONFIG_SYS_BR7_PRELIM   (SED1386_BASE | BR_PS_16 | BR_V )
 329
 330 /*
 331  * Memory Periodic Timer Prescaler
 332  */
 333
 334 /* periodic timer for refresh */
 335 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz   */
 336
 337 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 338 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks  */
 339 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank   */
 340
 341 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 342 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8  /* setting for 2 banks  */
 343 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank   */
 344
 345 /*
 346  * MAMR settings for SDRAM
 347  */
 348
 349 /* 8 column SDRAM */
 350 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 351                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 352                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 353 /* 9 column SDRAM */
 354 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 355                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 356                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 357
 358 #define CONFIG_ENV_OVERWRITE    /* allow changes to ethaddr (for now)   */
 359 #define CONFIG_ETHADDR          00:10:20:30:40:50
 360 #define CONFIG_IPADDR           10.77.77.20
 361 #define CONFIG_SERVERIP         10.77.77.250
 362
 363 #endif /* __CONFIG_H */