include/configs/OXC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC824X          1
  39 #define CONFIG_MPC8240          1
  40 #define CONFIG_OXC              1
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  43
  44 #define CONFIG_IDENT_STRING     " [oxc] "
  45
  46 #define CONFIG_WATCHDOG         1
  47 #define CONFIG_SHOW_ACTIVITY    1
  48 #define CONFIG_SHOW_BOOT_PROGRESS 1
  49
  50 #define CONFIG_CONS_INDEX       1
  51 #define CONFIG_BAUDRATE         9600
  52 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  53
  54 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_ELF)
  55
  56 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any)       */
  57 #include <cmd_confdefs.h>
  58
  59 /*
  60  * Miscellaneous configurable options
  61  */
  62 #define CFG_LONGHELP            1               /* undef to save memory         */
  63 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
  64 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  65 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size    */
  66 #define CFG_MAXARGS             16              /* max number of command args   */
  67 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  68 #define CFG_LOAD_ADDR           0x00100000      /* default load address         */
  69 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
  70
  71 #define CONFIG_MISC_INIT_R      1               /* call misc_init_r() on init   */
  72
  73 /*-----------------------------------------------------------------------
  74  * Boot options
  75  */
  76
  77 #define CONFIG_SERVERIP         10.0.0.1
  78 #define CONFIG_GATEWAYIP        10.0.0.1
  79 #define CONFIG_NETMASK          255.255.255.0
  80 #define CONFIG_LOADADDR         0x10000
  81 #define CONFIG_BOOTFILE         "/mnt/ide0/p2/usr/tftp/oxc.elf"
  82 #define CONFIG_BOOTCOMMAND      "tftp 0x10000 ; bootelf 0x10000"
  83 #define CONFIG_BOOTDELAY        10
  84
  85 #define CFG_OXC_GENERATE_IP     1               /* Generate IP automatically    */
  86 #define CFG_OXC_IPMASK          0x0A000000      /* 10.0.0.x                     */
  87
  88 /*-----------------------------------------------------------------------
  89  * PCI stuff
  90  */
  91
  92 #define CONFIG_PCI                              /* include pci support          */
  93
  94 #define CONFIG_NET_MULTI                        /* Multi ethernet cards support */
  95
  96 #define CONFIG_EEPRO100                         /* Ethernet Express PRO 100     */
  97 #define CFG_RX_ETH_BUFFER       8               /* use 8 rx buffer on eepro100  */
  98
  99 #define PCI_ENET0_IOADDR        0x80000000
 100 #define PCI_ENET0_MEMADDR       0x80000000
 101 #define PCI_ENET1_IOADDR        0x81000000
 102 #define PCI_ENET1_MEMADDR       0x81000000
 103
 104 /*-----------------------------------------------------------------------
 105  * FLASH
 106  */
 107
 108 #define CFG_FLASH_PRELIMBASE    0xFF800000
 109 #define CFG_FLASH_BASE          (0-flash_info[0].size)
 110
 111 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 112 #define CFG_MAX_FLASH_SECT      32      /* max number of sectors on one chip    */
 113
 114 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 115 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 116
 117 /*-----------------------------------------------------------------------
 118  * RAM
 119  */
 120
 121 #define CFG_SDRAM_BASE          0x00000000
 122 #define CFG_MAX_RAM_SIZE        0x10000000
 123
 124 #define CFG_RESET_ADDRESS       0xFFF00100
 125
 126 #define CFG_MONITOR_BASE        TEXT_BASE
 127 #define CFG_MONITOR_LEN         0x00030000
 128
 129 #if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE)
 130 # define CFG_RAMBOOT            1
 131 #else
 132 # undef CFG_RAMBOOT
 133 #endif
 134
 135 #define CFG_INIT_RAM_ADDR       0x40000000
 136 #define CFG_INIT_RAM_END        0x1000
 137
 138 #define CFG_GBL_DATA_SIZE       128
 139 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 140 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 141
 142 #define CFG_MALLOC_LEN          (512 << 10)     /* Reserve 512 kB for malloc()  */
 143
 144 #define CFG_MEMTEST_START       0x00000000      /* memtest works on             */
 145 #define CFG_MEMTEST_END         0x04000000      /* 0 ... 32 MB in DRAM          */
 146
 147 /*-----------------------------------------------------------------------
 148  * Memory mapping
 149  */
 150
 151 #define CFG_CPLD_BASE           0xff000000      /* CPLD registers */
 152 #define CFG_CPLD_WATCHDOG       (CFG_CPLD_BASE)                 /* Watchdog */
 153 #define CFG_CPLD_RESET          (CFG_CPLD_BASE + 0x040000)      /* Minor resets */
 154 #define CFG_UART_BASE           (CFG_CPLD_BASE + 0x700000)      /* debug UART */
 155
 156 /*-----------------------------------------------------------------------
 157  * NS16550 Configuration
 158  */
 159
 160 #define CFG_NS16550
 161 #define CFG_NS16550_SERIAL
 162 #define CFG_NS16550_REG_SIZE    -4
 163 #define CFG_NS16550_CLK         1843200
 164 #define CFG_NS16550_COM1        CFG_UART_BASE
 165
 166 /*-----------------------------------------------------------------------
 167  * I2C Bus
 168  */
 169
 170 #define CONFIG_I2C              1               /* I2C support on ... */
 171 #define CONFIG_HARD_I2C         1               /* ... hardware one */
 172 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 173 #define CFG_I2C_SLAVE           0x7F            /* I2C slave address */
 174
 175 #define CFG_I2C_EXPANDER0_ADDR  0x20            /* PCF8574 expander 0 addrerr */
 176 #define CFG_I2C_EXPANDER1_ADDR  0x21            /* PCF8574 expander 1 addrerr */
 177 #define CFG_I2C_EXPANDER2_ADDR  0x26            /* PCF8574 expander 2 addrerr */
 178
 179 /*-----------------------------------------------------------------------
 180  * Environment
 181  */
 182
 183 #define CFG_ENV_IS_IN_FLASH     1
 184 #define CFG_ENV_ADDR            0xFFF30000      /* Offset of Environment Sector */
 185 #define CFG_ENV_SIZE            0x00010000      /* Total Size of Environment Sector */
 186 #define CFG_ENV_IS_EMBEDDED     1               /* short-cut compile-time test  */
 187 #define CONFIG_ENV_OVERWRITE    1               /* Allow modifying the environment */
 188
 189 /*
 190  * Low Level Configuration Settings
 191  * (address mappings, register initial values, etc.)
 192  * You should know what you are doing if you make changes here.
 193  */
 194
 195 #define CONFIG_SYS_CLK_FREQ  33000000   /* external frequency to pll */
 196 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
 197
 198 #define CFG_EUMB_ADDR           0xFC000000
 199
 200 /* MCCR1 */
 201 #define CFG_ROMNAL              0       /* rom/flash next access time           */
 202 #define CFG_ROMFAL              19      /* rom/flash access time                */
 203
 204 /* MCCR2 */
 205 #define CFG_ASRISE              15      /* ASRISE=15 clocks                     */
 206 #define CFG_ASFALL              3       /* ASFALL=3 clocks                      */
 207 #define CFG_REFINT              1000    /* REFINT=1000 clocks                   */
 208
 209 /* MCCR3 */
 210 #define CFG_BSTOPRE             0x35c   /* Burst To Precharge                   */
 211 #define CFG_REFREC              7       /* Refresh to activate interval         */
 212 #define CFG_RDLAT               4       /* data latency from read command       */
 213
 214 /* MCCR4 */
 215 #define CFG_PRETOACT            2       /* Precharge to activate interval       */
 216 #define CFG_ACTTOPRE            5       /* Activate to Precharge interval       */
 217 #define CFG_ACTORW              2       /* Activate to R/W                      */
 218 #define CFG_SDMODE_CAS_LAT      3       /* SDMODE CAS latency                   */
 219 #define CFG_SDMODE_WRAP         0       /* SDMODE wrap type                     */
 220 #define CFG_SDMODE_BURSTLEN     3       /* SDMODE Burst length 2=4, 3=8         */
 221 #define CFG_REGISTERD_TYPE_BUFFER   1
 222
 223 /* memory bank settings*/
 224 /*
 225  * only bits 20-29 are actually used from these vales to set the
 226  * start/end address the upper two bits will be 0, and the lower 20
 227  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 228  * end address
 229  */
 230 #define CFG_BANK0_START         0x00000000
 231 #define CFG_BANK0_END           (CFG_MAX_RAM_SIZE - 1)
 232 #define CFG_BANK0_ENABLE        1
 233 #define CFG_BANK1_START         0x00000000
 234 #define CFG_BANK1_END           0x00000000
 235 #define CFG_BANK1_ENABLE        0
 236 #define CFG_BANK2_START         0x00000000
 237 #define CFG_BANK2_END           0x00000000
 238 #define CFG_BANK2_ENABLE        0
 239 #define CFG_BANK3_START         0x00000000
 240 #define CFG_BANK3_END           0x00000000
 241 #define CFG_BANK3_ENABLE        0
 242 #define CFG_BANK4_START         0x00000000
 243 #define CFG_BANK4_END           0x00000000
 244 #define CFG_BANK4_ENABLE        0
 245 #define CFG_BANK5_START         0x00000000
 246 #define CFG_BANK5_END           0x00000000
 247 #define CFG_BANK5_ENABLE        0
 248 #define CFG_BANK6_START         0x00000000
 249 #define CFG_BANK6_END           0x00000000
 250 #define CFG_BANK6_ENABLE        0
 251 #define CFG_BANK7_START         0x00000000
 252 #define CFG_BANK7_END           0x00000000
 253 #define CFG_BANK7_ENABLE        0
 254 /*
 255  * Memory bank enable bitmask, specifying which of the banks defined above
 256  are actually present. MSB is for bank #7, LSB is for bank #0.
 257  */
 258 #define CFG_BANK_ENABLE         0x01
 259
 260 #define CFG_ODCR                0xff    /* configures line driver impedances,   */
 261                                         /* see 8240 book for bit definitions    */
 262 #define CFG_PGMAX               0x32    /* how long the 8240 retains the        */
 263                                         /* currently accessed page in memory    */
 264                                         /* see 8240 book for details            */
 265
 266 /* SDRAM 0 - 256MB */
 267 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 268 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 269
 270 /* stack in DCACHE @ 1GB (no backing mem) */
 271 #define CFG_IBAT1L      (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 272 #define CFG_IBAT1U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 273
 274 /* PCI memory */
 275 #define CFG_IBAT2L      (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 276 #define CFG_IBAT2U      (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 277
 278 /* Flash, config addrs, etc */
 279 #define CFG_IBAT3L      (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 280 #define CFG_IBAT3U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 281
 282 #define CFG_DBAT0L      CFG_IBAT0L
 283 #define CFG_DBAT0U      CFG_IBAT0U
 284 #define CFG_DBAT1L      CFG_IBAT1L
 285 #define CFG_DBAT1U      CFG_IBAT1U
 286 #define CFG_DBAT2L      CFG_IBAT2L
 287 #define CFG_DBAT2U      CFG_IBAT2U
 288 #define CFG_DBAT3L      CFG_IBAT3L
 289 #define CFG_DBAT3U      CFG_IBAT3U
 290
 291 /*
 292  * For booting Linux, the board info and command line data
 293  * have to be in the first 8 MB of memory, since this is
 294  * the maximum mapped by the Linux kernel during initialization.
 295  */
 296 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 297
 298 /*-----------------------------------------------------------------------
 299  * Cache Configuration
 300  */
 301 #define CFG_CACHELINE_SIZE      32      /* For MPC8240 CPU                      */
 302 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 303 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 304 #endif
 305
 306 /*
 307  * Internal Definitions
 308  *
 309  * Boot Flags
 310  */
 311 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 312 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 313
 314 #endif  /* __CONFIG_H */