include/configs/P1010RDB.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #define CONFIG_P1010
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #include <asm/config_mpc85xx.h>
  19 #define CONFIG_NAND_FSL_IFC
  20
  21 #ifdef CONFIG_SDCARD
  22 #define CONFIG_SPL_MMC_MINIMAL
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  25 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  26 #define CONFIG_SYS_TEXT_BASE            0x11001000
  27 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  28 #define CONFIG_SPL_PAD_TO               0x18000
  29 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  30 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  31 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  32 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  33 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  34 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  35 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  36 #define CONFIG_SPL_MMC_BOOT
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_COMMON_INIT_DDR
  39 #endif
  40 #endif
  41
  42 #ifdef CONFIG_SPIFLASH
  43 #ifdef CONFIG_SECURE_BOOT
  44 #define CONFIG_RAMBOOT_SPIFLASH
  45 #define CONFIG_SYS_TEXT_BASE            0x11000000
  46 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  47 #else
  48 #define CONFIG_SPL_SPI_SUPPORT
  49 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  51 #define CONFIG_SPL_FLUSH_IMAGE
  52 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  53 #define CONFIG_FSL_LAW         /* Use common FSL init code */
  54 #define CONFIG_SYS_TEXT_BASE                    0x11001000
  55 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
  56 #define CONFIG_SPL_PAD_TO                       0x18000
  57 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  63 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  64 #define CONFIG_SPL_SPI_BOOT
  65 #ifdef CONFIG_SPL_BUILD
  66 #define CONFIG_SPL_COMMON_INIT_DDR
  67 #endif
  68 #endif
  69 #endif
  70
  71 #ifdef CONFIG_NAND
  72 #ifdef CONFIG_SECURE_BOOT
  73 #define CONFIG_SPL_INIT_MINIMAL
  74 #define CONFIG_SPL_NAND_BOOT
  75 #define CONFIG_SPL_FLUSH_IMAGE
  76 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  77
  78 #define CONFIG_SYS_TEXT_BASE            0x00201000
  79 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  80 #define CONFIG_SPL_MAX_SIZE             8192
  81 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  82 #define CONFIG_SPL_RELOC_STACK          0x00100000
  83 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  84 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  85 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  86 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  87 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  88 #else
  89 #ifdef CONFIG_TPL_BUILD
  90 #define CONFIG_SPL_NAND_BOOT
  91 #define CONFIG_SPL_FLUSH_IMAGE
  92 #define CONFIG_SPL_NAND_INIT
  93 #define CONFIG_SPL_COMMON_INIT_DDR
  94 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  95 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  97 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  98 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  99 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 100 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 101 #elif defined(CONFIG_SPL_BUILD)
 102 #define CONFIG_SPL_INIT_MINIMAL
 103 #define CONFIG_SPL_NAND_MINIMAL
 104 #define CONFIG_SPL_FLUSH_IMAGE
 105 #define CONFIG_SPL_TEXT_BASE            0xff800000
 106 #define CONFIG_SPL_MAX_SIZE             8192
 107 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 108 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
 109 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
 110 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 111 #endif
 112 #define CONFIG_SPL_PAD_TO       0x20000
 113 #define CONFIG_TPL_PAD_TO       0x20000
 114 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
 115 #define CONFIG_SYS_TEXT_BASE    0x11001000
 116 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 117 #endif
 118 #endif
 119
 120 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 121 #define CONFIG_RAMBOOT_NAND
 122 #define CONFIG_SYS_TEXT_BASE            0x11000000
 123 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 124 #endif
 125
 126 #ifndef CONFIG_SYS_TEXT_BASE
 127 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 128 #endif
 129
 130 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 131 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 132 #endif
 133
 134 #ifdef CONFIG_SPL_BUILD
 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 136 #else
 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 138 #endif
 139
 140 /* High Level Configuration Options */
 141 #define CONFIG_BOOKE                    /* BOOKE */
 142 #define CONFIG_E500                     /* BOOKE e500 family */
 143 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 144 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 145 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 146
 147 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 148 #if defined(CONFIG_PCI)
 149 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 150 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 151 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 152 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 153 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 154 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 155
 156 #define CONFIG_CMD_PCI
 157
 158 /*
 159  * PCI Windows
 160  * Memory space is mapped 1-1, but I/O space must start from 0.
 161  */
 162 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 163 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 164 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 165 #ifdef CONFIG_PHYS_64BIT
 166 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 167 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 168 #else
 169 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 170 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 171 #endif
 172 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 173 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 174 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 175 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 176 #ifdef CONFIG_PHYS_64BIT
 177 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 178 #else
 179 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 180 #endif
 181
 182 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 183 #if defined(CONFIG_P1010RDB_PA)
 184 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 185 #elif defined(CONFIG_P1010RDB_PB)
 186 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 187 #endif
 188 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 189 #ifdef CONFIG_PHYS_64BIT
 190 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 191 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 192 #else
 193 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 194 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 195 #endif
 196 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 197 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 198 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 199 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 200 #ifdef CONFIG_PHYS_64BIT
 201 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 202 #else
 203 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 204 #endif
 205
 206 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 207
 208 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 209 #define CONFIG_DOS_PARTITION
 210 #endif
 211
 212 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 213 #define CONFIG_TSEC_ENET
 214 #define CONFIG_ENV_OVERWRITE
 215
 216 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 217 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 218
 219 #define CONFIG_MISC_INIT_R
 220 #define CONFIG_HWCONFIG
 221 /*
 222  * These can be toggled for performance analysis, otherwise use default.
 223  */
 224 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 225 #define CONFIG_BTB                      /* toggle branch predition */
 226
 227 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 228
 229 #define CONFIG_ENABLE_36BIT_PHYS
 230
 231 #ifdef CONFIG_PHYS_64BIT
 232 #define CONFIG_ADDR_MAP                 1
 233 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 234 #endif
 235
 236 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 237 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 238 #define CONFIG_PANIC_HANG               /* do not reset board on panic */
 239
 240 /* DDR Setup */
 241 #define CONFIG_SYS_FSL_DDR3
 242 #define CONFIG_SYS_DDR_RAW_TIMING
 243 #define CONFIG_DDR_SPD
 244 #define CONFIG_SYS_SPD_BUS_NUM          1
 245 #define SPD_EEPROM_ADDRESS              0x52
 246
 247 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 248
 249 #ifndef __ASSEMBLY__
 250 extern unsigned long get_sdram_size(void);
 251 #endif
 252 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 253 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 254 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 255
 256 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 257 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 258
 259 /* DDR3 Controller Settings */
 260 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 261 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 262 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 263 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 264 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 265 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 266 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 267 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 268 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 269 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 270 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 271 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 272 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 273 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 274 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 275
 276 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 277 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 278 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 279 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 280 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 281 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 282 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 283 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 284 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 285
 286 /* settings for DDR3 at 667MT/s */
 287 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 288 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 289 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 290 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 291 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 292 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 293 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 294 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 295 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 296
 297 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 298 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 299
 300 /* Don't relocate CCSRBAR while in NAND_SPL */
 301 #ifdef CONFIG_SPL_BUILD
 302 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 303 #endif
 304
 305 /*
 306  * Memory map
 307  *
 308  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 309  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 310  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 311  *
 312  * Localbus non-cacheable
 313  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 314  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 315  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 316  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 317  */
 318
 319 /*
 320  * IFC Definitions
 321  */
 322 /* NOR Flash on IFC */
 323 #ifdef CONFIG_SPL_BUILD
 324 #define CONFIG_SYS_NO_FLASH
 325 #endif
 326
 327 #define CONFIG_SYS_FLASH_BASE           0xee000000
 328 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 329
 330 #ifdef CONFIG_PHYS_64BIT
 331 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 332 #else
 333 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 334 #endif
 335
 336 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 337                                 CSPR_PORT_SIZE_16 | \
 338                                 CSPR_MSEL_NOR | \
 339                                 CSPR_V)
 340 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 341 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 342 /* NOR Flash Timing Params */
 343 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 344                                 FTIM0_NOR_TEADC(0x5) | \
 345                                 FTIM0_NOR_TEAHC(0x5)
 346 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 347                                 FTIM1_NOR_TRAD_NOR(0x0f)
 348 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 349                                 FTIM2_NOR_TCH(0x4) | \
 350                                 FTIM2_NOR_TWP(0x1c)
 351 #define CONFIG_SYS_NOR_FTIM3    0x0
 352
 353 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 354 #define CONFIG_SYS_FLASH_QUIET_TEST
 355 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 356 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 357
 358 #undef CONFIG_SYS_FLASH_CHECKSUM
 359 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 360 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 361
 362 /* CFI for NOR Flash */
 363 #define CONFIG_FLASH_CFI_DRIVER
 364 #define CONFIG_SYS_FLASH_CFI
 365 #define CONFIG_SYS_FLASH_EMPTY_INFO
 366 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 367
 368 /* NAND Flash on IFC */
 369 #define CONFIG_SYS_NAND_BASE            0xff800000
 370 #ifdef CONFIG_PHYS_64BIT
 371 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 372 #else
 373 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 374 #endif
 375
 376 #define CONFIG_MTD_DEVICE
 377 #define CONFIG_MTD_PARTITION
 378 #define CONFIG_CMD_MTDPARTS
 379 #define MTDIDS_DEFAULT                  "nand0=ff800000.flash"
 380 #define MTDPARTS_DEFAULT                \
 381         "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
 382
 383 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 384                                 | CSPR_PORT_SIZE_8      \
 385                                 | CSPR_MSEL_NAND        \
 386                                 | CSPR_V)
 387 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 388
 389 #if defined(CONFIG_P1010RDB_PA)
 390 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 391                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 392                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 393                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 394                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 395                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 396                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 397 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 398
 399 #elif defined(CONFIG_P1010RDB_PB)
 400 #define CONFIG_SYS_NAND_ONFI_DETECTION
 401 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 402                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 403                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 404                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 405                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 406                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 407                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 408 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 409 #endif
 410
 411 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 412 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 413 #define CONFIG_CMD_NAND
 414
 415 #if defined(CONFIG_P1010RDB_PA)
 416 /* NAND Flash Timing Params */
 417 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 418                                         FTIM0_NAND_TWP(0x0C)   | \
 419                                         FTIM0_NAND_TWCHT(0x04) | \
 420                                         FTIM0_NAND_TWH(0x05)
 421 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 422                                         FTIM1_NAND_TWBE(0x1d)  | \
 423                                         FTIM1_NAND_TRR(0x07)   | \
 424                                         FTIM1_NAND_TRP(0x0c)
 425 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 426                                         FTIM2_NAND_TREH(0x05) | \
 427                                         FTIM2_NAND_TWHRE(0x0f)
 428 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 429
 430 #elif defined(CONFIG_P1010RDB_PB)
 431 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 432 /* ONFI NAND Flash mode0 Timing Params */
 433 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 434                                         FTIM0_NAND_TWP(0x18)   | \
 435                                         FTIM0_NAND_TWCHT(0x07) | \
 436                                         FTIM0_NAND_TWH(0x0a))
 437 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 438                                         FTIM1_NAND_TWBE(0x39)  | \
 439                                         FTIM1_NAND_TRR(0x0e)   | \
 440                                         FTIM1_NAND_TRP(0x18))
 441 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 442                                         FTIM2_NAND_TREH(0x0a)  | \
 443                                         FTIM2_NAND_TWHRE(0x1e))
 444 #define CONFIG_SYS_NAND_FTIM3   0x0
 445 #endif
 446
 447 #define CONFIG_SYS_NAND_DDR_LAW         11
 448
 449 /* Set up IFC registers for boot location NOR/NAND */
 450 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 451 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 452 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 453 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 454 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 455 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 456 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 457 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 458 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 459 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 460 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 461 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 462 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 463 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 464 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 465 #else
 466 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 467 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 468 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 469 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 470 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 471 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 472 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 473 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 474 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 475 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 476 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 477 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 478 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 479 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 480 #endif
 481
 482 /* CPLD on IFC */
 483 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 484
 485 #ifdef CONFIG_PHYS_64BIT
 486 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 487 #else
 488 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 489 #endif
 490
 491 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 492                                 | CSPR_PORT_SIZE_8 \
 493                                 | CSPR_MSEL_GPCM \
 494                                 | CSPR_V)
 495 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 496 #define CONFIG_SYS_CSOR3                0x0
 497 /* CPLD Timing parameters for IFC CS3 */
 498 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 499                                         FTIM0_GPCM_TEADC(0x0e) | \
 500                                         FTIM0_GPCM_TEAHC(0x0e))
 501 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 502                                         FTIM1_GPCM_TRAD(0x1f))
 503 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 504                                         FTIM2_GPCM_TCH(0x8) | \
 505                                         FTIM2_GPCM_TWP(0x1f))
 506 #define CONFIG_SYS_CS3_FTIM3            0x0
 507
 508 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 509         defined(CONFIG_RAMBOOT_NAND)
 510 #define CONFIG_SYS_RAMBOOT
 511 #define CONFIG_SYS_EXTRA_ENV_RELOC
 512 #else
 513 #undef CONFIG_SYS_RAMBOOT
 514 #endif
 515
 516 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 517 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 518 #define CONFIG_A003399_NOR_WORKAROUND
 519 #endif
 520 #endif
 521
 522 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 523 #define CONFIG_BOARD_EARLY_INIT_R
 524
 525 #define CONFIG_SYS_INIT_RAM_LOCK
 526 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 527 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 528
 529 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 530                                                 - GENERATED_GBL_DATA_SIZE)
 531 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 532
 533 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 534 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 535
 536 /*
 537  * Config the L2 Cache as L2 SRAM
 538  */
 539 #if defined(CONFIG_SPL_BUILD)
 540 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 541 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 542 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 543 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 544 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 545 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 546 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 547 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
 548 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 549 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 550 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 551 #elif defined(CONFIG_NAND)
 552 #ifdef CONFIG_TPL_BUILD
 553 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 554 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 555 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 556 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 557 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 558 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 559 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 560 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 561 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 562 #else
 563 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 564 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 565 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 566 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 567 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 568 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 569 #endif
 570 #endif
 571 #endif
 572
 573 /* Serial Port */
 574 #define CONFIG_CONS_INDEX       1
 575 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 576 #define CONFIG_SYS_NS16550_SERIAL
 577 #define CONFIG_SYS_NS16550_REG_SIZE     1
 578 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 579 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 580 #define CONFIG_NS16550_MIN_FUNCTIONS
 581 #endif
 582
 583 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 584
 585 #define CONFIG_SYS_BAUDRATE_TABLE       \
 586         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 587
 588 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 589 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 590
 591 /* I2C */
 592 #define CONFIG_SYS_I2C
 593 #define CONFIG_SYS_I2C_FSL
 594 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 595 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 596 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 597 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 598 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 599 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 600 #define I2C_PCA9557_ADDR1               0x18
 601 #define I2C_PCA9557_ADDR2               0x19
 602 #define I2C_PCA9557_BUS_NUM             0
 603
 604 /* I2C EEPROM */
 605 #if defined(CONFIG_P1010RDB_PB)
 606 #define CONFIG_ID_EEPROM
 607 #ifdef CONFIG_ID_EEPROM
 608 #define CONFIG_SYS_I2C_EEPROM_NXID
 609 #endif
 610 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 611 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 612 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 613 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 614 #endif
 615 /* enable read and write access to EEPROM */
 616 #define CONFIG_CMD_EEPROM
 617 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 618 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 619 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 620
 621 /* RTC */
 622 #define CONFIG_RTC_PT7C4338
 623 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 624
 625 /*
 626  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 627  * used for SLIC
 628  */
 629 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 630 /* eSPI - Enhanced SPI */
 631 #define CONFIG_SF_DEFAULT_SPEED         10000000
 632 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 633 #endif
 634
 635 #if defined(CONFIG_TSEC_ENET)
 636 #define CONFIG_MII                      /* MII PHY management */
 637 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 638 #define CONFIG_TSEC1    1
 639 #define CONFIG_TSEC1_NAME       "eTSEC1"
 640 #define CONFIG_TSEC2    1
 641 #define CONFIG_TSEC2_NAME       "eTSEC2"
 642 #define CONFIG_TSEC3    1
 643 #define CONFIG_TSEC3_NAME       "eTSEC3"
 644
 645 #define TSEC1_PHY_ADDR          1
 646 #define TSEC2_PHY_ADDR          0
 647 #define TSEC3_PHY_ADDR          2
 648
 649 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 650 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 651 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 652
 653 #define TSEC1_PHYIDX            0
 654 #define TSEC2_PHYIDX            0
 655 #define TSEC3_PHYIDX            0
 656
 657 #define CONFIG_ETHPRIME         "eTSEC1"
 658
 659 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 660
 661 /* TBI PHY configuration for SGMII mode */
 662 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 663                 TBICR_PHY_RESET \
 664                 | TBICR_ANEG_ENABLE \
 665                 | TBICR_FULL_DUPLEX \
 666                 | TBICR_SPEED1_SET \
 667                 )
 668
 669 #endif  /* CONFIG_TSEC_ENET */
 670
 671 /* SATA */
 672 #define CONFIG_FSL_SATA
 673 #define CONFIG_FSL_SATA_V2
 674 #define CONFIG_LIBATA
 675
 676 #ifdef CONFIG_FSL_SATA
 677 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 678 #define CONFIG_SATA1
 679 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 680 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 681 #define CONFIG_SATA2
 682 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 683 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 684
 685 #define CONFIG_CMD_SATA
 686 #define CONFIG_LBA48
 687 #endif /* #ifdef CONFIG_FSL_SATA  */
 688
 689 #define CONFIG_MMC
 690 #ifdef CONFIG_MMC
 691 #define CONFIG_DOS_PARTITION
 692 #define CONFIG_FSL_ESDHC
 693 #define CONFIG_GENERIC_MMC
 694 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 695 #endif
 696
 697 #define CONFIG_HAS_FSL_DR_USB
 698
 699 #if defined(CONFIG_HAS_FSL_DR_USB)
 700 #define CONFIG_USB_EHCI
 701
 702 #ifdef CONFIG_USB_EHCI
 703 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 704 #define CONFIG_USB_EHCI_FSL
 705 #endif
 706 #endif
 707
 708 /*
 709  * Environment
 710  */
 711 #if defined(CONFIG_SDCARD)
 712 #define CONFIG_ENV_IS_IN_MMC
 713 #define CONFIG_FSL_FIXED_MMC_LOCATION
 714 #define CONFIG_SYS_MMC_ENV_DEV          0
 715 #define CONFIG_ENV_SIZE                 0x2000
 716 #elif defined(CONFIG_SPIFLASH)
 717 #define CONFIG_ENV_IS_IN_SPI_FLASH
 718 #define CONFIG_ENV_SPI_BUS      0
 719 #define CONFIG_ENV_SPI_CS       0
 720 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 721 #define CONFIG_ENV_SPI_MODE     0
 722 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 723 #define CONFIG_ENV_SECT_SIZE    0x10000
 724 #define CONFIG_ENV_SIZE         0x2000
 725 #elif defined(CONFIG_NAND)
 726 #define CONFIG_ENV_IS_IN_NAND
 727 #ifdef CONFIG_TPL_BUILD
 728 #define CONFIG_ENV_SIZE         0x2000
 729 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 730 #else
 731 #if defined(CONFIG_P1010RDB_PA)
 732 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 733 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 734 #elif defined(CONFIG_P1010RDB_PB)
 735 #define CONFIG_ENV_SIZE         (16 * 1024)
 736 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 737 #endif
 738 #endif
 739 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 740 #elif defined(CONFIG_SYS_RAMBOOT)
 741 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 742 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 743 #define CONFIG_ENV_SIZE                 0x2000
 744 #else
 745 #define CONFIG_ENV_IS_IN_FLASH
 746 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 747 #define CONFIG_ENV_SIZE         0x2000
 748 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 749 #endif
 750
 751 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 752 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 753
 754 /*
 755  * Command line configuration.
 756  */
 757 #define CONFIG_CMD_DATE
 758 #define CONFIG_CMD_ERRATA
 759 #define CONFIG_CMD_IRQ
 760 #define CONFIG_CMD_REGINFO
 761
 762 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 763
 764 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 765                  || defined(CONFIG_FSL_SATA)
 766 #define CONFIG_DOS_PARTITION
 767 #endif
 768
 769 /* Hash command with SHA acceleration supported in hardware */
 770 #ifdef CONFIG_FSL_CAAM
 771 #define CONFIG_CMD_HASH
 772 #define CONFIG_SHA_HW_ACCEL
 773 #endif
 774
 775 /*
 776  * Miscellaneous configurable options
 777  */
 778 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 779 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 780 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 781 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 782
 783 #if defined(CONFIG_CMD_KGDB)
 784 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 785 #else
 786 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 787 #endif
 788 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 789                                                 /* Print Buffer Size */
 790 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 791 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 792
 793 /*
 794  * For booting Linux, the board info and command line data
 795  * have to be in the first 64 MB of memory, since this is
 796  * the maximum mapped by the Linux kernel during initialization.
 797  */
 798 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 799 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 800
 801 #if defined(CONFIG_CMD_KGDB)
 802 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 803 #endif
 804
 805 /*
 806  * Environment Configuration
 807  */
 808
 809 #if defined(CONFIG_TSEC_ENET)
 810 #define CONFIG_HAS_ETH0
 811 #define CONFIG_HAS_ETH1
 812 #define CONFIG_HAS_ETH2
 813 #endif
 814
 815 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 816 #define CONFIG_BOOTFILE         "uImage"
 817 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 818
 819 /* default location for tftp and bootm */
 820 #define CONFIG_LOADADDR         1000000
 821
 822 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 823
 824 #define CONFIG_BAUDRATE         115200
 825
 826 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 827         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 828         "netdev=eth0\0"                                         \
 829         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 830         "loadaddr=1000000\0"                    \
 831         "consoledev=ttyS0\0"                            \
 832         "ramdiskaddr=2000000\0"                 \
 833         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 834         "fdtaddr=1e00000\0"                             \
 835         "fdtfile=p1010rdb.dtb\0"                \
 836         "bdev=sda1\0"   \
 837         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 838         "othbootargs=ramdisk_size=600000\0" \
 839         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 840         "console=$consoledev,$baudrate $othbootargs; "  \
 841         "usb start;"                    \
 842         "fatload usb 0:2 $loadaddr $bootfile;"          \
 843         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 844         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 845         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 846         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 847         "console=$consoledev,$baudrate $othbootargs; "  \
 848         "usb start;"                    \
 849         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 850         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 851         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 852         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 853         CONFIG_BOOTMODE
 854
 855 #if defined(CONFIG_P1010RDB_PA)
 856 #define CONFIG_BOOTMODE \
 857         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 858         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 859         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 860         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 861         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 862         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 863
 864 #elif defined(CONFIG_P1010RDB_PB)
 865 #define CONFIG_BOOTMODE \
 866         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 867         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 868         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 869         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 870         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 871         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 872         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 873         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 874         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 875         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 876 #endif
 877
 878 #define CONFIG_RAMBOOTCOMMAND           \
 879         "setenv bootargs root=/dev/ram rw "     \
 880         "console=$consoledev,$baudrate $othbootargs; "  \
 881         "tftp $ramdiskaddr $ramdiskfile;"       \
 882         "tftp $loadaddr $bootfile;"             \
 883         "tftp $fdtaddr $fdtfile;"               \
 884         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 885
 886 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 887
 888 #include <asm/fsl_secure_boot.h>
 889
 890 #endif  /* __CONFIG_H */