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git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/P1010RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <asm/config_mpc85xx.h>
15 #define CONFIG_NAND_FSL_IFC
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SPL_PAD_TO 0x18000
21 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
27 #ifdef CONFIG_SPL_BUILD
28 #define CONFIG_SPL_COMMON_INIT_DDR
32 #ifdef CONFIG_SPIFLASH
33 #ifdef CONFIG_NXP_ESBC
34 #define CONFIG_RAMBOOT_SPIFLASH
35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
37 #define CONFIG_SPL_SPI_FLASH_MINIMAL
38 #define CONFIG_SPL_FLUSH_IMAGE
39 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
40 #define CONFIG_SPL_PAD_TO 0x18000
41 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
47 #ifdef CONFIG_SPL_BUILD
48 #define CONFIG_SPL_COMMON_INIT_DDR
53 #ifdef CONFIG_MTD_RAW_NAND
54 #ifdef CONFIG_NXP_ESBC
55 #define CONFIG_SPL_INIT_MINIMAL
56 #define CONFIG_SPL_FLUSH_IMAGE
57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
59 #define CONFIG_SPL_MAX_SIZE 8192
60 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
61 #define CONFIG_SPL_RELOC_STACK 0x00100000
62 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
63 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
64 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
65 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
67 #ifdef CONFIG_TPL_BUILD
68 #define CONFIG_SPL_FLUSH_IMAGE
69 #define CONFIG_SPL_NAND_INIT
70 #define CONFIG_SPL_COMMON_INIT_DDR
71 #define CONFIG_SPL_MAX_SIZE (128 << 10)
72 #define CONFIG_TPL_TEXT_BASE 0xD0001000
73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
74 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
75 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
76 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
77 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
78 #elif defined(CONFIG_SPL_BUILD)
79 #define CONFIG_SPL_INIT_MINIMAL
80 #define CONFIG_SPL_NAND_MINIMAL
81 #define CONFIG_SPL_FLUSH_IMAGE
82 #define CONFIG_SPL_MAX_SIZE 8192
83 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
84 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
85 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
86 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
88 #define CONFIG_SPL_PAD_TO 0x20000
89 #define CONFIG_TPL_PAD_TO 0x20000
90 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
94 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
95 #define CONFIG_RAMBOOT_NAND
96 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
99 #ifndef CONFIG_RESET_VECTOR_ADDRESS
100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
103 #ifdef CONFIG_TPL_BUILD
104 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
105 #elif defined(CONFIG_SPL_BUILD)
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
111 /* High Level Configuration Options */
112 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
114 #if defined(CONFIG_PCI)
115 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
116 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
117 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
121 * Memory space is mapped 1-1, but I/O space must start from 0.
123 /* controller 1, Slot 1, tgtid 1, Base address a000 */
124 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
125 #ifdef CONFIG_PHYS_64BIT
126 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
128 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
130 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
131 #ifdef CONFIG_PHYS_64BIT
132 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
134 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
137 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
138 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
139 #ifdef CONFIG_PHYS_64BIT
140 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
142 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
144 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
145 #ifdef CONFIG_PHYS_64BIT
146 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
148 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
151 #if !defined(CONFIG_DM_PCI)
152 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
153 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
154 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
155 #ifdef CONFIG_PHYS_64BIT
156 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
158 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
160 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
161 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
162 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
164 #if defined(CONFIG_TARGET_P1010RDB_PA)
165 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
166 #elif defined(CONFIG_TARGET_P1010RDB_PB)
167 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
172 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
174 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
175 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
176 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
179 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
182 #define CONFIG_ENV_OVERWRITE
184 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
185 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
187 #define CONFIG_HWCONFIG
189 * These can be toggled for performance analysis, otherwise use default.
191 #define CONFIG_L2_CACHE /* toggle L2 cache */
192 #define CONFIG_BTB /* toggle branch predition */
195 #define CONFIG_ENABLE_36BIT_PHYS
197 #ifdef CONFIG_PHYS_64BIT
198 #define CONFIG_ADDR_MAP 1
199 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
203 #define CONFIG_SYS_DDR_RAW_TIMING
204 #define CONFIG_DDR_SPD
205 #define CONFIG_SYS_SPD_BUS_NUM 1
206 #define SPD_EEPROM_ADDRESS 0x52
208 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
211 extern unsigned long get_sdram_size(void);
213 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
214 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
215 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
217 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
218 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
220 /* DDR3 Controller Settings */
221 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
222 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
223 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
224 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
225 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
226 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
227 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
228 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
229 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
230 #define CONFIG_SYS_DDR_RCW_1 0x00000000
231 #define CONFIG_SYS_DDR_RCW_2 0x00000000
232 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
233 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
234 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
235 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
237 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
238 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
239 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
240 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
241 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
242 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
243 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
244 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
245 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
247 /* settings for DDR3 at 667MT/s */
248 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
249 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
250 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
251 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
252 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
253 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
254 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
255 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
256 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
258 #define CONFIG_SYS_CCSRBAR 0xffe00000
259 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
261 /* Don't relocate CCSRBAR while in NAND_SPL */
262 #ifdef CONFIG_SPL_BUILD
263 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
269 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
270 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
271 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
273 * Localbus non-cacheable
274 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
275 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
276 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
277 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
283 /* NOR Flash on IFC */
285 #define CONFIG_SYS_FLASH_BASE 0xee000000
286 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
288 #ifdef CONFIG_PHYS_64BIT
289 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
291 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
294 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
295 CSPR_PORT_SIZE_16 | \
298 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
299 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
300 /* NOR Flash Timing Params */
301 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
302 FTIM0_NOR_TEADC(0x5) | \
304 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
305 FTIM1_NOR_TRAD_NOR(0x0f)
306 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
307 FTIM2_NOR_TCH(0x4) | \
309 #define CONFIG_SYS_NOR_FTIM3 0x0
311 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
312 #define CONFIG_SYS_FLASH_QUIET_TEST
313 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
314 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
316 #undef CONFIG_SYS_FLASH_CHECKSUM
317 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
318 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
320 /* CFI for NOR Flash */
321 #define CONFIG_SYS_FLASH_EMPTY_INFO
323 /* NAND Flash on IFC */
324 #define CONFIG_SYS_NAND_BASE 0xff800000
325 #ifdef CONFIG_PHYS_64BIT
326 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
328 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
331 #define CONFIG_MTD_PARTITION
333 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
337 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
339 #if defined(CONFIG_TARGET_P1010RDB_PA)
340 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
341 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
342 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
343 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
344 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
345 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
346 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
347 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
349 #elif defined(CONFIG_TARGET_P1010RDB_PB)
350 #define CONFIG_SYS_NAND_ONFI_DETECTION
351 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
352 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
353 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
354 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
355 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
356 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
357 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
358 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
361 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
362 #define CONFIG_SYS_MAX_NAND_DEVICE 1
364 #if defined(CONFIG_TARGET_P1010RDB_PA)
365 /* NAND Flash Timing Params */
366 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
367 FTIM0_NAND_TWP(0x0C) | \
368 FTIM0_NAND_TWCHT(0x04) | \
370 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
371 FTIM1_NAND_TWBE(0x1d) | \
372 FTIM1_NAND_TRR(0x07) | \
374 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
375 FTIM2_NAND_TREH(0x05) | \
376 FTIM2_NAND_TWHRE(0x0f)
377 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
379 #elif defined(CONFIG_TARGET_P1010RDB_PB)
380 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
381 /* ONFI NAND Flash mode0 Timing Params */
382 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
383 FTIM0_NAND_TWP(0x18) | \
384 FTIM0_NAND_TWCHT(0x07) | \
385 FTIM0_NAND_TWH(0x0a))
386 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
387 FTIM1_NAND_TWBE(0x39) | \
388 FTIM1_NAND_TRR(0x0e) | \
389 FTIM1_NAND_TRP(0x18))
390 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
391 FTIM2_NAND_TREH(0x0a) | \
392 FTIM2_NAND_TWHRE(0x1e))
393 #define CONFIG_SYS_NAND_FTIM3 0x0
396 #define CONFIG_SYS_NAND_DDR_LAW 11
398 /* Set up IFC registers for boot location NOR/NAND */
399 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
407 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
408 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
409 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
410 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
411 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
412 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
413 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
415 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
416 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
417 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
418 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
419 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
420 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
421 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
432 #define CONFIG_SYS_CPLD_BASE 0xffb00000
434 #ifdef CONFIG_PHYS_64BIT
435 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
437 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
440 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
444 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
445 #define CONFIG_SYS_CSOR3 0x0
446 /* CPLD Timing parameters for IFC CS3 */
447 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
448 FTIM0_GPCM_TEADC(0x0e) | \
449 FTIM0_GPCM_TEAHC(0x0e))
450 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
451 FTIM1_GPCM_TRAD(0x1f))
452 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
453 FTIM2_GPCM_TCH(0x8) | \
454 FTIM2_GPCM_TWP(0x1f))
455 #define CONFIG_SYS_CS3_FTIM3 0x0
457 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
458 defined(CONFIG_RAMBOOT_NAND)
459 #define CONFIG_SYS_RAMBOOT
461 #undef CONFIG_SYS_RAMBOOT
464 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
465 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
466 #define CONFIG_A003399_NOR_WORKAROUND
470 #define CONFIG_SYS_INIT_RAM_LOCK
471 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
472 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
474 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
475 - GENERATED_GBL_DATA_SIZE)
476 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
478 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
479 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
482 * Config the L2 Cache as L2 SRAM
484 #if defined(CONFIG_SPL_BUILD)
485 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
486 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
487 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
488 #define CONFIG_SYS_L2_SIZE (256 << 10)
489 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
490 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
491 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
492 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
493 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
494 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
495 #elif defined(CONFIG_MTD_RAW_NAND)
496 #ifdef CONFIG_TPL_BUILD
497 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
498 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
499 #define CONFIG_SYS_L2_SIZE (256 << 10)
500 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
501 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
502 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
503 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
504 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
505 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
507 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
508 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
509 #define CONFIG_SYS_L2_SIZE (256 << 10)
510 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
511 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
512 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
518 #undef CONFIG_SERIAL_SOFTWARE_FIFO
519 #define CONFIG_SYS_NS16550_SERIAL
520 #define CONFIG_SYS_NS16550_REG_SIZE 1
521 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
522 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
523 #define CONFIG_NS16550_MIN_FUNCTIONS
526 #define CONFIG_SYS_BAUDRATE_TABLE \
527 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
529 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
530 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
533 #ifndef CONFIG_DM_I2C
534 #define CONFIG_SYS_I2C
535 #define CONFIG_SYS_FSL_I2C_SPEED 400000
536 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
537 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
538 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
539 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
540 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
542 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
543 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
545 #define I2C_PCA9557_ADDR1 0x18
546 #define I2C_PCA9557_ADDR2 0x19
547 #define I2C_PCA9557_BUS_NUM 0
548 #define CONFIG_SYS_I2C_FSL
551 #if defined(CONFIG_TARGET_P1010RDB_PB)
552 #define CONFIG_ID_EEPROM
553 #ifdef CONFIG_ID_EEPROM
554 #define CONFIG_SYS_I2C_EEPROM_NXID
556 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
557 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
558 #define CONFIG_SYS_EEPROM_BUS_NUM 0
559 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
561 /* enable read and write access to EEPROM */
562 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
563 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
564 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
567 #define CONFIG_RTC_PT7C4338
568 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
571 * SPI interface will not be available in case of NAND boot SPI CS0 will be
574 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
575 /* eSPI - Enhanced SPI */
578 #if defined(CONFIG_TSEC_ENET)
579 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
580 #define CONFIG_TSEC1 1
581 #define CONFIG_TSEC1_NAME "eTSEC1"
582 #define CONFIG_TSEC2 1
583 #define CONFIG_TSEC2_NAME "eTSEC2"
584 #define CONFIG_TSEC3 1
585 #define CONFIG_TSEC3_NAME "eTSEC3"
587 #define TSEC1_PHY_ADDR 1
588 #define TSEC2_PHY_ADDR 0
589 #define TSEC3_PHY_ADDR 2
591 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
592 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
593 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
595 #define TSEC1_PHYIDX 0
596 #define TSEC2_PHYIDX 0
597 #define TSEC3_PHYIDX 0
599 #define CONFIG_ETHPRIME "eTSEC1"
601 /* TBI PHY configuration for SGMII mode */
602 #define CONFIG_TSEC_TBICR_SETTINGS ( \
604 | TBICR_ANEG_ENABLE \
605 | TBICR_FULL_DUPLEX \
609 #endif /* CONFIG_TSEC_ENET */
612 #define CONFIG_FSL_SATA_V2
614 #ifdef CONFIG_FSL_SATA
615 #define CONFIG_SYS_SATA_MAX_DEVICE 2
617 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
618 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
620 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
621 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
624 #endif /* #ifdef CONFIG_FSL_SATA */
627 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
630 #define CONFIG_HAS_FSL_DR_USB
632 #if defined(CONFIG_HAS_FSL_DR_USB)
633 #ifdef CONFIG_USB_EHCI_HCD
634 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
635 #define CONFIG_USB_EHCI_FSL
642 #if defined(CONFIG_SDCARD)
643 #define CONFIG_FSL_FIXED_MMC_LOCATION
644 #define CONFIG_SYS_MMC_ENV_DEV 0
645 #elif defined(CONFIG_MTD_RAW_NAND)
646 #ifdef CONFIG_TPL_BUILD
647 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
649 #if defined(CONFIG_TARGET_P1010RDB_PA)
650 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
651 #elif defined(CONFIG_TARGET_P1010RDB_PB)
652 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
657 #define CONFIG_LOADS_ECHO /* echo on for serial download */
658 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
660 #undef CONFIG_WATCHDOG /* watchdog disabled */
662 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
663 || defined(CONFIG_FSL_SATA)
667 * Miscellaneous configurable options
669 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
672 * For booting Linux, the board info and command line data
673 * have to be in the first 64 MB of memory, since this is
674 * the maximum mapped by the Linux kernel during initialization.
676 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
677 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
679 #if defined(CONFIG_CMD_KGDB)
680 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
684 * Environment Configuration
687 #if defined(CONFIG_TSEC_ENET)
688 #define CONFIG_HAS_ETH0
689 #define CONFIG_HAS_ETH1
690 #define CONFIG_HAS_ETH2
693 #define CONFIG_ROOTPATH "/opt/nfsroot"
694 #define CONFIG_BOOTFILE "uImage"
695 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
697 /* default location for tftp and bootm */
698 #define CONFIG_LOADADDR 1000000
700 #define CONFIG_EXTRA_ENV_SETTINGS \
701 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
703 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
704 "loadaddr=1000000\0" \
705 "consoledev=ttyS0\0" \
706 "ramdiskaddr=2000000\0" \
707 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
708 "fdtaddr=1e00000\0" \
709 "fdtfile=p1010rdb.dtb\0" \
711 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
712 "othbootargs=ramdisk_size=600000\0" \
713 "usbfatboot=setenv bootargs root=/dev/ram rw " \
714 "console=$consoledev,$baudrate $othbootargs; " \
716 "fatload usb 0:2 $loadaddr $bootfile;" \
717 "fatload usb 0:2 $fdtaddr $fdtfile;" \
718 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
719 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
720 "usbext2boot=setenv bootargs root=/dev/ram rw " \
721 "console=$consoledev,$baudrate $othbootargs; " \
723 "ext2load usb 0:4 $loadaddr $bootfile;" \
724 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
725 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
726 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
729 #if defined(CONFIG_TARGET_P1010RDB_PA)
730 #define CONFIG_BOOTMODE \
731 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
732 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
733 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
734 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
735 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
736 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
738 #elif defined(CONFIG_TARGET_P1010RDB_PB)
739 #define CONFIG_BOOTMODE \
740 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
741 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
742 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
743 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
744 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
745 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
746 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
747 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
748 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
749 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
752 #define CONFIG_RAMBOOTCOMMAND \
753 "setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs; " \
755 "tftp $ramdiskaddr $ramdiskfile;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr $ramdiskaddr $fdtaddr"
760 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
762 #include <asm/fsl_secure_boot.h>
764 #endif /* __CONFIG_H */