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git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/P1022DS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
11 #include <linux/stringify.h>
13 #include "../board/freescale/common/ics307_clk.h"
16 #define CONFIG_SPL_FLUSH_IMAGE
17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
18 #define CONFIG_SPL_PAD_TO 0x20000
19 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
20 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
21 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
23 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
25 #ifdef CONFIG_SPL_BUILD
26 #define CONFIG_SPL_COMMON_INIT_DDR
30 #ifdef CONFIG_SPIFLASH
31 #define CONFIG_SPL_SPI_FLASH_MINIMAL
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_PAD_TO 0x20000
35 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SPL_COMMON_INIT_DDR
46 #define CONFIG_NAND_FSL_ELBC
47 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
48 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
50 #ifdef CONFIG_MTD_RAW_NAND
51 #ifdef CONFIG_TPL_BUILD
52 #define CONFIG_SPL_FLUSH_IMAGE
53 #define CONFIG_SPL_NAND_INIT
54 #define CONFIG_SPL_COMMON_INIT_DDR
55 #define CONFIG_SPL_MAX_SIZE (128 << 10)
56 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
59 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
60 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
61 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
62 #elif defined(CONFIG_SPL_BUILD)
63 #define CONFIG_SPL_INIT_MINIMAL
64 #define CONFIG_SPL_FLUSH_IMAGE
65 #define CONFIG_SPL_MAX_SIZE 4096
66 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
67 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
68 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
69 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
71 #define CONFIG_SPL_PAD_TO 0x20000
72 #define CONFIG_TPL_PAD_TO 0x20000
73 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
76 /* High Level Configuration Options */
78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
82 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
83 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
84 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
85 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
86 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
88 #define CONFIG_ENABLE_36BIT_PHYS
90 #ifdef CONFIG_PHYS_64BIT
91 #define CONFIG_ADDR_MAP
92 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
95 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
96 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
97 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
100 * These can be toggled for performance analysis, otherwise use default.
102 #define CONFIG_L2_CACHE
105 #define CONFIG_SYS_CCSRBAR 0xffe00000
106 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
108 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
110 #ifdef CONFIG_SPL_BUILD
111 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
115 #define CONFIG_DDR_SPD
116 #define CONFIG_VERY_BIG_RAM
118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
127 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
129 /* I2C addresses of SPD EEPROMs */
130 #define CONFIG_SYS_SPD_BUS_NUM 1
131 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
133 /* These are used when DDR doesn't use SPD. */
134 #define CONFIG_SYS_SDRAM_SIZE 2048
135 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
136 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
137 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
138 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
139 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
140 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
141 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
142 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
143 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
144 #define CONFIG_SYS_DDR_MODE_1 0x00441221
145 #define CONFIG_SYS_DDR_MODE_2 0x00000000
146 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
147 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
148 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
149 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
150 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
151 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
152 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
153 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
154 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
159 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
160 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
161 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
163 * Localbus cacheable (TBD)
164 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
166 * Localbus non-cacheable
167 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
168 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
169 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
170 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
171 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
172 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
176 * Local Bus Definitions
178 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
179 #ifdef CONFIG_PHYS_64BIT
180 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
182 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
185 #define CONFIG_FLASH_BR_PRELIM \
186 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
187 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
189 #ifdef CONFIG_MTD_RAW_NAND
190 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
191 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
193 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
194 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
197 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
198 #define CONFIG_SYS_FLASH_QUIET_TEST
199 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
201 #define CONFIG_SYS_MAX_FLASH_BANKS 1
202 #define CONFIG_SYS_MAX_FLASH_SECT 1024
204 #ifndef CONFIG_SYS_MONITOR_BASE
205 #ifdef CONFIG_TPL_BUILD
206 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
207 #elif defined(CONFIG_SPL_BUILD)
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
214 #define CONFIG_SYS_FLASH_EMPTY_INFO
217 #if defined(CONFIG_NAND_FSL_ELBC)
218 #define CONFIG_SYS_NAND_BASE 0xff800000
219 #ifdef CONFIG_PHYS_64BIT
220 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
222 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
225 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
226 #define CONFIG_SYS_MAX_NAND_DEVICE 1
227 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
228 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
230 /* NAND flash config */
231 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
232 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
233 | BR_PS_8 /* Port Size = 8 bit */ \
234 | BR_MS_FCM /* MSEL = FCM */ \
236 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
237 | OR_FCM_PGS /* Large Page*/ \
244 #ifdef CONFIG_MTD_RAW_NAND
245 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
246 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
248 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
249 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
252 #endif /* CONFIG_NAND_FSL_ELBC */
254 #define CONFIG_HWCONFIG
256 #define CONFIG_FSL_NGPIXIS
257 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
258 #ifdef CONFIG_PHYS_64BIT
259 #define PIXIS_BASE_PHYS 0xfffdf0000ull
261 #define PIXIS_BASE_PHYS PIXIS_BASE
264 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
265 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
267 #define PIXIS_LBMAP_SWITCH 7
268 #define PIXIS_LBMAP_MASK 0xF0
269 #define PIXIS_LBMAP_ALTBANK 0x20
270 #define PIXIS_SPD 0x07
271 #define PIXIS_SPD_SYSCLK_MASK 0x07
272 #define PIXIS_ELBC_SPI_MASK 0xc0
273 #define PIXIS_SPI 0x80
275 #define CONFIG_SYS_INIT_RAM_LOCK
276 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
277 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
279 #define CONFIG_SYS_GBL_DATA_OFFSET \
280 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
283 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
284 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
287 * Config the L2 Cache as L2 SRAM
289 #if defined(CONFIG_SPL_BUILD)
290 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
291 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
292 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
293 #define CONFIG_SYS_L2_SIZE (256 << 10)
294 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
295 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
296 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
297 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
298 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
299 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
300 #elif defined(CONFIG_MTD_RAW_NAND)
301 #ifdef CONFIG_TPL_BUILD
302 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
303 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
304 #define CONFIG_SYS_L2_SIZE (256 << 10)
305 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
306 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
307 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
308 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
309 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
310 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
312 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
313 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
314 #define CONFIG_SYS_L2_SIZE (256 << 10)
315 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
316 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
317 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
325 #define CONFIG_SYS_NS16550_SERIAL
326 #define CONFIG_SYS_NS16550_REG_SIZE 1
327 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
328 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
329 #define CONFIG_NS16550_MIN_FUNCTIONS
332 #define CONFIG_SYS_BAUDRATE_TABLE \
333 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
340 #ifdef CONFIG_FSL_DIU_FB
341 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
342 #define CONFIG_VIDEO_LOGO
343 #define CONFIG_VIDEO_BMP_LOGO
344 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
346 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
347 * disable empty flash sector detection, which is I/O-intensive.
349 #undef CONFIG_SYS_FLASH_EMPTY_INFO
353 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
354 #define CONFIG_BIOSEMU
355 #define CONFIG_ATI_RADEON_FB
356 #define CONFIG_VIDEO_LOGO
357 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
361 #ifndef CONFIG_DM_I2C
362 #define CONFIG_SYS_I2C
363 #define CONFIG_SYS_FSL_I2C_SPEED 400000
364 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
365 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
366 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
367 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
368 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
369 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
371 #define CONFIG_SYS_I2C_FSL
376 #define CONFIG_ID_EEPROM
377 #define CONFIG_SYS_I2C_EEPROM_NXID
378 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
379 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
380 #define CONFIG_SYS_EEPROM_BUS_NUM 1
384 * Memory space is mapped 1-1, but I/O space must start from 0.
387 /* controller 1, Slot 2, tgtid 1, Base address a000 */
388 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
389 #ifdef CONFIG_PHYS_64BIT
390 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
391 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
393 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
394 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
396 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
397 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
398 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
399 #ifdef CONFIG_PHYS_64BIT
400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
402 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
404 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
406 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
407 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
410 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
415 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
416 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
417 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
421 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
423 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
425 /* controller 3, Slot 1, tgtid 3, Base address b000 */
426 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
429 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
431 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
432 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
434 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
440 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
442 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
445 #define CONFIG_PCI_INDIRECT_BRIDGE
446 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
450 #define CONFIG_FSL_SATA_V2
452 #define CONFIG_SYS_SATA_MAX_DEVICE 2
454 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
455 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
457 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
458 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
460 #ifdef CONFIG_FSL_SATA
465 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
468 #ifdef CONFIG_TSEC_ENET
470 #define CONFIG_TSECV2
472 #define CONFIG_TSEC1 1
473 #define CONFIG_TSEC1_NAME "eTSEC1"
474 #define CONFIG_TSEC2 1
475 #define CONFIG_TSEC2_NAME "eTSEC2"
477 #define TSEC1_PHY_ADDR 1
478 #define TSEC2_PHY_ADDR 2
480 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
481 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
483 #define TSEC1_PHYIDX 0
484 #define TSEC2_PHYIDX 0
486 #define CONFIG_ETHPRIME "eTSEC1"
490 * Dynamic MTD Partition support with mtdparts
496 #if defined(CONFIG_SDCARD)
497 #define CONFIG_FSL_FIXED_MMC_LOCATION
498 #define CONFIG_SYS_MMC_ENV_DEV 0
499 #elif defined(CONFIG_MTD_RAW_NAND)
500 #ifdef CONFIG_TPL_BUILD
501 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
503 #elif defined(CONFIG_SYS_RAMBOOT)
504 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
507 #define CONFIG_LOADS_ECHO
508 #define CONFIG_SYS_LOADS_BAUD_CHANGE
513 #define CONFIG_HAS_FSL_DR_USB
514 #ifdef CONFIG_HAS_FSL_DR_USB
515 #ifdef CONFIG_USB_EHCI_HCD
516 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
517 #define CONFIG_USB_EHCI_FSL
522 * Miscellaneous configurable options
524 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
527 * For booting Linux, the board info and command line data
528 * have to be in the first 64 MB of memory, since this is
529 * the maximum mapped by the Linux kernel during initialization.
531 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
532 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
534 #ifdef CONFIG_CMD_KGDB
535 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
539 * Environment Configuration
542 #define CONFIG_HOSTNAME "p1022ds"
543 #define CONFIG_ROOTPATH "/opt/nfsroot"
544 #define CONFIG_BOOTFILE "uImage"
545 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
547 #define CONFIG_LOADADDR 1000000
549 #define CONFIG_EXTRA_ENV_SETTINGS \
551 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
552 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
553 "tftpflash=tftpboot $loadaddr $uboot && " \
554 "protect off $ubootaddr +$filesize && " \
555 "erase $ubootaddr +$filesize && " \
556 "cp.b $loadaddr $ubootaddr $filesize && " \
557 "protect on $ubootaddr +$filesize && " \
558 "cmp.b $loadaddr $ubootaddr $filesize\0" \
559 "consoledev=ttyS0\0" \
560 "ramdiskaddr=2000000\0" \
561 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
562 "fdtaddr=1e00000\0" \
563 "fdtfile=p1022ds.dtb\0" \
565 "hwconfig=esdhc;audclk:12\0"
567 #define CONFIG_HDBOOT \
568 "setenv bootargs root=/dev/$bdev rw " \
569 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
570 "tftp $loadaddr $bootfile;" \
571 "tftp $fdtaddr $fdtfile;" \
572 "bootm $loadaddr - $fdtaddr"
574 #define CONFIG_NFSBOOTCOMMAND \
575 "setenv bootargs root=/dev/nfs rw " \
576 "nfsroot=$serverip:$rootpath " \
577 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
578 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
579 "tftp $loadaddr $bootfile;" \
580 "tftp $fdtaddr $fdtfile;" \
581 "bootm $loadaddr - $fdtaddr"
583 #define CONFIG_RAMBOOTCOMMAND \
584 "setenv bootargs root=/dev/ram rw " \
585 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
586 "tftp $ramdiskaddr $ramdiskfile;" \
587 "tftp $loadaddr $bootfile;" \
588 "tftp $fdtaddr $fdtfile;" \
589 "bootm $loadaddr $ramdiskaddr $fdtaddr"
591 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND