include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #ifdef CONFIG_36BIT
  15 #define CONFIG_PHYS_64BIT
  16 #endif
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_RAMBOOT_SDCARD
  20 #define CONFIG_SYS_RAMBOOT
  21 #define CONFIG_SYS_EXTRA_ENV_RELOC
  22 #define CONFIG_SYS_TEXT_BASE            0x11000000
  23 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  24 #endif
  25
  26 #ifdef CONFIG_SPIFLASH
  27 #define CONFIG_RAMBOOT_SPIFLASH
  28 #define CONFIG_SYS_RAMBOOT
  29 #define CONFIG_SYS_EXTRA_ENV_RELOC
  30 #define CONFIG_SYS_TEXT_BASE            0x11000000
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  32 #endif
  33
  34 #define CONFIG_NAND_FSL_ELBC
  35
  36 #ifdef CONFIG_NAND
  37 #define CONFIG_SPL
  38 #define CONFIG_SPL_INIT_MINIMAL
  39 #define CONFIG_SPL_SERIAL_SUPPORT
  40 #define CONFIG_SPL_NAND_SUPPORT
  41 #define CONFIG_SPL_NAND_MINIMAL
  42 #define CONFIG_SPL_FLUSH_IMAGE
  43 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
  44
  45 #define CONFIG_SYS_TEXT_BASE           0x00201000
  46 #define CONFIG_SPL_TEXT_BASE           0xfffff000
  47 #define CONFIG_SPL_MAX_SIZE            4096
  48 #define CONFIG_SPL_RELOC_TEXT_BASE     0x00100000
  49 #define CONFIG_SPL_RELOC_STACK         0x00100000
  50 #define CONFIG_SYS_NAND_U_BOOT_SIZE    ((512 << 10) + CONFIG_SPL_MAX_SIZE)
  51 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x00200000 - CONFIG_SPL_MAX_SIZE)
  52 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
  53 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0
  54 #define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  55 #endif
  56
  57 /* High Level Configuration Options */
  58 #define CONFIG_BOOKE                    /* BOOKE */
  59 #define CONFIG_E500                     /* BOOKE e500 family */
  60 #define CONFIG_MPC85xx                  /* MPC8540/60/55/41/48 */
  61 #define CONFIG_P1022
  62 #define CONFIG_P1022DS
  63 #define CONFIG_MP                       /* support multiple processors */
  64
  65 #ifndef CONFIG_SYS_TEXT_BASE
  66 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  67 #endif
  68
  69 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  70 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  71 #endif
  72
  73 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  74 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  75 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
  76 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
  77 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
  78 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  79 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  80 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  81
  82 #define CONFIG_ENABLE_36BIT_PHYS
  83
  84 #ifdef CONFIG_PHYS_64BIT
  85 #define CONFIG_ADDR_MAP
  86 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  87 #endif
  88
  89 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  90
  91 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  92 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  93 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  94
  95 /*
  96  * These can be toggled for performance analysis, otherwise use default.
  97  */
  98 #define CONFIG_L2_CACHE
  99 #define CONFIG_BTB
 100
 101 #define CONFIG_SYS_MEMTEST_START        0x00000000
 102 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 103
 104 #define CONFIG_SYS_CCSRBAR              0xffe00000
 105 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 106
 107 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 108        SPL code*/
 109 #ifdef CONFIG_SPL_BUILD
 110 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 111 #endif
 112
 113
 114 /* DDR Setup */
 115 #define CONFIG_DDR_SPD
 116 #define CONFIG_VERY_BIG_RAM
 117 #define CONFIG_FSL_DDR3
 118
 119 #ifdef CONFIG_DDR_ECC
 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 121 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 122 #endif
 123
 124 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 126
 127 #define CONFIG_NUM_DDR_CONTROLLERS      1
 128 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 129 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 130
 131 /* I2C addresses of SPD EEPROMs */
 132 #define CONFIG_SYS_SPD_BUS_NUM          1
 133 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 134
 135 /* These are used when DDR doesn't use SPD.  */
 136 #define CONFIG_SYS_SDRAM_SIZE           2048
 137 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 138 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 139 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 140 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 141 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 142 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 143 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 144 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 145 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 146 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 147 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 148 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 149 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 150 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 151 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 152 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 153 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 154 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 155 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 156 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 157
 158
 159 /*
 160  * Memory map
 161  *
 162  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 163  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 164  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 165  *
 166  * Localbus cacheable (TBD)
 167  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 168  *
 169  * Localbus non-cacheable
 170  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 171  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 172  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 173  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 174  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 175  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 176  */
 177
 178 /*
 179  * Local Bus Definitions
 180  */
 181 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 184 #else
 185 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 186 #endif
 187
 188 #define CONFIG_FLASH_BR_PRELIM  \
 189         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 190 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 191
 192 #ifdef CONFIG_NAND
 193 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 194 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 195 #else
 196 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 197 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 198 #endif
 199
 200 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 201 #define CONFIG_SYS_FLASH_QUIET_TEST
 202 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 203
 204 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 205 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 206
 207 #ifndef CONFIG_SYS_MONITOR_BASE
 208 #ifdef CONFIG_SPL_BUILD
 209 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 210 #else
 211 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 212 #endif
 213 #endif
 214
 215 #define CONFIG_FLASH_CFI_DRIVER
 216 #define CONFIG_SYS_FLASH_CFI
 217 #define CONFIG_SYS_FLASH_EMPTY_INFO
 218
 219 /* Nand Flash */
 220 #if defined(CONFIG_NAND_FSL_ELBC)
 221 #define CONFIG_SYS_NAND_BASE            0xff800000
 222 #ifdef CONFIG_PHYS_64BIT
 223 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 224 #else
 225 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 226 #endif
 227
 228 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE, }
 229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 230 #define CONFIG_MTD_NAND_VERIFY_WRITE
 231 #define CONFIG_CMD_NAND                 1
 232 #define CONFIG_SYS_NAND_BLOCK_SIZE    (256 * 1024)
 233 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 234
 235 /* NAND flash config */
 236 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 237                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 238                                | BR_PS_8               /* Port Size = 8 bit */ \
 239                                | BR_MS_FCM             /* MSEL = FCM */ \
 240                                | BR_V)                 /* valid */
 241 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 242                                | OR_FCM_PGS            /* Large Page*/ \
 243                                | OR_FCM_CSCT \
 244                                | OR_FCM_CST \
 245                                | OR_FCM_CHT \
 246                                | OR_FCM_SCY_1 \
 247                                | OR_FCM_TRLX \
 248                                | OR_FCM_EHTR)
 249 #ifdef CONFIG_NAND
 250 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 251 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 252 #else
 253 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 254 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 255 #endif
 256
 257 #endif /* CONFIG_NAND_FSL_ELBC */
 258
 259 #define CONFIG_BOARD_EARLY_INIT_F
 260 #define CONFIG_BOARD_EARLY_INIT_R
 261 #define CONFIG_MISC_INIT_R
 262 #define CONFIG_HWCONFIG
 263
 264 #define CONFIG_FSL_NGPIXIS
 265 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 266 #ifdef CONFIG_PHYS_64BIT
 267 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 268 #else
 269 #define PIXIS_BASE_PHYS         PIXIS_BASE
 270 #endif
 271
 272 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 273 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 274
 275 #define PIXIS_LBMAP_SWITCH      7
 276 #define PIXIS_LBMAP_MASK        0xF0
 277 #define PIXIS_LBMAP_ALTBANK     0x20
 278 #define PIXIS_SPD               0x07
 279 #define PIXIS_SPD_SYSCLK_MASK   0x07
 280 #define PIXIS_ELBC_SPI_MASK     0xc0
 281 #define PIXIS_SPI               0x80
 282
 283 #define CONFIG_SYS_INIT_RAM_LOCK
 284 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 285 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 286
 287 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 288         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 289 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 290
 291 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 292 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 293
 294 /*
 295  * Serial Port
 296  */
 297 #define CONFIG_CONS_INDEX               1
 298 #define CONFIG_SYS_NS16550
 299 #define CONFIG_SYS_NS16550_SERIAL
 300 #define CONFIG_SYS_NS16550_REG_SIZE     1
 301 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 302 #ifdef CONFIG_SPL_BUILD
 303 #define CONFIG_NS16550_MIN_FUNCTIONS
 304 #endif
 305
 306 #define CONFIG_SYS_BAUDRATE_TABLE       \
 307         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 308
 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 311
 312 /* Use the HUSH parser */
 313 #define CONFIG_SYS_HUSH_PARSER
 314
 315 /* Video */
 316
 317 #ifdef CONFIG_FSL_DIU_FB
 318 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 319 #define CONFIG_VIDEO
 320 #define CONFIG_CMD_BMP
 321 #define CONFIG_CFB_CONSOLE
 322 #define CONFIG_VIDEO_SW_CURSOR
 323 #define CONFIG_VGA_AS_SINGLE_DEVICE
 324 #define CONFIG_VIDEO_LOGO
 325 #define CONFIG_VIDEO_BMP_LOGO
 326 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 327 /*
 328  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 329  * disable empty flash sector detection, which is I/O-intensive.
 330  */
 331 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 332 #endif
 333
 334 #ifndef CONFIG_FSL_DIU_FB
 335 #endif
 336
 337 #ifdef CONFIG_ATI
 338 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 339 #define CONFIG_VIDEO
 340 #define CONFIG_BIOSEMU
 341 #define CONFIG_VIDEO_SW_CURSOR
 342 #define CONFIG_ATI_RADEON_FB
 343 #define CONFIG_VIDEO_LOGO
 344 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 345 #define CONFIG_CFB_CONSOLE
 346 #define CONFIG_VGA_AS_SINGLE_DEVICE
 347 #endif
 348
 349 /*
 350  * Pass open firmware flat tree
 351  */
 352 #define CONFIG_OF_LIBFDT
 353 #define CONFIG_OF_BOARD_SETUP
 354 #define CONFIG_OF_STDOUT_VIA_ALIAS
 355
 356 /* new uImage format support */
 357 #define CONFIG_FIT
 358 #define CONFIG_FIT_VERBOSE
 359
 360 /* I2C */
 361 #define CONFIG_SYS_I2C
 362 #define CONFIG_SYS_I2C_FSL
 363 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 364 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 365 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 366 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 367 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 368 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 369 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 370
 371 /*
 372  * I2C2 EEPROM
 373  */
 374 #define CONFIG_ID_EEPROM
 375 #define CONFIG_SYS_I2C_EEPROM_NXID
 376 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 377 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 378 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 379
 380 /*
 381  * eSPI - Enhanced SPI
 382  */
 383 #define CONFIG_SPI_FLASH
 384 #define CONFIG_SPI_FLASH_SPANSION
 385
 386 #define CONFIG_HARD_SPI
 387 #define CONFIG_FSL_ESPI
 388
 389 #define CONFIG_CMD_SF
 390 #define CONFIG_SF_DEFAULT_SPEED         10000000
 391 #define CONFIG_SF_DEFAULT_MODE          0
 392
 393 /*
 394  * General PCI
 395  * Memory space is mapped 1-1, but I/O space must start from 0.
 396  */
 397
 398 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 399 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 400 #ifdef CONFIG_PHYS_64BIT
 401 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 402 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 403 #else
 404 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 405 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 406 #endif
 407 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 408 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 409 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 410 #ifdef CONFIG_PHYS_64BIT
 411 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 412 #else
 413 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 414 #endif
 415 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 416
 417 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 418 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 419 #ifdef CONFIG_PHYS_64BIT
 420 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 421 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 422 #else
 423 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 424 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 425 #endif
 426 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 427 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 428 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 429 #ifdef CONFIG_PHYS_64BIT
 430 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 431 #else
 432 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 433 #endif
 434 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 435
 436 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 437 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 438 #ifdef CONFIG_PHYS_64BIT
 439 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 440 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 441 #else
 442 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 443 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 444 #endif
 445 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 446 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 447 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 448 #ifdef CONFIG_PHYS_64BIT
 449 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 450 #else
 451 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 452 #endif
 453 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 454
 455 #ifdef CONFIG_PCI
 456 #define CONFIG_PCI_INDIRECT_BRIDGE
 457 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 458 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 459 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
 460 #endif
 461
 462 /* SATA */
 463 #define CONFIG_LIBATA
 464 #define CONFIG_FSL_SATA
 465 #define CONFIG_FSL_SATA_V2
 466
 467 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 468 #define CONFIG_SATA1
 469 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 470 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 471 #define CONFIG_SATA2
 472 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 473 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 474
 475 #ifdef CONFIG_FSL_SATA
 476 #define CONFIG_LBA48
 477 #define CONFIG_CMD_SATA
 478 #define CONFIG_DOS_PARTITION
 479 #define CONFIG_CMD_EXT2
 480 #endif
 481
 482 #define CONFIG_MMC
 483 #ifdef CONFIG_MMC
 484 #define CONFIG_CMD_MMC
 485 #define CONFIG_FSL_ESDHC
 486 #define CONFIG_GENERIC_MMC
 487 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 488 #endif
 489
 490 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 491 #define CONFIG_CMD_EXT2
 492 #define CONFIG_CMD_FAT
 493 #define CONFIG_DOS_PARTITION
 494 #endif
 495
 496 #define CONFIG_TSEC_ENET
 497 #ifdef CONFIG_TSEC_ENET
 498
 499 #define CONFIG_TSECV2
 500
 501 #define CONFIG_MII                      /* MII PHY management */
 502 #define CONFIG_TSEC1            1
 503 #define CONFIG_TSEC1_NAME       "eTSEC1"
 504 #define CONFIG_TSEC2            1
 505 #define CONFIG_TSEC2_NAME       "eTSEC2"
 506
 507 #define TSEC1_PHY_ADDR          1
 508 #define TSEC2_PHY_ADDR          2
 509
 510 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 511 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 512
 513 #define TSEC1_PHYIDX            0
 514 #define TSEC2_PHYIDX            0
 515
 516 #define CONFIG_ETHPRIME         "eTSEC1"
 517
 518 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 519 #endif
 520
 521 /*
 522  * Environment
 523  */
 524 #ifdef CONFIG_RAMBOOT_SPIFLASH
 525 #define CONFIG_ENV_IS_IN_SPI_FLASH
 526 #define CONFIG_ENV_SPI_BUS      0
 527 #define CONFIG_ENV_SPI_CS       0
 528 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 529 #define CONFIG_ENV_SPI_MODE     0
 530 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 531 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 532 #define CONFIG_ENV_SECT_SIZE    0x10000
 533 #elif defined(CONFIG_RAMBOOT_SDCARD)
 534 #define CONFIG_ENV_IS_IN_MMC
 535 #define CONFIG_ENV_SIZE         0x2000
 536 #define CONFIG_SYS_MMC_ENV_DEV  0
 537 #elif defined(CONFIG_NAND)
 538 #define CONFIG_ENV_IS_IN_NAND
 539 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 540 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 541 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 542 #elif defined(CONFIG_SYS_RAMBOOT)
 543 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 544 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 545 #define CONFIG_ENV_SIZE         0x2000
 546 #else
 547 #define CONFIG_ENV_IS_IN_FLASH
 548 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 549 #define CONFIG_ENV_ADDR 0xfff80000
 550 #else
 551 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 552 #endif
 553 #define CONFIG_ENV_SIZE         0x2000
 554 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 555 #endif
 556
 557 #define CONFIG_LOADS_ECHO
 558 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 559
 560 /*
 561  * Command line configuration.
 562  */
 563 #include <config_cmd_default.h>
 564
 565 #define CONFIG_CMD_ELF
 566 #define CONFIG_CMD_ERRATA
 567 #define CONFIG_CMD_IRQ
 568 #define CONFIG_CMD_I2C
 569 #define CONFIG_CMD_MII
 570 #define CONFIG_CMD_PING
 571 #define CONFIG_CMD_SETEXPR
 572 #define CONFIG_CMD_REGINFO
 573
 574 #ifdef CONFIG_PCI
 575 #define CONFIG_CMD_PCI
 576 #define CONFIG_CMD_NET
 577 #endif
 578
 579 /*
 580  * USB
 581  */
 582 #define CONFIG_HAS_FSL_DR_USB
 583 #ifdef CONFIG_HAS_FSL_DR_USB
 584 #define CONFIG_USB_EHCI
 585
 586 #ifdef CONFIG_USB_EHCI
 587 #define CONFIG_CMD_USB
 588 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 589 #define CONFIG_USB_EHCI_FSL
 590 #define CONFIG_USB_STORAGE
 591 #define CONFIG_CMD_FAT
 592 #endif
 593 #endif
 594
 595 /*
 596  * Miscellaneous configurable options
 597  */
 598 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 599 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 600 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 601 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 602 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 603 #ifdef CONFIG_CMD_KGDB
 604 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 605 #else
 606 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 607 #endif
 608 /* Print Buffer Size */
 609 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 610 #define CONFIG_SYS_MAXARGS      16
 611 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 612 #define CONFIG_SYS_HZ           1000
 613
 614 /*
 615  * For booting Linux, the board info and command line data
 616  * have to be in the first 64 MB of memory, since this is
 617  * the maximum mapped by the Linux kernel during initialization.
 618  */
 619 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 620 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 621
 622 #ifdef CONFIG_CMD_KGDB
 623 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 624 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 625 #endif
 626
 627 /*
 628  * Environment Configuration
 629  */
 630
 631 #define CONFIG_HOSTNAME         p1022ds
 632 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 633 #define CONFIG_BOOTFILE         "uImage"
 634 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 635
 636 #define CONFIG_LOADADDR         1000000
 637
 638 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 639
 640 #define CONFIG_BAUDRATE 115200
 641
 642 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 643         "netdev=eth0\0"                                         \
 644         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 645         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 646         "tftpflash=tftpboot $loadaddr $uboot && "               \
 647                 "protect off $ubootaddr +$filesize && "         \
 648                 "erase $ubootaddr +$filesize && "               \
 649                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 650                 "protect on $ubootaddr +$filesize && "          \
 651                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 652         "consoledev=ttyS0\0"                                    \
 653         "ramdiskaddr=2000000\0"                                 \
 654         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 655         "fdtaddr=c00000\0"                                      \
 656         "fdtfile=p1022ds.dtb\0"                                 \
 657         "bdev=sda3\0"                                           \
 658         "hwconfig=esdhc;audclk:12\0"
 659
 660 #define CONFIG_HDBOOT                                   \
 661         "setenv bootargs root=/dev/$bdev rw "           \
 662         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 663         "tftp $loadaddr $bootfile;"                     \
 664         "tftp $fdtaddr $fdtfile;"                       \
 665         "bootm $loadaddr - $fdtaddr"
 666
 667 #define CONFIG_NFSBOOTCOMMAND                                           \
 668         "setenv bootargs root=/dev/nfs rw "                             \
 669         "nfsroot=$serverip:$rootpath "                                  \
 670         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 671         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 672         "tftp $loadaddr $bootfile;"                                     \
 673         "tftp $fdtaddr $fdtfile;"                                       \
 674         "bootm $loadaddr - $fdtaddr"
 675
 676 #define CONFIG_RAMBOOTCOMMAND                                           \
 677         "setenv bootargs root=/dev/ram rw "                             \
 678         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 679         "tftp $ramdiskaddr $ramdiskfile;"                               \
 680         "tftp $loadaddr $bootfile;"                                     \
 681         "tftp $fdtaddr $fdtfile;"                                       \
 682         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 683
 684 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 685
 686 #endif