include/configs/P1023RDB.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifndef CONFIG_SYS_TEXT_BASE
  14 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  15 #endif
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  23 #endif
  24
  25 /* High Level Configuration Options */
  26 #define CONFIG_BOOKE            /* BOOKE */
  27 #define CONFIG_E500             /* BOOKE e500 family */
  28 #define CONFIG_P1023
  29 #define CONFIG_MP               /* support multiple processors */
  30
  31 #define CONFIG_FSL_ELBC         /* Has Enhanced localbus controller */
  32 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
  33 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  34 #define CONFIG_PCIE2            /* PCIE controller 2 (slot 2) */
  35 #define CONFIG_PCIE3            /* PCIE controller 3 (slot 3) */
  36 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  37 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  38 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  39 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  40
  41 #ifndef __ASSEMBLY__
  42 extern unsigned long get_clock_freq(void);
  43 #endif
  44
  45 #define CONFIG_SYS_CLK_FREQ     66666666
  46 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  47
  48 /*
  49  * These can be toggled for performance analysis, otherwise use default.
  50  */
  51 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  52 #define CONFIG_BTB                      /* toggle branch predition */
  53 #define CONFIG_HWCONFIG
  54
  55 #define CONFIG_ENABLE_36BIT_PHYS
  56
  57 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
  58 #define CONFIG_SYS_MEMTEST_END          0x02000000
  59
  60 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  61
  62 /* Implement conversion of addresses in the LBC */
  63 #define CONFIG_SYS_LBC_LBCR             0x00000000
  64 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  65
  66 /* DDR Setup */
  67 #define CONFIG_VERY_BIG_RAM
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  69 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  70
  71 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  72 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  73
  74 #define CONFIG_DDR_SPD
  75 #define CONFIG_SYS_FSL_DDR3
  76 #define CONFIG_FSL_DDR_INTERACTIVE
  77 #define CONFIG_SYS_SDRAM_SIZE           512u    /* DDR is 512M */
  78 #define CONFIG_SYS_SPD_BUS_NUM          0
  79 #define SPD_EEPROM_ADDRESS              0x50
  80 #define CONFIG_SYS_DDR_RAW_TIMING
  81
  82 /*
  83  * Memory map
  84  *
  85  * 0x0000_0000  0x1fff_ffff     DDR                     512M cacheable
  86  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  87  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  88  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  89  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M cacheable
  90  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
  91  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K cacheable TLB0
  92  *
  93  * Localbus non-cacheable
  94  *
  95  * 0xec00_0000  0xefff_ffff     NOR flash               64M non-cacheable
  96  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
  97  */
  98
  99 /*
 100  * Local Bus Definitions
 101  */
 102 #define CONFIG_SYS_FLASH_BASE           0xec000000 /* start of FLASH 64M */
 103 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 104
 105 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 106                                 | BR_PS_16 | BR_V)
 107 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 108
 109 #define CONFIG_FLASH_CFI_DRIVER
 110 #define CONFIG_SYS_FLASH_CFI
 111 #define CONFIG_SYS_FLASH_EMPTY_INFO
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 113 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 114 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 115 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 116
 117 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f function */
 118 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 119
 120 #define CONFIG_SYS_INIT_RAM_LOCK
 121 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 122 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* Size of used area in RAM */
 123 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 124                                         GENERATED_GBL_DATA_SIZE)
 125 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 126
 127 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)      /* Reserve 512 kB for Mon */
 128 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 129
 130 #define CONFIG_SYS_NAND_BASE            0xffa00000
 131 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 132
 133 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 134 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 135 #define CONFIG_CMD_NAND
 136 #define CONFIG_NAND_FSL_ELBC
 137 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 138
 139 /* NAND flash config */
 140 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 141                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 142                                 | BR_PS_8               /* Port Size = 8bit */ \
 143                                 | BR_MS_FCM             /* MSEL = FCM */ \
 144                                 | BR_V)                 /* valid */
 145 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB         /* length 256K */ \
 146                                 | OR_FCM_PGS \
 147                                 | OR_FCM_CSCT \
 148                                 | OR_FCM_CST \
 149                                 | OR_FCM_CHT \
 150                                 | OR_FCM_SCY_1 \
 151                                 | OR_FCM_TRLX \
 152                                 | OR_FCM_EHTR)
 153
 154 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 155 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 156 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 157 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 158
 159 /* Serial Port */
 160 #define CONFIG_CONS_INDEX               1
 161 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 162 #define CONFIG_SYS_NS16550_SERIAL
 163 #define CONFIG_SYS_NS16550_REG_SIZE     1
 164 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 165
 166 #define CONFIG_SYS_BAUDRATE_TABLE       \
 167         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 168
 169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 171
 172 /* I2C */
 173 #define CONFIG_SYS_I2C
 174 #define CONFIG_SYS_I2C_FSL
 175 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 176 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 177 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 178 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 179 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 180 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 181
 182 /*
 183  * I2C2 EEPROM
 184  */
 185 #define CONFIG_ID_EEPROM
 186 #ifdef CONFIG_ID_EEPROM
 187 #define CONFIG_SYS_I2C_EEPROM_NXID
 188 #endif
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 191 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 192
 193 /*
 194  * General PCI
 195  * Memory space is mapped 1-1, but I/O space must start from 0.
 196  */
 197
 198 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 199 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 200 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 201 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 202 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 203 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 204 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 205 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 206 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 207 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 208
 209 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 210 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 211 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 212 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 213 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 214 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 215 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 216 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 217 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 218 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 219
 220 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 221 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 222 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 223 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 224 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 225 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 226 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 227 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 228 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 229 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 230
 231 #if defined(CONFIG_PCI)
 232 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 233 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 234 #endif  /* CONFIG_PCI */
 235
 236 /*
 237  * Environment
 238  */
 239 #define CONFIG_ENV_OVERWRITE
 240
 241 #define CONFIG_ENV_IS_IN_FLASH
 242 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 243 #define CONFIG_ENV_SIZE         0x2000
 244 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 245
 246 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 247 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 248
 249 /*
 250  * Command line configuration.
 251  */
 252 #define CONFIG_CMD_IRQ
 253 #define CONFIG_CMD_REGINFO
 254
 255 #if defined(CONFIG_PCI)
 256 #define CONFIG_CMD_PCI
 257 #endif
 258
 259 /*
 260  * USB
 261  */
 262 #define CONFIG_HAS_FSL_DR_USB
 263 #ifdef CONFIG_HAS_FSL_DR_USB
 264 #define CONFIG_USB_EHCI
 265
 266 #ifdef CONFIG_USB_EHCI
 267 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 268 #define CONFIG_USB_EHCI_FSL
 269 #define CONFIG_DOS_PARTITION
 270 #endif
 271 #endif
 272
 273 /*
 274  * Miscellaneous configurable options
 275  */
 276 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 277 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 278 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 279 #if defined(CONFIG_CMD_KGDB)
 280 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 281 #else
 282 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 283 #endif
 284 /* Print Buffer Size */
 285 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 286 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 287 /* Boot Argument Buffer Size */
 288 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 289
 290 /*
 291  * For booting Linux, the board info and command line data
 292  * have to be in the first 64 MB of memory, since this is
 293  * the maximum mapped by the Linux kernel during initialization.
 294  */
 295 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)   /* Initial Memory map for Linux*/
 296 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)   /* Increase max gunzip size */
 297
 298 /*
 299  * Environment Configuration
 300  */
 301 #define CONFIG_BOOTFILE         "uImage"
 302 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 303
 304 /* default location for tftp and bootm */
 305 #define CONFIG_LOADADDR         1000000
 306
 307
 308 #define CONFIG_BAUDRATE 115200
 309
 310 /* Qman/Bman */
 311 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
 312 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 313 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 314 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 315 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 316 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 317 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 318 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 319 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 320                                         CONFIG_SYS_QMAN_CENA_SIZE)
 321 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 322 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 323 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 324 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 325 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 326 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 327 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 328 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 329 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 330 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 331                                         CONFIG_SYS_BMAN_CENA_SIZE)
 332 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 333 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 334
 335 /* For FM */
 336 #define CONFIG_SYS_DPAA_FMAN
 337 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 338
 339 #ifdef CONFIG_SYS_DPAA_FMAN
 340 #define CONFIG_FMAN_ENET
 341 #define CONFIG_PHY_ATHEROS
 342 #endif
 343
 344 /* Default address of microcode for the Linux Fman driver */
 345 /* QE microcode/firmware address */
 346 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 347 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 348 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 349 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 350
 351 #ifdef CONFIG_FMAN_ENET
 352 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1
 353 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x2
 354
 355 #define CONFIG_SYS_TBIPA_VALUE  8
 356 #define CONFIG_MII              /* MII PHY management */
 357 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 358 #endif
 359
 360 #define CONFIG_EXTRA_ENV_SETTINGS       \
 361         "netdev=eth0\0"                                         \
 362         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 363         "loadaddr=1000000\0"                                    \
 364         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 365         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 366                 "protect off $ubootaddr +$filesize; "           \
 367                 "erase $ubootaddr +$filesize; "                 \
 368                 "cp.b $loadaddr $ubootaddr $filesize; "         \
 369                 "protect on $ubootaddr +$filesize; "            \
 370                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 371         "consoledev=ttyS0\0"                                    \
 372         "ramdiskaddr=2000000\0"                                 \
 373         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 374         "fdtaddr=1e00000\0"                                     \
 375         "fdtfile=p1023rdb.dtb\0"                                \
 376         "othbootargs=ramdisk_size=600000\0"                     \
 377         "bdev=sda1\0"                                           \
 378         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 379
 380 #define CONFIG_HDBOOT                                   \
 381         "setenv bootargs root=/dev/$bdev rw "           \
 382         "console=$consoledev,$baudrate $othbootargs;"   \
 383         "tftp $loadaddr $bootfile;"                     \
 384         "tftp $fdtaddr $fdtfile;"                       \
 385         "bootm $loadaddr - $fdtaddr"
 386
 387 #define CONFIG_NFSBOOTCOMMAND                                           \
 388         "setenv bootargs root=/dev/nfs rw "                             \
 389         "nfsroot=$serverip:$rootpath "                                  \
 390         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 391         "console=$consoledev,$baudrate $othbootargs;"                   \
 392         "tftp $loadaddr $bootfile;"                                     \
 393         "tftp $fdtaddr $fdtfile;"                                       \
 394         "bootm $loadaddr - $fdtaddr"
 395
 396 #define CONFIG_RAMBOOTCOMMAND                                           \
 397         "setenv bootargs root=/dev/ram rw "                             \
 398         "console=$consoledev,$baudrate $othbootargs;"                   \
 399         "tftp $ramdiskaddr $ramdiskfile;"                               \
 400         "tftp $loadaddr $bootfile;"                                     \
 401         "tftp $fdtaddr $fdtfile;"                                       \
 402         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 403
 404 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 405
 406 #endif  /* __CONFIG_H */