include/configs/P1023RDS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <b25806@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * p1023rds board configuration file
  12  *
  13  */
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #ifdef CONFIG_NAND
  18 #define CONFIG_NAND_U_BOOT
  19 #define CONFIG_RAMBOOT_NAND
  20 #endif
  21
  22 #ifdef CONFIG_NAND_U_BOOT
  23 #define CONFIG_SYS_TEXT_BASE_SPL        0xfff00000
  24 #define CONFIG_SYS_TEXT_BASE            0x11001000
  25
  26 #ifdef CONFIG_NAND_SPL
  27 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  28 #else
  29 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  30 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  31 #endif /* CONFIG_NAND_SPL */
  32 #endif
  33
  34 #ifndef CONFIG_SYS_TEXT_BASE
  35 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  36 #endif
  37
  38 #ifndef CONFIG_SYS_MONITOR_BASE
  39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  40 #endif
  41
  42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  43 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  44 #endif
  45
  46 /* High Level Configuration Options */
  47 #define CONFIG_BOOKE            /* BOOKE */
  48 #define CONFIG_E500             /* BOOKE e500 family */
  49 #define CONFIG_MPC85xx
  50 #define CONFIG_P1023
  51 #define CONFIG_P1023RDS
  52 #define CONFIG_MP               /* support multiple processors */
  53
  54 #define CONFIG_FSL_ELBC         /* Has Enhanced localbus controller */
  55 #define CONFIG_PCI              /* Enable PCI/PCIE */
  56 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  57 #define CONFIG_PCIE2            /* PCIE controler 2 (slot 2) */
  58 #define CONFIG_PCIE3            /* PCIE controler 3 (slot 3) */
  59 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  60 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  61 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  62 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  63 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  64
  65 #ifndef __ASSEMBLY__
  66 extern unsigned long get_clock_freq(void);
  67 #endif
  68
  69 #define CONFIG_SYS_CLK_FREQ     66666666
  70 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  71
  72 /*
  73  * These can be toggled for performance analysis, otherwise use default.
  74  */
  75 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  76 #define CONFIG_BTB                      /* toggle branch predition */
  77 #define CONFIG_HWCONFIG
  78
  79 #define CONFIG_ENABLE_36BIT_PHYS
  80
  81 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  82 #define CONFIG_SYS_MEMTEST_END          0x1fffffff      /* fix me, only 1G */
  83 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  84
  85 #define CONFIG_SYS_LBC_LBCR     0x00000000      /* Implement conversion of
  86                                                 addresses in the LBC */
  87
  88 /* DDR Setup */
  89 #define CONFIG_VERY_BIG_RAM
  90
  91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  92 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  93
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  96
  97 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  98 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  99
 100 /* These are used when DDR doesn't use SPD.  */
 101 #define CONFIG_SYS_SDRAM_SIZE           2048u   /* DDR is 2GB */
 102
 103 /* Default settings for "stable" mode */
 104 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 105 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 106 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 107 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 108 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 109 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 110 #define CONFIG_SYS_DDR_TIMING_1         0x5C59E544
 111 #define CONFIG_SYS_DDR_TIMING_2         0x0fA888CA
 112 #define CONFIG_SYS_DDR_MODE_1           0x00441210
 113 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 114 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
 115 #define CONFIG_SYS_DDR_INTERVAL         0x0A280100
 116 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 117 #define CONFIG_SYS_DDR_CLK_CTRL         0x01800000
 118 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 119 #define CONFIG_SYS_DDR_TIMING_5         0x01401400
 120 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 121 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8675F605
 122 #define CONFIG_SYS_DDR_CONTROL  0xC70C0008 /* Type = DDR3: No Interleaving */
 123 #define CONFIG_SYS_DDR_CONTROL2         0x24401010
 124 #define CONFIG_SYS_DDR_CDR1             0x00000000
 125 #define CONFIG_SYS_DDR_CDR2             0x00000000
 126
 127 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 128 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 129 #define CONFIG_SYS_DDR_SBE              0x00000000
 130
 131 /* Settings that differ for "performance" mode */
 132 #define CONFIG_SYS_DDR_CS0_BNDS_PERF    0x0000007F /* Interleaving Enabled */
 133 #define CONFIG_SYS_DDR_CS1_BNDS_PERF    0x00000000 /* Interleaving Enabled */
 134 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014302
 135 #define CONFIG_SYS_DDR_TIMING_1_PERF    0x5C58E544
 136 #define CONFIG_SYS_DDR_TIMING_2_PERF    0x0FA888CA
 137 /* Type = DDR3: cs0-cs1 interleaving */
 138 #define CONFIG_SYS_DDR_CONTROL_PERF     0xC70C4008
 139 #define CONFIG_SYS_DDR_CDR_1            0x00000000
 140 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 141
 142
 143 /*
 144  * Memory map
 145  *
 146  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 147  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 148  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 149  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 150  *
 151  * Localbus non-cacheable
 152  * 0xe000_0000  0xe003_ffff     BCSR                    256K BCSR
 153  * 0xee00_0000  0xefff_ffff     NOR flash               32M NOR flash
 154  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M
 155  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
 156  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 157  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 158  */
 159
 160 /*
 161  * Local Bus Definitions
 162  */
 163 #define CONFIG_SYS_BCSR_BASE            0xe0000000 /* start of on board FPGA */
 164 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 165
 166 #ifndef CONFIG_NAND
 167 #define CONFIG_SYS_FLASH_BASE           0xee000000 /* start of FLASH 32M */
 168
 169 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 170
 171 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 172                 | BR_PS_16 | BR_V)
 173 #define CONFIG_FLASH_OR_PRELIM  0xfe000ff7
 174
 175 #define CONFIG_FLASH_CFI_DRIVER
 176 #define CONFIG_SYS_FLASH_CFI
 177 #define CONFIG_SYS_FLASH_EMPTY_INFO
 178
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 181 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 182 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 183 #else
 184 #define CONFIG_SYS_NO_FLASH
 185 #endif
 186
 187 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
 188 #define CONFIG_SYS_RAMBOOT
 189 #endif
 190
 191 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f function */
 192 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 193
 194 #define CONFIG_SYS_INIT_RAM_LOCK
 195 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 196 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 197
 198 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 199 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 200         (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 201 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 202
 203 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 204 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 205
 206 #ifndef CONFIG_NAND_SPL
 207 #define CONFIG_SYS_NAND_BASE            0xffa00000
 208 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 209 #else
 210 #define CONFIG_SYS_NAND_BASE            0xfff00000
 211 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 212 #endif
 213
 214 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 215 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 216 #define CONFIG_MTD_NAND_VERIFY_WRITE
 217 #define CONFIG_CMD_NAND
 218 #define CONFIG_NAND_FSL_ELBC
 219 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 220
 221 /* NAND boot: 4K NAND loader config */
 222 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 223 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
 224 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
 225 #define CONFIG_SYS_NAND_U_BOOT_START    0x11000000
 226 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 227 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
 228 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 229
 230 /* NAND flash config */
 231 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 232                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 233                                 | BR_PS_8               /* Port Size = 8bit */ \
 234                                 | BR_MS_FCM             /* MSEL = FCM */ \
 235                                 | BR_V)                 /* valid */
 236 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFF80000          /* length 32K */ \
 237                                 | OR_FCM_CSCT \
 238                                 | OR_FCM_CST \
 239                                 | OR_FCM_CHT \
 240                                 | OR_FCM_SCY_1 \
 241                                 | OR_FCM_TRLX \
 242                                 | OR_FCM_EHTR)
 243
 244 #ifdef CONFIG_RAMBOOT_NAND
 245 /* NAND Base Address */
 246 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 247 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 248 /* chip select 1 - BCSR */
 249 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
 250                                 | BR_MS_GPCM | BR_PS_8 | BR_V)
 251 #define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
 252                                 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
 253                                 | OR_GPCM_EAD)
 254 #else
 255 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 256 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 257 /* chip select 1 - BCSR */
 258 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
 259                                 | BR_MS_GPCM | BR_PS_8 | BR_V)
 260 #define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
 261                                 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
 262                                 | OR_GPCM_EAD)
 263 #endif
 264
 265 /* Serial Port
 266  * open - index 2
 267  * shorted - index 1
 268  */
 269 #define CONFIG_CONS_INDEX               1
 270 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 271 #define CONFIG_SYS_NS16550
 272 #define CONFIG_SYS_NS16550_SERIAL
 273 #define CONFIG_SYS_NS16550_REG_SIZE     1
 274 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 275 #ifdef CONFIG_NAND_SPL
 276 #define CONFIG_NS16550_MIN_FUNCTIONS
 277 #endif
 278
 279 #define CONFIG_SYS_BAUDRATE_TABLE       \
 280         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 281
 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 284
 285 /* Use the HUSH parser */
 286 #define CONFIG_SYS_HUSH_PARSER
 287
 288 /*
 289  * Pass open firmware flat tree
 290  */
 291 #define CONFIG_OF_LIBFDT
 292 #define CONFIG_OF_BOARD_SETUP
 293 #define CONFIG_OF_STDOUT_VIA_ALIAS
 294
 295 /* new uImage format support */
 296 #define CONFIG_FIT
 297 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 298
 299 /* I2C */
 300 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 301 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 302 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 303 #define CONFIG_I2C_MULTI_BUS
 304 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 305 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x51
 306 #define CONFIG_SYS_I2C_SLAVE            0x7F
 307 #define CONFIG_SYS_I2C_OFFSET           0x3000
 308 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 309
 310 /*
 311  * I2C2 EEPROM
 312  */
 313 #define CONFIG_ID_EEPROM
 314 #ifdef CONFIG_ID_EEPROM
 315 #define CONFIG_SYS_I2C_EEPROM_NXID
 316 #endif
 317 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x51
 318 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 319 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 320
 321 #define CONFIG_CMD_I2C
 322
 323 /*
 324  * eSPI - Enhanced SPI
 325  */
 326 #define CONFIG_SPI_FLASH
 327 #define CONFIG_SPI_FLASH_ATMEL
 328
 329 #define CONFIG_HARD_SPI
 330 #define CONFIG_FSL_ESPI
 331
 332 #define CONFIG_CMD_SF
 333 #define CONFIG_SF_DEFAULT_SPEED         10000000
 334 #define CONFIG_SF_DEFAULT_MODE          0
 335
 336 /*
 337  * General PCI
 338  * Memory space is mapped 1-1, but I/O space must start from 0.
 339  */
 340
 341 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 342 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 343 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 344 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 345 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 346 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 347 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 348 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 349 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 350 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 351
 352 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 353 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 354 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 355 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 356 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 357 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 358 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 359 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 360 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 361 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 362
 363 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 364 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 365 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 366 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 367 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 368 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 369 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 370 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 371 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 372 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 373
 374 #if defined(CONFIG_PCI)
 375 #define CONFIG_E1000            /* Defind e1000 pci Ethernet card */
 376 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 377 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 378 #endif  /* CONFIG_PCI */
 379
 380 /*
 381  * Environment
 382  */
 383 #define CONFIG_ENV_OVERWRITE
 384
 385 #if defined(CONFIG_SYS_RAMBOOT)
 386 #if defined(CONFIG_RAMBOOT_NAND)
 387 #define CONFIG_ENV_IS_IN_NAND
 388 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 389 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 390 #else
 391 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 392 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x4000)
 393 #define CONFIG_ENV_SIZE         0x2000
 394 #endif
 395 #else
 396 #define CONFIG_ENV_IS_IN_FLASH
 397 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 398 #define CONFIG_ENV_ADDR         0xfff80000
 399 #else
 400 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 401 #endif
 402 #define CONFIG_ENV_SIZE         0x2000
 403 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 404 #endif
 405
 406 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 407 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 408
 409 /*
 410  * Command line configuration.
 411  */
 412 #include <config_cmd_default.h>
 413
 414 #define CONFIG_CMD_IRQ
 415 #define CONFIG_CMD_PING
 416 #define CONFIG_CMD_MII
 417 #define CONFIG_CMD_ELF
 418 #define CONFIG_CMD_SETEXPR
 419 #define CONFIG_CMD_REGINFO
 420
 421 #if defined(CONFIG_PCI)
 422 #define CONFIG_CMD_PCI
 423 #define CONFIG_CMD_NET
 424 #endif
 425
 426 /*
 427  * USB
 428  */
 429 #define CONFIG_HAS_FSL_DR_USB
 430 #ifdef CONFIG_HAS_FSL_DR_USB
 431 #define CONFIG_USB_EHCI
 432
 433 #ifdef CONFIG_USB_EHCI
 434 #define CONFIG_CMD_USB
 435 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 436 #define CONFIG_USB_EHCI_FSL
 437 #define CONFIG_USB_STORAGE
 438 #define CONFIG_CMD_FAT
 439 #define CONFIG_CMD_EXT2
 440 #define CONFIG_CMD_FAT
 441 #define CONFIG_DOS_PARTITION
 442 #endif
 443 #endif
 444
 445 /*
 446  * Miscellaneous configurable options
 447  */
 448 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 449 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 450 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 451 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 452 #if defined(CONFIG_CMD_KGDB)
 453 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 454 #else
 455 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 456 #endif
 457 /* Print Buffer Size */
 458 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 459 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 460 /* Boot Argument Buffer Size */
 461 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 462 #define CONFIG_SYS_HZ   1000            /* decrementer freq: 1ms ticks */
 463
 464 /*
 465  * For booting Linux, the board info and command line data
 466  * have to be in the first 16 MB of memory, since this is
 467  * the maximum mapped by the Linux kernel during initialization.
 468  */
 469 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20) /* Initial Memory map for Linux*/
 470 #define CONFIG_SYS_BOOTM_LEN    (16 << 20) /* Increase max gunzip size */
 471
 472 #if defined(CONFIG_CMD_KGDB)
 473 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 474 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 475 #endif
 476
 477 /*
 478  * Environment Configuration
 479  */
 480 #define CONFIG_BOOTFILE         "uImage"
 481 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 482
 483 /* default location for tftp and bootm */
 484 #define CONFIG_LOADADDR         1000000
 485
 486 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 487
 488 #define CONFIG_BAUDRATE 115200
 489
 490 /* Qman/Bman */
 491 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
 492 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 493 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 494 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 495 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 496 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 497 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 498
 499 /* For FM */
 500 #define CONFIG_SYS_DPAA_FMAN
 501 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 502
 503 #ifdef CONFIG_SYS_DPAA_FMAN
 504 #define CONFIG_FMAN_ENET
 505 #define CONFIG_PHY_MARVELL
 506 #endif
 507
 508 #ifndef CONFIG_NAND
 509 /* Default address of microcode for the Linux Fman driver */
 510 /* QE microcode/firmware address */
 511 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 512 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEFF40000
 513 #else
 514 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 515 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x1f00000
 516 #endif
 517 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 518 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 519
 520 #ifdef CONFIG_FMAN_ENET
 521 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 522 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x7
 523
 524 #define CONFIG_SYS_TBIPA_VALUE  8
 525 #define CONFIG_MII              /* MII PHY management */
 526 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 527 #endif
 528
 529 #define CONFIG_EXTRA_ENV_SETTINGS       \
 530         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 531
 532 #endif  /* __CONFIG_H */