include/configs/P1_P2_RDB.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P1 P2 RDB board configuration file
  25  * This file is intended to address a set of Low End and Ultra Low End
  26  * Freescale SOCs of QorIQ series(RDB platforms).
  27  * Currently only P2020RDB
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #ifdef CONFIG_36BIT
  34 #define CONFIG_PHYS_64BIT
  35 #endif
  36
  37 #ifdef CONFIG_P1011RDB
  38 #define CONFIG_P1011
  39 #endif
  40 #ifdef CONFIG_P1020RDB
  41 #define CONFIG_P1020
  42 #endif
  43 #ifdef CONFIG_P2010RDB
  44 #define CONFIG_P2010
  45 #endif
  46 #ifdef CONFIG_P2020RDB
  47 #define CONFIG_P2020
  48 #endif
  49
  50 #ifdef CONFIG_NAND
  51 #define CONFIG_NAND_U_BOOT              1
  52 #define CONFIG_RAMBOOT_NAND             1
  53 #ifdef CONFIG_NAND_SPL
  54 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  56 #else
  57 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  58 #define CONFIG_SYS_TEXT_BASE            0xf8f82000
  59 #endif /* CONFIG_NAND_SPL */
  60 #endif
  61
  62 #ifdef CONFIG_SDCARD
  63 #define CONFIG_RAMBOOT_SDCARD           1
  64 #define CONFIG_SYS_TEXT_BASE            0x11000000
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  66 #endif
  67
  68 #ifdef CONFIG_SPIFLASH
  69 #define CONFIG_RAMBOOT_SPIFLASH         1
  70 #define CONFIG_SYS_TEXT_BASE            0x11000000
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  72 #endif
  73
  74 #ifndef CONFIG_SYS_TEXT_BASE
  75 #define CONFIG_SYS_TEXT_BASE            0xeff80000
  76 #endif
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 #ifndef CONFIG_SYS_MONITOR_BASE
  83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  84 #endif
  85
  86 /* High Level Configuration Options */
  87 #define CONFIG_BOOKE            1       /* BOOKE */
  88 #define CONFIG_E500             1       /* BOOKE e500 family */
  89 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  90 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  91
  92 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  93 #if defined(CONFIG_PCI)
  94 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  95 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  96 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  97 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  98 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  99 #endif /* #if defined(CONFIG_PCI) */
 100 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
 101 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 102 #define CONFIG_ENV_OVERWRITE
 103
 104 #if defined(CONFIG_PCI)
 105 #define CONFIG_E1000            1       /*  E1000 pci Ethernet card*/
 106 #endif
 107
 108 #ifndef __ASSEMBLY__
 109 extern unsigned long get_board_sys_clk(unsigned long dummy);
 110 #endif
 111 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1_P2 RDB */
 112 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
 113
 114 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
 115 #define CONFIG_MP
 116 #endif
 117
 118 #define CONFIG_HWCONFIG
 119
 120 /*
 121  * These can be toggled for performance analysis, otherwise use default.
 122  */
 123 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 124 #define CONFIG_BTB                      /* toggle branch predition */
 125
 126 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 127
 128 #define CONFIG_ENABLE_36BIT_PHYS        1
 129
 130 #ifdef CONFIG_PHYS_64BIT
 131 #define CONFIG_ADDR_MAP                 1
 132 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 133 #endif
 134
 135 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
 136 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 137 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 138
 139  /*
 140   * Config the L2 Cache as L2 SRAM
 141   */
 142 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 143 #ifdef CONFIG_PHYS_64BIT
 144 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 145 #else
 146 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 147 #endif
 148 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 149 #define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 150
 151 #define CONFIG_SYS_CCSRBAR              0xffe00000
 152 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 153
 154 #if defined(CONFIG_NAND_SPL)
 155 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 156 #endif
 157
 158 /* DDR Setup */
 159 #define CONFIG_FSL_DDR2
 160 #undef CONFIG_FSL_DDR_INTERACTIVE
 161 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 162
 163 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 164
 165 #define CONFIG_SYS_SDRAM_SIZE   1024    /* DDR size on P1_P2 RDBs */
 166 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 167 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 168
 169 #define CONFIG_NUM_DDR_CONTROLLERS      1
 170 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 171 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 172
 173 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 174 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 175 #define CONFIG_SYS_DDR_SBE              0x00FF0000
 176
 177 /*
 178  * Memory map
 179  *
 180  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheablen
 181  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 182  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 183  *
 184  * Localbus cacheable (TBD)
 185  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 186  *
 187  * Localbus non-cacheable
 188  * 0xef00_0000  0xefff_ffff     FLASH                   16M non-cacheable
 189  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 190  * 0xffb0_0000  0xffbf_ffff     VSC7385 switch          1M non-cacheable
 191  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 192  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 193  */
 194
 195 /*
 196  * Local Bus Definitions
 197  */
 198 #define CONFIG_SYS_FLASH_BASE           0xef000000      /* start of FLASH 16M */
 199
 200 #ifdef CONFIG_PHYS_64BIT
 201 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfef000000ull
 202 #else
 203 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 204 #endif
 205
 206 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 207                                         BR_PS_16 | BR_V)
 208 #define CONFIG_FLASH_OR_PRELIM          0xff000ff7
 209
 210 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 211 #define CONFIG_SYS_FLASH_QUIET_TEST
 212 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 213
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 216 #undef  CONFIG_SYS_FLASH_CHECKSUM
 217 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 218 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 219
 220 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 221     defined(CONFIG_RAMBOOT_SPIFLASH)
 222 #define CONFIG_SYS_RAMBOOT
 223 #define CONFIG_SYS_EXTRA_ENV_RELOC
 224 #else
 225 #undef CONFIG_SYS_RAMBOOT
 226 #endif
 227
 228 #define CONFIG_FLASH_CFI_DRIVER
 229 #define CONFIG_SYS_FLASH_CFI
 230 #define CONFIG_SYS_FLASH_EMPTY_INFO
 231 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 232
 233 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 234 #define CONFIG_MISC_INIT_R
 235 #define CONFIG_HWCONFIG
 236
 237 #define CONFIG_SYS_INIT_RAM_LOCK        1
 238 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000        /* stack in RAM */
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 242 /* The assembler doesn't like typecast */
 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 244         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 245           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 246 #else
 247 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 248 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 249 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 250 #endif
 251 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 252
 253 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 254                                                 - GENERATED_GBL_DATA_SIZE)
 255 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 256
 257 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 258 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 259
 260 #ifndef CONFIG_NAND_SPL
 261 #define CONFIG_SYS_NAND_BASE            0xffa00000
 262 #ifdef CONFIG_PHYS_64BIT
 263 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 264 #else
 265 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 266 #endif
 267 #else
 268 #define CONFIG_SYS_NAND_BASE            0xfff00000
 269 #ifdef CONFIG_PHYS_64BIT
 270 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 271 #else
 272 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 273 #endif
 274 #endif
 275
 276 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 277 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 278 #define NAND_MAX_CHIPS                  1
 279 #define CONFIG_MTD_NAND_VERIFY_WRITE
 280 #define CONFIG_CMD_NAND                 1
 281 #define CONFIG_NAND_FSL_ELBC            1
 282 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 283
 284 /* NAND boot: 4K NAND loader config */
 285 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 286 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 287 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 288 #define CONFIG_SYS_NAND_U_BOOT_START    (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 289 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 290 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 291 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP         ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 292
 293 /* NAND flash config */
 294 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 295                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 296                                 | BR_PS_8       /* Port Size = 8 bit */ \
 297                                 | BR_MS_FCM             /* MSEL = FCM */ \
 298                                 | BR_V)                 /* valid */
 299
 300 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFF80000     /* length 32K */ \
 301                                 | OR_FCM_CSCT \
 302                                 | OR_FCM_CST \
 303                                 | OR_FCM_CHT \
 304                                 | OR_FCM_SCY_1 \
 305                                 | OR_FCM_TRLX \
 306                                 | OR_FCM_EHTR)
 307
 308 #ifdef CONFIG_RAMBOOT_NAND
 309 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 310 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 311 #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 312 #define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 313 #else
 314 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 315 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 316 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 317 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 318 #endif
 319
 320 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 321
 322 #ifdef CONFIG_PHYS_64BIT
 323 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 324 #else
 325 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 326 #endif
 327
 328 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
 329                                                         | BR_PS_8 | BR_V)
 330 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 331                                 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 332                                 OR_GPCM_EHTR | OR_GPCM_EAD)
 333
 334 /* Serial Port - controlled on board with jumper J8
 335  * open - index 2
 336  * shorted - index 1
 337  */
 338 #define CONFIG_CONS_INDEX       1
 339 #define CONFIG_SYS_NS16550
 340 #define CONFIG_SYS_NS16550_SERIAL
 341 #define CONFIG_SYS_NS16550_REG_SIZE     1
 342 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 343 #ifdef CONFIG_NAND_SPL
 344 #define CONFIG_NS16550_MIN_FUNCTIONS
 345 #endif
 346
 347 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 348 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 349
 350 #define CONFIG_SYS_BAUDRATE_TABLE       \
 351         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 352
 353 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 354 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 355
 356 /* Use the HUSH parser */
 357 #define CONFIG_SYS_HUSH_PARSER
 358 #ifdef  CONFIG_SYS_HUSH_PARSER
 359 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 360 #endif
 361
 362 /*
 363  * Pass open firmware flat tree
 364  */
 365 #define CONFIG_OF_LIBFDT                1
 366 #define CONFIG_OF_BOARD_SETUP           1
 367 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 368
 369 /* new uImage format support */
 370 #define CONFIG_FIT              1
 371 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 372
 373 /* I2C */
 374 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 375 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 376 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 377 #define CONFIG_I2C_MULTI_BUS
 378 #define CONFIG_I2C_CMD_TREE
 379 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address*/
 380 #define CONFIG_SYS_I2C_SLAVE            0x7F
 381 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}      /* Don't probe these addrs */
 382 #define CONFIG_SYS_I2C_OFFSET           0x3000
 383 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 384
 385 /*
 386  * I2C2 EEPROM
 387  */
 388 #define CONFIG_ID_EEPROM
 389 #ifdef CONFIG_ID_EEPROM
 390 #define CONFIG_SYS_I2C_EEPROM_NXID
 391 #endif
 392 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 393 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 394 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 395
 396 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 397
 398 #define CONFIG_RTC_DS1337
 399 #define CONFIG_SYS_RTC_DS1337_NOOSC
 400 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 401
 402 /* eSPI - Enhanced SPI */
 403 #define CONFIG_FSL_ESPI
 404 #define CONFIG_SPI_FLASH
 405 #define CONFIG_SPI_FLASH_SPANSION
 406 #define CONFIG_CMD_SF
 407 #define CONFIG_SF_DEFAULT_SPEED         10000000
 408 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 409
 410 /*
 411  * General PCI
 412  * Memory space is mapped 1-1, but I/O space must start from 0.
 413  */
 414
 415 #if defined(CONFIG_PCI)
 416 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 417 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 418 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 419 #ifdef CONFIG_PHYS_64BIT
 420 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 421 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 422 #else
 423 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 424 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 425 #endif
 426 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 427 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 428 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 429 #ifdef CONFIG_PHYS_64BIT
 430 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 431 #else
 432 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 433 #endif
 434 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 435
 436 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 437 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 438 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 439 #ifdef CONFIG_PHYS_64BIT
 440 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 441 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 442 #else
 443 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 444 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 445 #endif
 446 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 447 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 448 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 449 #ifdef CONFIG_PHYS_64BIT
 450 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 451 #else
 452 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 453 #endif
 454 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 455
 456 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 457
 458 #undef CONFIG_EEPRO100
 459 #undef CONFIG_TULIP
 460 #undef CONFIG_RTL8139
 461
 462 #ifdef CONFIG_RTL8139
 463 /* This macro is used by RTL8139 but not defined in PPC architecture */
 464 #define KSEG1ADDR(x)            (x)
 465 #define _IO_BASE        0x00000000
 466 #endif
 467
 468
 469 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 470 #define CONFIG_DOS_PARTITION
 471
 472 #endif  /* CONFIG_PCI */
 473
 474
 475 #if defined(CONFIG_TSEC_ENET)
 476 #define CONFIG_MII              1       /* MII PHY management */
 477 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 478 #define CONFIG_TSEC1    1
 479 #define CONFIG_TSEC1_NAME       "eTSEC1"
 480 #define CONFIG_TSEC2    1
 481 #define CONFIG_TSEC2_NAME       "eTSEC2"
 482 #define CONFIG_TSEC3    1
 483 #define CONFIG_TSEC3_NAME       "eTSEC3"
 484
 485 #define TSEC1_PHY_ADDR          2
 486 #define TSEC2_PHY_ADDR          0
 487 #define TSEC3_PHY_ADDR          1
 488
 489 #define CONFIG_VSC7385_ENET
 490
 491 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 492 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 493 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 494
 495 #define TSEC1_PHYIDX            0
 496 #define TSEC2_PHYIDX            0
 497 #define TSEC3_PHYIDX            0
 498
 499 /* Vitesse 7385 */
 500
 501 #ifdef CONFIG_VSC7385_ENET
 502 /* The size of the VSC7385 firmware image */
 503 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 504 #endif
 505
 506 #define CONFIG_ETHPRIME         "eTSEC1"
 507
 508 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 509
 510 #endif  /* CONFIG_TSEC_ENET */
 511
 512 /*
 513  * Environment
 514  */
 515 #if defined(CONFIG_SYS_RAMBOOT)
 516 #if defined(CONFIG_RAMBOOT_NAND)
 517         #define CONFIG_ENV_IS_IN_NAND   1
 518         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 519         #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 520 #elif defined(CONFIG_RAMBOOT_SDCARD)
 521 #define CONFIG_ENV_IS_IN_MMC
 522 #define CONFIG_ENV_SIZE                 0x2000
 523 #define CONFIG_SYS_MMC_ENV_DEV          0
 524 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 525         #define CONFIG_ENV_IS_IN_SPI_FLASH
 526         #define CONFIG_ENV_SPI_BUS      0
 527         #define CONFIG_ENV_SPI_CS       0
 528         #define CONFIG_ENV_SPI_MAX_HZ   10000000
 529         #define CONFIG_ENV_SPI_MODE     0
 530         #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 531         #define CONFIG_ENV_SECT_SIZE    0x10000
 532         #define CONFIG_ENV_SIZE         0x2000
 533 #endif
 534 #else
 535         #define CONFIG_ENV_IS_IN_FLASH  1
 536         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 537         #define CONFIG_ENV_ADDR         0xfff80000
 538         #else
 539         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 540         #endif
 541         #define CONFIG_ENV_SIZE         0x2000
 542         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 543 #endif
 544
 545 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 546 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 547
 548 /*
 549  * Command line configuration.
 550  */
 551 #include <config_cmd_default.h>
 552
 553 #define CONFIG_CMD_DATE
 554 #define CONFIG_CMD_ELF
 555 #define CONFIG_CMD_I2C
 556 #define CONFIG_CMD_IRQ
 557 #define CONFIG_CMD_MII
 558 #define CONFIG_CMD_PING
 559 #define CONFIG_CMD_SETEXPR
 560 #define CONFIG_CMD_REGINFO
 561
 562 #if defined(CONFIG_PCI)
 563 #define CONFIG_CMD_NET
 564 #define CONFIG_CMD_PCI
 565 #endif
 566
 567 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 568
 569 #define CONFIG_MMC      1
 570
 571 #ifdef CONFIG_MMC
 572 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 573 #define CONFIG_CMD_MMC
 574 #define CONFIG_DOS_PARTITION
 575 #define CONFIG_FSL_ESDHC
 576 #define CONFIG_GENERIC_MMC
 577 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 578 #ifdef CONFIG_P2020
 579 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
 580 #endif
 581 #endif
 582
 583 #define CONFIG_HAS_FSL_DR_USB
 584
 585 #if defined(CONFIG_HAS_FSL_DR_USB)
 586 #define CONFIG_USB_EHCI
 587
 588 #ifdef CONFIG_USB_EHCI
 589 #define CONFIG_CMD_USB
 590 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 591 #define CONFIG_USB_EHCI_FSL
 592 #define CONFIG_USB_STORAGE
 593 #endif
 594 #endif
 595
 596 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 597 #define CONFIG_CMD_EXT2
 598 #define CONFIG_CMD_FAT
 599 #define CONFIG_DOS_PARTITION
 600 #endif
 601
 602 /*
 603  * Miscellaneous configurable options
 604  */
 605 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 606 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 607 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 608 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 609 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 610 #if defined(CONFIG_CMD_KGDB)
 611 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 612 #else
 613 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 614 #endif
 615 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 616                                                 /* Print Buffer Size */
 617 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 618 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 619 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 620
 621 /*
 622  * For booting Linux, the board info and command line data
 623  * have to be in the first 64 MB of memory, since this is
 624  * the maximum mapped by the Linux kernel during initialization.
 625  */
 626 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)/* Initial Memory map for Linux*/
 627 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 628
 629 #if defined(CONFIG_CMD_KGDB)
 630 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 631 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 632 #endif
 633
 634 /*
 635  * Environment Configuration
 636  */
 637
 638 #if defined(CONFIG_TSEC_ENET)
 639 #define CONFIG_HAS_ETH0
 640 #define CONFIG_HAS_ETH1
 641 #define CONFIG_HAS_ETH2
 642 #endif
 643
 644 #define CONFIG_HOSTNAME         P2020RDB
 645 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 646 #define CONFIG_BOOTFILE         "uImage"
 647 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 648
 649 /* default location for tftp and bootm */
 650 #define CONFIG_LOADADDR         1000000
 651
 652 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 653 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 654
 655 #define CONFIG_BAUDRATE 115200
 656
 657 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 658         "netdev=eth0\0"                                         \
 659         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 660         "loadaddr=1000000\0"                    \
 661         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 662                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 663                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 664                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 665                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 666                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 667         "consoledev=ttyS0\0"                            \
 668         "ramdiskaddr=2000000\0"                 \
 669         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 670         "fdtaddr=c00000\0"                              \
 671         "fdtfile=p2020rdb.dtb\0"                \
 672         "bdev=sda1\0"   \
 673         "jffs2nor=mtdblock3\0"  \
 674         "norbootaddr=ef080000\0"        \
 675         "norfdtaddr=ef040000\0" \
 676         "jffs2nand=mtdblock9\0" \
 677         "nandbootaddr=100000\0" \
 678         "nandfdtaddr=80000\0"           \
 679         "nandimgsize=400000\0"          \
 680         "nandfdtsize=80000\0"           \
 681         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 682         "vscfw_addr=ef000000\0" \
 683         "othbootargs=ramdisk_size=600000\0" \
 684         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 685         "console=$consoledev,$baudrate $othbootargs; "  \
 686         "usb start;"                    \
 687         "fatload usb 0:2 $loadaddr $bootfile;"          \
 688         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 689         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 690         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 691         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 692         "console=$consoledev,$baudrate $othbootargs; "  \
 693         "usb start;"                    \
 694         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 695         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 696         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 697         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 698         "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
 699         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 700         "bootm $norbootaddr - $norfdtaddr\0"            \
 701         "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
 702         "console=$consoledev,$baudrate $othbootargs;"   \
 703         "nand read 2000000 $nandbootaddr $nandimgsize;" \
 704         "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
 705         "bootm 2000000 - 3000000;\0"
 706
 707 #define CONFIG_NFSBOOTCOMMAND           \
 708         "setenv bootargs root=/dev/nfs rw "     \
 709         "nfsroot=$serverip:$rootpath "          \
 710         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 711         "console=$consoledev,$baudrate $othbootargs;"   \
 712         "tftp $loadaddr $bootfile;"             \
 713         "tftp $fdtaddr $fdtfile;"               \
 714         "bootm $loadaddr - $fdtaddr"
 715
 716 #define CONFIG_HDBOOT                   \
 717         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 718         "console=$consoledev,$baudrate $othbootargs;"   \
 719         "usb start;"                    \
 720         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
 721         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 722         "bootm $loadaddr - $fdtaddr"
 723
 724 #define CONFIG_RAMBOOTCOMMAND           \
 725         "setenv bootargs root=/dev/ram rw "     \
 726         "console=$consoledev,$baudrate $othbootargs; "  \
 727         "tftp $ramdiskaddr $ramdiskfile;"       \
 728         "tftp $loadaddr $bootfile;"             \
 729         "tftp $fdtaddr $fdtfile;"               \
 730         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 731
 732 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 733
 734 #endif  /* __CONFIG_H */