include/configs/P1_P2_RDB.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P1 P2 RDB board configuration file
  25  * This file is intended to address a set of Low End and Ultra Low End
  26  * Freescale SOCs of QorIQ series(RDB platforms).
  27  * Currently only P2020RDB
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #ifdef CONFIG_P1011RDB
  34 #define CONFIG_P1011
  35 #endif
  36 #ifdef CONFIG_P1020RDB
  37 #define CONFIG_P1020
  38 #endif
  39 #ifdef CONFIG_P2010RDB
  40 #define CONFIG_P2010
  41 #endif
  42 #ifdef CONFIG_P2020RDB
  43 #define CONFIG_P2020
  44 #endif
  45
  46 #ifdef CONFIG_NAND
  47 #define CONFIG_NAND_U_BOOT              1
  48 #define CONFIG_RAMBOOT_NAND             1
  49 #ifdef CONFIG_NAND_SPL
  50 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  52 #else
  53 #define CONFIG_SYS_TEXT_BASE            0xf8f82000
  54 #endif /* CONFIG_NAND_SPL */
  55 #endif
  56
  57 #ifdef CONFIG_SDCARD
  58 #define CONFIG_RAMBOOT_SDCARD           1
  59 #define CONFIG_SYS_TEXT_BASE            0xf8f80000
  60 #endif
  61
  62 #ifdef CONFIG_SPIFLASH
  63 #define CONFIG_RAMBOOT_SPIFLASH         1
  64 #define CONFIG_SYS_TEXT_BASE            0xf8f80000
  65 #endif
  66
  67 #ifndef CONFIG_SYS_TEXT_BASE
  68 #define CONFIG_SYS_TEXT_BASE            0xeff80000
  69 #endif
  70
  71 #ifndef CONFIG_SYS_MONITOR_BASE
  72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  73 #endif
  74
  75 /* High Level Configuration Options */
  76 #define CONFIG_BOOKE            1       /* BOOKE */
  77 #define CONFIG_E500             1       /* BOOKE e500 family */
  78 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  79 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  80 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  81 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  82 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  83 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  84 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  85 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  86 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  87 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  88 #define CONFIG_ENV_OVERWRITE
  89
  90 #define CONFIG_E1000            1       /*  E1000 pci Ethernet card*/
  91 #ifndef __ASSEMBLY__
  92 extern unsigned long get_board_sys_clk(unsigned long dummy);
  93 #endif
  94 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1_P2 RDB */
  95 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
  96
  97 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
  98 #define CONFIG_MP
  99 #endif
 100
 101 #define CONFIG_HWCONFIG
 102
 103 /*
 104  * These can be toggled for performance analysis, otherwise use default.
 105  */
 106 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 107 #define CONFIG_BTB                      /* toggle branch predition */
 108
 109 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 110
 111 #define CONFIG_ENABLE_36BIT_PHYS        1
 112
 113 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
 114 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 115 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 116
 117  /*
 118   * Config the L2 Cache as L2 SRAM
 119   */
 120 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 121 #ifdef CONFIG_PHYS_64BIT
 122 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 123 #else
 124 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 125 #endif
 126 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 127 #define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 128
 129 /*
 130  * Base addresses -- Note these are effective addresses where the
 131  * actual resources get mapped (not physical addresses)
 132  */
 133 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 134 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of */
 135                                                         /* CCSRBAR */
 136 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
 137                                                         /* CONFIG_SYS_IMMR */
 138
 139 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
 140 #define CONFIG_SYS_CCSRBAR_DEFAULT      CONFIG_SYS_CCSRBAR
 141 #else
 142 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 143 #endif
 144
 145 /* DDR Setup */
 146 #define CONFIG_FSL_DDR2
 147 #undef CONFIG_FSL_DDR_INTERACTIVE
 148 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 149
 150 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 151
 152 #define CONFIG_SYS_SDRAM_SIZE   1024    /* DDR size on P1_P2 RDBs */
 153 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 154 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 155
 156 #define CONFIG_NUM_DDR_CONTROLLERS      1
 157 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 158 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 159
 160 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 161 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 162 #define CONFIG_SYS_DDR_SBE              0x00FF0000
 163
 164 /*
 165  * Memory map
 166  *
 167  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheablen
 168  * 0xa000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 169  * 0xffc2_0000  0xffc5_ffff     PCI IO range            256K non-cacheable
 170  *
 171  * Localbus cacheable (TBD)
 172  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 173  *
 174  * Localbus non-cacheable
 175  * 0xef00_0000  0xefff_ffff     FLASH                   16M non-cacheable
 176  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 177  * 0xffb0_0000  0xffbf_ffff     VSC7385 switch          1M non-cacheable
 178  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 179  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 180  */
 181
 182 /*
 183  * Local Bus Definitions
 184  */
 185 #define CONFIG_SYS_FLASH_BASE           0xef000000      /* start of FLASH 16M */
 186
 187 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 188
 189 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 190                                         BR_PS_16 | BR_V)
 191 #define CONFIG_FLASH_OR_PRELIM          0xff000ff7
 192
 193 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 194 #define CONFIG_SYS_FLASH_QUIET_TEST
 195 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 196
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 199 #undef  CONFIG_SYS_FLASH_CHECKSUM
 200 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 201 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 202
 203 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 204     defined(CONFIG_RAMBOOT_SPIFLASH)
 205 #define CONFIG_SYS_RAMBOOT
 206 #define CONFIG_SYS_EXTRA_ENV_RELOC
 207 #else
 208 #undef CONFIG_SYS_RAMBOOT
 209 #endif
 210
 211 #define CONFIG_FLASH_CFI_DRIVER
 212 #define CONFIG_SYS_FLASH_CFI
 213 #define CONFIG_SYS_FLASH_EMPTY_INFO
 214 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 215
 216 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 217 #define CONFIG_HWCONFIG
 218
 219 #define CONFIG_SYS_INIT_RAM_LOCK        1
 220 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000        /* stack in RAM */
 221 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 222
 223 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 224                                                 - GENERATED_GBL_DATA_SIZE)
 225 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 226
 227 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 228 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 229
 230 #ifndef CONFIG_NAND_SPL
 231 #define CONFIG_SYS_NAND_BASE            0xffa00000
 232 #else
 233 #define CONFIG_SYS_NAND_BASE            0xfff00000
 234 #endif
 235 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 236 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 237 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 238 #define NAND_MAX_CHIPS                  1
 239 #define CONFIG_MTD_NAND_VERIFY_WRITE
 240 #define CONFIG_CMD_NAND                 1
 241 #define CONFIG_NAND_FSL_ELBC            1
 242 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 243
 244 /* NAND boot: 4K NAND loader config */
 245 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 246 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 247 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 248 #define CONFIG_SYS_NAND_U_BOOT_START    (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 249 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 250 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 251 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP         ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 252
 253 /* NAND flash config */
 254 #define CONFIG_NAND_BR_PRELIM   (CONFIG_SYS_NAND_BASE_PHYS \
 255                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 256                                 | BR_PS_8       /* Port Size = 8 bit */ \
 257                                 | BR_MS_FCM             /* MSEL = FCM */ \
 258                                 | BR_V)                 /* valid */
 259
 260 #define CONFIG_NAND_OR_PRELIM   (0xFFF80000             /* length 32K */ \
 261                                 | OR_FCM_CSCT \
 262                                 | OR_FCM_CST \
 263                                 | OR_FCM_CHT \
 264                                 | OR_FCM_SCY_1 \
 265                                 | OR_FCM_TRLX \
 266                                 | OR_FCM_EHTR)
 267
 268 #ifdef CONFIG_RAMBOOT_NAND
 269 #define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 270 #define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 271 #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 272 #define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 273 #else
 274 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 275 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 276 #define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 277 #define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 278 #endif
 279
 280 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 281
 282 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 283
 284 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
 285 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 286                                 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 287                                 OR_GPCM_EHTR | OR_GPCM_EAD)
 288
 289 /* Serial Port - controlled on board with jumper J8
 290  * open - index 2
 291  * shorted - index 1
 292  */
 293 #define CONFIG_CONS_INDEX       1
 294 #define CONFIG_SYS_NS16550
 295 #define CONFIG_SYS_NS16550_SERIAL
 296 #define CONFIG_SYS_NS16550_REG_SIZE     1
 297 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 298 #ifdef CONFIG_NAND_SPL
 299 #define CONFIG_NS16550_MIN_FUNCTIONS
 300 #endif
 301
 302 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 303 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 304
 305 #define CONFIG_SYS_BAUDRATE_TABLE       \
 306         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 307
 308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 310
 311 /* Use the HUSH parser */
 312 #define CONFIG_SYS_HUSH_PARSER
 313 #ifdef  CONFIG_SYS_HUSH_PARSER
 314 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 315 #endif
 316
 317 /*
 318  * Pass open firmware flat tree
 319  */
 320 #define CONFIG_OF_LIBFDT                1
 321 #define CONFIG_OF_BOARD_SETUP           1
 322 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 323
 324 /* new uImage format support */
 325 #define CONFIG_FIT              1
 326 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 327
 328 /* I2C */
 329 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 330 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 331 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 332 #define CONFIG_I2C_MULTI_BUS
 333 #define CONFIG_I2C_CMD_TREE
 334 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address*/
 335 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 336 #define CONFIG_SYS_I2C_SLAVE            0x7F
 337 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}      /* Don't probe these addrs */
 338 #define CONFIG_SYS_I2C_OFFSET           0x3000
 339 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 340
 341 /*
 342  * I2C2 EEPROM
 343  */
 344 #define CONFIG_ID_EEPROM
 345 #ifdef CONFIG_ID_EEPROM
 346 #define CONFIG_SYS_I2C_EEPROM_NXID
 347 #endif
 348 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 349 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 350 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 351
 352 #define CONFIG_RTC_DS1337
 353 #define CONFIG_SYS_RTC_DS1337_NOOSC
 354 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 355 /*
 356  * General PCI
 357  * Memory space is mapped 1-1, but I/O space must start from 0.
 358  */
 359
 360 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 361 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 362 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 363 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 364 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 365 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 366 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 367 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 368 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 369 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 370
 371 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 372 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 373 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 374 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 375 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 376 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 377 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc30000
 378 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 379 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc30000
 380 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 381
 382 #if defined(CONFIG_PCI)
 383 #define CONFIG_NET_MULTI
 384 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 385
 386 #undef CONFIG_EEPRO100
 387 #undef CONFIG_TULIP
 388 #undef CONFIG_RTL8139
 389
 390 #ifdef CONFIG_RTL8139
 391 /* This macro is used by RTL8139 but not defined in PPC architecture */
 392 #define KSEG1ADDR(x)            (x)
 393 #define _IO_BASE        0x00000000
 394 #endif
 395
 396
 397 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 398 #define CONFIG_DOS_PARTITION
 399
 400 #endif  /* CONFIG_PCI */
 401
 402 #if defined(CONFIG_TSEC_ENET)
 403 #ifndef CONFIG_NET_MULTI
 404 #define CONFIG_NET_MULTI        1
 405 #endif
 406
 407 #define CONFIG_MII              1       /* MII PHY management */
 408 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 409 #define CONFIG_TSEC1    1
 410 #define CONFIG_TSEC1_NAME       "eTSEC1"
 411 #define CONFIG_TSEC2    1
 412 #define CONFIG_TSEC2_NAME       "eTSEC2"
 413 #define CONFIG_TSEC3    1
 414 #define CONFIG_TSEC3_NAME       "eTSEC3"
 415
 416 #define TSEC1_PHY_ADDR          2
 417 #define TSEC2_PHY_ADDR          0
 418 #define TSEC3_PHY_ADDR          1
 419
 420 #define CONFIG_VSC7385_ENET
 421
 422 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 423 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 424 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 425
 426 #define TSEC1_PHYIDX            0
 427 #define TSEC2_PHYIDX            0
 428 #define TSEC3_PHYIDX            0
 429
 430 /* Vitesse 7385 */
 431
 432 #ifdef CONFIG_VSC7385_ENET
 433 /* The size of the VSC7385 firmware image */
 434 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 435 #endif
 436
 437 #define CONFIG_ETHPRIME         "eTSEC1"
 438
 439 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 440
 441 #endif  /* CONFIG_TSEC_ENET */
 442
 443 /*
 444  * Environment
 445  */
 446 #if defined(CONFIG_SYS_RAMBOOT)
 447 #if defined(CONFIG_RAMBOOT_NAND)
 448         #define CONFIG_ENV_IS_IN_NAND   1
 449         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 450         #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 451 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 452         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 453         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 454         #define CONFIG_ENV_SIZE         0x2000
 455 #endif
 456 #else
 457         #define CONFIG_ENV_IS_IN_FLASH  1
 458         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 459         #define CONFIG_ENV_ADDR         0xfff80000
 460         #else
 461         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 462         #endif
 463         #define CONFIG_ENV_SIZE         0x2000
 464         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 465 #endif
 466
 467 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 468 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 469
 470 /*
 471  * Command line configuration.
 472  */
 473 #include <config_cmd_default.h>
 474
 475 #define CONFIG_CMD_DATE
 476 #define CONFIG_CMD_ELF
 477 #define CONFIG_CMD_I2C
 478 #define CONFIG_CMD_IRQ
 479 #define CONFIG_CMD_MII
 480 #define CONFIG_CMD_PING
 481 #define CONFIG_CMD_SETEXPR
 482 #define CONFIG_CMD_REGINFO
 483
 484 #if defined(CONFIG_PCI)
 485 #define CONFIG_CMD_NET
 486 #define CONFIG_CMD_PCI
 487 #endif
 488
 489 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 490
 491 #define CONFIG_MMC      1
 492
 493 #ifdef CONFIG_MMC
 494 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 495 #define CONFIG_CMD_MMC
 496 #define CONFIG_DOS_PARTITION
 497 #define CONFIG_FSL_ESDHC
 498 #define CONFIG_GENERIC_MMC
 499 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 500 #ifdef CONFIG_P2020
 501 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
 502 #endif
 503 #endif
 504
 505 #define CONFIG_USB_EHCI
 506
 507 #ifdef CONFIG_USB_EHCI
 508 #define CONFIG_CMD_USB
 509 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 510 #define CONFIG_USB_EHCI_FSL
 511 #define CONFIG_USB_STORAGE
 512 #endif
 513
 514 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 515 #define CONFIG_CMD_EXT2
 516 #define CONFIG_CMD_FAT
 517 #define CONFIG_DOS_PARTITION
 518 #endif
 519
 520 /*
 521  * Miscellaneous configurable options
 522  */
 523 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 524 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 525 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 526 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 527 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 528 #if defined(CONFIG_CMD_KGDB)
 529 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 530 #else
 531 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 532 #endif
 533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 534                                                 /* Print Buffer Size */
 535 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 536 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 537 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 538
 539 /*
 540  * For booting Linux, the board info and command line data
 541  * have to be in the first 16 MB of memory, since this is
 542  * the maximum mapped by the Linux kernel during initialization.
 543  */
 544 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)/* Initial Memory map for Linux*/
 545 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 546
 547 #if defined(CONFIG_CMD_KGDB)
 548 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 549 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 550 #endif
 551
 552 /*
 553  * Environment Configuration
 554  */
 555
 556 #if defined(CONFIG_TSEC_ENET)
 557 #define CONFIG_HAS_ETH0
 558 #define CONFIG_HAS_ETH1
 559 #define CONFIG_HAS_ETH2
 560 #endif
 561
 562 #define CONFIG_HOSTNAME         P2020RDB
 563 #define CONFIG_ROOTPATH         /opt/nfsroot
 564 #define CONFIG_BOOTFILE         uImage
 565 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 566
 567 /* default location for tftp and bootm */
 568 #define CONFIG_LOADADDR         1000000
 569
 570 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 571 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 572
 573 #define CONFIG_BAUDRATE 115200
 574
 575 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 576         "netdev=eth0\0"                                         \
 577         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 578         "loadaddr=1000000\0"                    \
 579         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 580                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 581                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 582                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 583                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 584                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 585         "consoledev=ttyS0\0"                            \
 586         "ramdiskaddr=2000000\0"                 \
 587         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 588         "fdtaddr=c00000\0"                              \
 589         "fdtfile=p2020rdb.dtb\0"                \
 590         "bdev=sda1\0"   \
 591         "jffs2nor=mtdblock3\0"  \
 592         "norbootaddr=ef080000\0"        \
 593         "norfdtaddr=ef040000\0" \
 594         "jffs2nand=mtdblock9\0" \
 595         "nandbootaddr=100000\0" \
 596         "nandfdtaddr=80000\0"           \
 597         "nandimgsize=400000\0"          \
 598         "nandfdtsize=80000\0"           \
 599         "usb_phy_type=ulpi\0"           \
 600         "vscfw_addr=ef000000\0" \
 601         "othbootargs=ramdisk_size=600000\0" \
 602         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 603         "console=$consoledev,$baudrate $othbootargs; "  \
 604         "usb start;"                    \
 605         "fatload usb 0:2 $loadaddr $bootfile;"          \
 606         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 607         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 608         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 609         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 610         "console=$consoledev,$baudrate $othbootargs; "  \
 611         "usb start;"                    \
 612         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 613         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 614         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 615         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 616         "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
 617         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 618         "bootm $norbootaddr - $norfdtaddr\0"            \
 619         "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
 620         "console=$consoledev,$baudrate $othbootargs;"   \
 621         "nand read 2000000 $nandbootaddr $nandimgsize;" \
 622         "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
 623         "bootm 2000000 - 3000000;\0"
 624
 625 #define CONFIG_NFSBOOTCOMMAND           \
 626         "setenv bootargs root=/dev/nfs rw "     \
 627         "nfsroot=$serverip:$rootpath "          \
 628         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 629         "console=$consoledev,$baudrate $othbootargs;"   \
 630         "tftp $loadaddr $bootfile;"             \
 631         "tftp $fdtaddr $fdtfile;"               \
 632         "bootm $loadaddr - $fdtaddr"
 633
 634 #define CONFIG_HDBOOT                   \
 635         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 636         "console=$consoledev,$baudrate $othbootargs;"   \
 637         "usb start;"                    \
 638         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
 639         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 640         "bootm $loadaddr - $fdtaddr"
 641
 642 #define CONFIG_RAMBOOTCOMMAND           \
 643         "setenv bootargs root=/dev/ram rw "     \
 644         "console=$consoledev,$baudrate $othbootargs; "  \
 645         "tftp $ramdiskaddr $ramdiskfile;"       \
 646         "tftp $loadaddr $bootfile;"             \
 647         "tftp $fdtaddr $fdtfile;"               \
 648         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 649
 650 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 651
 652 #endif  /* __CONFIG_H */