include/configs/P1_P2_RDB.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P1 P2 RDB board configuration file
  25  * This file is intended to address a set of Low End and Ultra Low End
  26  * Freescale SOCs of QorIQ series(RDB platforms).
  27  * Currently only P2020RDB
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #ifdef CONFIG_P1011RDB
  34 #define CONFIG_P1011
  35 #endif
  36 #ifdef CONFIG_P1020RDB
  37 #define CONFIG_P1020
  38 #endif
  39 #ifdef CONFIG_P2010RDB
  40 #define CONFIG_P2010
  41 #endif
  42 #ifdef CONFIG_P2020RDB
  43 #define CONFIG_P2020
  44 #endif
  45
  46 #ifdef CONFIG_NAND
  47 #define CONFIG_NAND_U_BOOT              1
  48 #define CONFIG_RAMBOOT_NAND             1
  49 #ifdef CONFIG_NAND_SPL
  50 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  52 #else
  53 #define CONFIG_SYS_TEXT_BASE            0xf8f82000
  54 #endif /* CONFIG_NAND_SPL */
  55 #endif
  56
  57 #ifdef CONFIG_SDCARD
  58 #define CONFIG_RAMBOOT_SDCARD           1
  59 #define CONFIG_SYS_TEXT_BASE            0xf8f80000
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  61 #endif
  62
  63 #ifdef CONFIG_SPIFLASH
  64 #define CONFIG_RAMBOOT_SPIFLASH         1
  65 #define CONFIG_SYS_TEXT_BASE            0xf8f80000
  66 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  67 #endif
  68
  69 #ifndef CONFIG_SYS_TEXT_BASE
  70 #define CONFIG_SYS_TEXT_BASE            0xeff80000
  71 #endif
  72
  73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  74 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  75 #endif
  76
  77 #ifndef CONFIG_SYS_MONITOR_BASE
  78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  79 #endif
  80
  81 /* High Level Configuration Options */
  82 #define CONFIG_BOOKE            1       /* BOOKE */
  83 #define CONFIG_E500             1       /* BOOKE e500 family */
  84 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  85 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  86
  87 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  88 #if defined(CONFIG_PCI)
  89 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  90 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  91 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  92 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  93 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  94 #endif /* #if defined(CONFIG_PCI) */
  95 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  96 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  97 #define CONFIG_ENV_OVERWRITE
  98
  99 #if defined(CONFIG_PCI)
 100 #define CONFIG_E1000            1       /*  E1000 pci Ethernet card*/
 101 #endif
 102
 103 #ifndef __ASSEMBLY__
 104 extern unsigned long get_board_sys_clk(unsigned long dummy);
 105 #endif
 106 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1_P2 RDB */
 107 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
 108
 109 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
 110 #define CONFIG_MP
 111 #endif
 112
 113 #define CONFIG_HWCONFIG
 114
 115 /*
 116  * These can be toggled for performance analysis, otherwise use default.
 117  */
 118 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 119 #define CONFIG_BTB                      /* toggle branch predition */
 120
 121 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 122
 123 #define CONFIG_ENABLE_36BIT_PHYS        1
 124
 125 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
 126 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 127 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 128
 129  /*
 130   * Config the L2 Cache as L2 SRAM
 131   */
 132 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 135 #else
 136 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 137 #endif
 138 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 139 #define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 140
 141 /*
 142  * Base addresses -- Note these are effective addresses where the
 143  * actual resources get mapped (not physical addresses)
 144  */
 145 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 146 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of */
 147                                                         /* CCSRBAR */
 148 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
 149                                                         /* CONFIG_SYS_IMMR */
 150
 151 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
 152 #define CONFIG_SYS_CCSRBAR_DEFAULT      CONFIG_SYS_CCSRBAR
 153 #else
 154 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 155 #endif
 156
 157 /* DDR Setup */
 158 #define CONFIG_FSL_DDR2
 159 #undef CONFIG_FSL_DDR_INTERACTIVE
 160 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 161
 162 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 163
 164 #define CONFIG_SYS_SDRAM_SIZE   1024    /* DDR size on P1_P2 RDBs */
 165 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 166 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 167
 168 #define CONFIG_NUM_DDR_CONTROLLERS      1
 169 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 170 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 171
 172 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 173 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 174 #define CONFIG_SYS_DDR_SBE              0x00FF0000
 175
 176 /*
 177  * Memory map
 178  *
 179  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheablen
 180  * 0xa000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 181  * 0xffc2_0000  0xffc5_ffff     PCI IO range            256K non-cacheable
 182  *
 183  * Localbus cacheable (TBD)
 184  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 185  *
 186  * Localbus non-cacheable
 187  * 0xef00_0000  0xefff_ffff     FLASH                   16M non-cacheable
 188  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 189  * 0xffb0_0000  0xffbf_ffff     VSC7385 switch          1M non-cacheable
 190  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 191  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 192  */
 193
 194 /*
 195  * Local Bus Definitions
 196  */
 197 #define CONFIG_SYS_FLASH_BASE           0xef000000      /* start of FLASH 16M */
 198
 199 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 200
 201 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 202                                         BR_PS_16 | BR_V)
 203 #define CONFIG_FLASH_OR_PRELIM          0xff000ff7
 204
 205 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 206 #define CONFIG_SYS_FLASH_QUIET_TEST
 207 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 208
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 210 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 211 #undef  CONFIG_SYS_FLASH_CHECKSUM
 212 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 213 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 214
 215 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 216     defined(CONFIG_RAMBOOT_SPIFLASH)
 217 #define CONFIG_SYS_RAMBOOT
 218 #define CONFIG_SYS_EXTRA_ENV_RELOC
 219 #else
 220 #undef CONFIG_SYS_RAMBOOT
 221 #endif
 222
 223 #define CONFIG_FLASH_CFI_DRIVER
 224 #define CONFIG_SYS_FLASH_CFI
 225 #define CONFIG_SYS_FLASH_EMPTY_INFO
 226 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 227
 228 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 229 #define CONFIG_HWCONFIG
 230
 231 #define CONFIG_SYS_INIT_RAM_LOCK        1
 232 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000        /* stack in RAM */
 233 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 234
 235 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 236                                                 - GENERATED_GBL_DATA_SIZE)
 237 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 238
 239 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 240 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 241
 242 #ifndef CONFIG_NAND_SPL
 243 #define CONFIG_SYS_NAND_BASE            0xffa00000
 244 #else
 245 #define CONFIG_SYS_NAND_BASE            0xfff00000
 246 #endif
 247 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 248 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 249 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 250 #define NAND_MAX_CHIPS                  1
 251 #define CONFIG_MTD_NAND_VERIFY_WRITE
 252 #define CONFIG_CMD_NAND                 1
 253 #define CONFIG_NAND_FSL_ELBC            1
 254 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 255
 256 /* NAND boot: 4K NAND loader config */
 257 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 258 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 259 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 260 #define CONFIG_SYS_NAND_U_BOOT_START    (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 261 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 262 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 263 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP         ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 264
 265 /* NAND flash config */
 266 #define CONFIG_NAND_BR_PRELIM   (CONFIG_SYS_NAND_BASE_PHYS \
 267                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 268                                 | BR_PS_8       /* Port Size = 8 bit */ \
 269                                 | BR_MS_FCM             /* MSEL = FCM */ \
 270                                 | BR_V)                 /* valid */
 271
 272 #define CONFIG_NAND_OR_PRELIM   (0xFFF80000             /* length 32K */ \
 273                                 | OR_FCM_CSCT \
 274                                 | OR_FCM_CST \
 275                                 | OR_FCM_CHT \
 276                                 | OR_FCM_SCY_1 \
 277                                 | OR_FCM_TRLX \
 278                                 | OR_FCM_EHTR)
 279
 280 #ifdef CONFIG_RAMBOOT_NAND
 281 #define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 282 #define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 283 #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 284 #define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 285 #else
 286 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 287 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 288 #define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 289 #define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 290 #endif
 291
 292 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 293
 294 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 295
 296 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
 297 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 298                                 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 299                                 OR_GPCM_EHTR | OR_GPCM_EAD)
 300
 301 /* Serial Port - controlled on board with jumper J8
 302  * open - index 2
 303  * shorted - index 1
 304  */
 305 #define CONFIG_CONS_INDEX       1
 306 #define CONFIG_SYS_NS16550
 307 #define CONFIG_SYS_NS16550_SERIAL
 308 #define CONFIG_SYS_NS16550_REG_SIZE     1
 309 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 310 #ifdef CONFIG_NAND_SPL
 311 #define CONFIG_NS16550_MIN_FUNCTIONS
 312 #endif
 313
 314 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 315 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 316
 317 #define CONFIG_SYS_BAUDRATE_TABLE       \
 318         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 319
 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 322
 323 /* Use the HUSH parser */
 324 #define CONFIG_SYS_HUSH_PARSER
 325 #ifdef  CONFIG_SYS_HUSH_PARSER
 326 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 327 #endif
 328
 329 /*
 330  * Pass open firmware flat tree
 331  */
 332 #define CONFIG_OF_LIBFDT                1
 333 #define CONFIG_OF_BOARD_SETUP           1
 334 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 335
 336 /* new uImage format support */
 337 #define CONFIG_FIT              1
 338 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 339
 340 /* I2C */
 341 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 342 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 343 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 344 #define CONFIG_I2C_MULTI_BUS
 345 #define CONFIG_I2C_CMD_TREE
 346 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address*/
 347 #define CONFIG_SYS_I2C_SLAVE            0x7F
 348 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}      /* Don't probe these addrs */
 349 #define CONFIG_SYS_I2C_OFFSET           0x3000
 350 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 351
 352 /*
 353  * I2C2 EEPROM
 354  */
 355 #define CONFIG_ID_EEPROM
 356 #ifdef CONFIG_ID_EEPROM
 357 #define CONFIG_SYS_I2C_EEPROM_NXID
 358 #endif
 359 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 360 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 361 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 362
 363 #define CONFIG_RTC_DS1337
 364 #define CONFIG_SYS_RTC_DS1337_NOOSC
 365 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 366 /*
 367  * General PCI
 368  * Memory space is mapped 1-1, but I/O space must start from 0.
 369  */
 370
 371 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 372 #if defined(CONFIG_PCI)
 373 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 374 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 375 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 376 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 377 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 378 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 379 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 380 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 381 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 382
 383 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 384 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 385 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 386 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 387 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 388 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 389 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc30000
 390 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 391 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc30000
 392 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 393
 394 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 395
 396 #undef CONFIG_EEPRO100
 397 #undef CONFIG_TULIP
 398 #undef CONFIG_RTL8139
 399
 400 #ifdef CONFIG_RTL8139
 401 /* This macro is used by RTL8139 but not defined in PPC architecture */
 402 #define KSEG1ADDR(x)            (x)
 403 #define _IO_BASE        0x00000000
 404 #endif
 405
 406
 407 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 408 #define CONFIG_DOS_PARTITION
 409
 410 #endif  /* CONFIG_PCI */
 411
 412 #define CONFIG_NET_MULTI        1
 413
 414 #if defined(CONFIG_TSEC_ENET)
 415 #define CONFIG_MII              1       /* MII PHY management */
 416 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 417 #define CONFIG_TSEC1    1
 418 #define CONFIG_TSEC1_NAME       "eTSEC1"
 419 #define CONFIG_TSEC2    1
 420 #define CONFIG_TSEC2_NAME       "eTSEC2"
 421 #define CONFIG_TSEC3    1
 422 #define CONFIG_TSEC3_NAME       "eTSEC3"
 423
 424 #define TSEC1_PHY_ADDR          2
 425 #define TSEC2_PHY_ADDR          0
 426 #define TSEC3_PHY_ADDR          1
 427
 428 #define CONFIG_VSC7385_ENET
 429
 430 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 431 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 432 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 433
 434 #define TSEC1_PHYIDX            0
 435 #define TSEC2_PHYIDX            0
 436 #define TSEC3_PHYIDX            0
 437
 438 /* Vitesse 7385 */
 439
 440 #ifdef CONFIG_VSC7385_ENET
 441 /* The size of the VSC7385 firmware image */
 442 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 443 #endif
 444
 445 #define CONFIG_ETHPRIME         "eTSEC1"
 446
 447 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 448
 449 #endif  /* CONFIG_TSEC_ENET */
 450
 451 /*
 452  * Environment
 453  */
 454 #if defined(CONFIG_SYS_RAMBOOT)
 455 #if defined(CONFIG_RAMBOOT_NAND)
 456         #define CONFIG_ENV_IS_IN_NAND   1
 457         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 458         #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 459 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 460         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 461         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 462         #define CONFIG_ENV_SIZE         0x2000
 463 #endif
 464 #else
 465         #define CONFIG_ENV_IS_IN_FLASH  1
 466         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 467         #define CONFIG_ENV_ADDR         0xfff80000
 468         #else
 469         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 470         #endif
 471         #define CONFIG_ENV_SIZE         0x2000
 472         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 473 #endif
 474
 475 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 476 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 477
 478 /*
 479  * Command line configuration.
 480  */
 481 #include <config_cmd_default.h>
 482
 483 #define CONFIG_CMD_DATE
 484 #define CONFIG_CMD_ELF
 485 #define CONFIG_CMD_I2C
 486 #define CONFIG_CMD_IRQ
 487 #define CONFIG_CMD_MII
 488 #define CONFIG_CMD_PING
 489 #define CONFIG_CMD_SETEXPR
 490 #define CONFIG_CMD_REGINFO
 491
 492 #if defined(CONFIG_PCI)
 493 #define CONFIG_CMD_NET
 494 #define CONFIG_CMD_PCI
 495 #endif
 496
 497 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 498
 499 #define CONFIG_MMC      1
 500
 501 #ifdef CONFIG_MMC
 502 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 503 #define CONFIG_CMD_MMC
 504 #define CONFIG_DOS_PARTITION
 505 #define CONFIG_FSL_ESDHC
 506 #define CONFIG_GENERIC_MMC
 507 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 508 #ifdef CONFIG_P2020
 509 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
 510 #endif
 511 #endif
 512
 513 #define CONFIG_USB_EHCI
 514
 515 #ifdef CONFIG_USB_EHCI
 516 #define CONFIG_CMD_USB
 517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 518 #define CONFIG_USB_EHCI_FSL
 519 #define CONFIG_USB_STORAGE
 520 #endif
 521
 522 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 523 #define CONFIG_CMD_EXT2
 524 #define CONFIG_CMD_FAT
 525 #define CONFIG_DOS_PARTITION
 526 #endif
 527
 528 /*
 529  * Miscellaneous configurable options
 530  */
 531 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 532 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 533 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 534 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 535 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 536 #if defined(CONFIG_CMD_KGDB)
 537 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 538 #else
 539 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 540 #endif
 541 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 542                                                 /* Print Buffer Size */
 543 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 544 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 545 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 546
 547 /*
 548  * For booting Linux, the board info and command line data
 549  * have to be in the first 16 MB of memory, since this is
 550  * the maximum mapped by the Linux kernel during initialization.
 551  */
 552 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)/* Initial Memory map for Linux*/
 553 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 554
 555 #if defined(CONFIG_CMD_KGDB)
 556 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 557 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 558 #endif
 559
 560 /*
 561  * Environment Configuration
 562  */
 563
 564 #if defined(CONFIG_TSEC_ENET)
 565 #define CONFIG_HAS_ETH0
 566 #define CONFIG_HAS_ETH1
 567 #define CONFIG_HAS_ETH2
 568 #endif
 569
 570 #define CONFIG_HOSTNAME         P2020RDB
 571 #define CONFIG_ROOTPATH         /opt/nfsroot
 572 #define CONFIG_BOOTFILE         uImage
 573 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 574
 575 /* default location for tftp and bootm */
 576 #define CONFIG_LOADADDR         1000000
 577
 578 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 579 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 580
 581 #define CONFIG_BAUDRATE 115200
 582
 583 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 584         "netdev=eth0\0"                                         \
 585         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 586         "loadaddr=1000000\0"                    \
 587         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 588                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 589                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 590                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 591                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 592                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 593         "consoledev=ttyS0\0"                            \
 594         "ramdiskaddr=2000000\0"                 \
 595         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 596         "fdtaddr=c00000\0"                              \
 597         "fdtfile=p2020rdb.dtb\0"                \
 598         "bdev=sda1\0"   \
 599         "jffs2nor=mtdblock3\0"  \
 600         "norbootaddr=ef080000\0"        \
 601         "norfdtaddr=ef040000\0" \
 602         "jffs2nand=mtdblock9\0" \
 603         "nandbootaddr=100000\0" \
 604         "nandfdtaddr=80000\0"           \
 605         "nandimgsize=400000\0"          \
 606         "nandfdtsize=80000\0"           \
 607         "usb_phy_type=ulpi\0"           \
 608         "vscfw_addr=ef000000\0" \
 609         "othbootargs=ramdisk_size=600000\0" \
 610         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 611         "console=$consoledev,$baudrate $othbootargs; "  \
 612         "usb start;"                    \
 613         "fatload usb 0:2 $loadaddr $bootfile;"          \
 614         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 615         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 616         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 617         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 618         "console=$consoledev,$baudrate $othbootargs; "  \
 619         "usb start;"                    \
 620         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 621         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 622         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 623         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 624         "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
 625         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 626         "bootm $norbootaddr - $norfdtaddr\0"            \
 627         "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
 628         "console=$consoledev,$baudrate $othbootargs;"   \
 629         "nand read 2000000 $nandbootaddr $nandimgsize;" \
 630         "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
 631         "bootm 2000000 - 3000000;\0"
 632
 633 #define CONFIG_NFSBOOTCOMMAND           \
 634         "setenv bootargs root=/dev/nfs rw "     \
 635         "nfsroot=$serverip:$rootpath "          \
 636         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 637         "console=$consoledev,$baudrate $othbootargs;"   \
 638         "tftp $loadaddr $bootfile;"             \
 639         "tftp $fdtaddr $fdtfile;"               \
 640         "bootm $loadaddr - $fdtaddr"
 641
 642 #define CONFIG_HDBOOT                   \
 643         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 644         "console=$consoledev,$baudrate $othbootargs;"   \
 645         "usb start;"                    \
 646         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
 647         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 648         "bootm $loadaddr - $fdtaddr"
 649
 650 #define CONFIG_RAMBOOTCOMMAND           \
 651         "setenv bootargs root=/dev/ram rw "     \
 652         "console=$consoledev,$baudrate $othbootargs; "  \
 653         "tftp $ramdiskaddr $ramdiskfile;"       \
 654         "tftp $loadaddr $bootfile;"             \
 655         "tftp $fdtaddr $fdtfile;"               \
 656         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 657
 658 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 659
 660 #endif  /* __CONFIG_H */