include/configs/P1_P2_RDB.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P1 P2 RDB board configuration file
   9  * This file is intended to address a set of Low End and Ultra Low End
  10  * Freescale SOCs of QorIQ series(RDB platforms).
  11  * Currently only P2020RDB
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #ifdef CONFIG_36BIT
  18 #define CONFIG_PHYS_64BIT
  19 #endif
  20
  21 #ifdef CONFIG_P1011RDB
  22 #define CONFIG_P1011
  23 #endif
  24 #ifdef CONFIG_P1020RDB
  25 #define CONFIG_P1020
  26 #endif
  27 #ifdef CONFIG_P2010RDB
  28 #define CONFIG_P2010
  29 #endif
  30 #ifdef CONFIG_P2020RDB
  31 #define CONFIG_P2020
  32 #endif
  33
  34 #ifdef CONFIG_NAND
  35 #define CONFIG_NAND_U_BOOT              1
  36 #define CONFIG_RAMBOOT_NAND             1
  37 #ifdef CONFIG_NAND_SPL
  38 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  40 #else
  41 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  42 #define CONFIG_SYS_TEXT_BASE            0xf8f82000
  43 #endif /* CONFIG_NAND_SPL */
  44 #endif
  45
  46 #ifdef CONFIG_SDCARD
  47 #define CONFIG_RAMBOOT_SDCARD           1
  48 #define CONFIG_SYS_TEXT_BASE            0x11000000
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  50 #endif
  51
  52 #ifdef CONFIG_SPIFLASH
  53 #define CONFIG_RAMBOOT_SPIFLASH         1
  54 #define CONFIG_SYS_TEXT_BASE            0x11000000
  55 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  56 #endif
  57
  58 #ifndef CONFIG_SYS_TEXT_BASE
  59 #define CONFIG_SYS_TEXT_BASE            0xeff80000
  60 #endif
  61
  62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  63 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  64 #endif
  65
  66 #ifndef CONFIG_SYS_MONITOR_BASE
  67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  68 #endif
  69
  70 /* High Level Configuration Options */
  71 #define CONFIG_BOOKE            1       /* BOOKE */
  72 #define CONFIG_E500             1       /* BOOKE e500 family */
  73 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  74 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  75
  76 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  77 #if defined(CONFIG_PCI)
  78 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  79 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  80 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  81 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  82 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  83 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  84 #endif /* #if defined(CONFIG_PCI) */
  85 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  86 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  87 #define CONFIG_ENV_OVERWRITE
  88
  89 #if defined(CONFIG_PCI)
  90 #define CONFIG_E1000            1       /*  E1000 pci Ethernet card*/
  91 #endif
  92
  93 #ifndef __ASSEMBLY__
  94 extern unsigned long get_board_sys_clk(unsigned long dummy);
  95 #endif
  96 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1_P2 RDB */
  97 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
  98
  99 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
 100 #define CONFIG_MP
 101 #endif
 102
 103 #define CONFIG_HWCONFIG
 104
 105 /*
 106  * These can be toggled for performance analysis, otherwise use default.
 107  */
 108 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 109 #define CONFIG_BTB                      /* toggle branch predition */
 110
 111 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 112
 113 #define CONFIG_ENABLE_36BIT_PHYS        1
 114
 115 #ifdef CONFIG_PHYS_64BIT
 116 #define CONFIG_ADDR_MAP                 1
 117 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 118 #endif
 119
 120 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
 121 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 122 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 123
 124  /*
 125   * Config the L2 Cache as L2 SRAM
 126   */
 127 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 128 #ifdef CONFIG_PHYS_64BIT
 129 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 130 #else
 131 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 132 #endif
 133 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 134 #define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 135
 136 #define CONFIG_SYS_CCSRBAR              0xffe00000
 137 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 138
 139 #if defined(CONFIG_NAND_SPL)
 140 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 141 #endif
 142
 143 /* DDR Setup */
 144 #define CONFIG_SYS_FSL_DDR2
 145 #undef CONFIG_FSL_DDR_INTERACTIVE
 146 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 147
 148 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 149
 150 #define CONFIG_SYS_SDRAM_SIZE   1024    /* DDR size on P1_P2 RDBs */
 151 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 152 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 153
 154 #define CONFIG_NUM_DDR_CONTROLLERS      1
 155 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 156 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 157
 158 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 159 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 160 #define CONFIG_SYS_DDR_SBE              0x00FF0000
 161
 162 /*
 163  * Memory map
 164  *
 165  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheablen
 166  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 167  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 168  *
 169  * Localbus cacheable (TBD)
 170  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 171  *
 172  * Localbus non-cacheable
 173  * 0xef00_0000  0xefff_ffff     FLASH                   16M non-cacheable
 174  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 175  * 0xffb0_0000  0xffbf_ffff     VSC7385 switch          1M non-cacheable
 176  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 177  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 178  */
 179
 180 /*
 181  * Local Bus Definitions
 182  */
 183 #define CONFIG_SYS_FLASH_BASE           0xef000000      /* start of FLASH 16M */
 184
 185 #ifdef CONFIG_PHYS_64BIT
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfef000000ull
 187 #else
 188 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 189 #endif
 190
 191 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 192                                         BR_PS_16 | BR_V)
 193 #define CONFIG_FLASH_OR_PRELIM          0xff000ff7
 194
 195 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 196 #define CONFIG_SYS_FLASH_QUIET_TEST
 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 201 #undef  CONFIG_SYS_FLASH_CHECKSUM
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 203 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 204
 205 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 206     defined(CONFIG_RAMBOOT_SPIFLASH)
 207 #define CONFIG_SYS_RAMBOOT
 208 #define CONFIG_SYS_EXTRA_ENV_RELOC
 209 #else
 210 #undef CONFIG_SYS_RAMBOOT
 211 #endif
 212
 213 #define CONFIG_FLASH_CFI_DRIVER
 214 #define CONFIG_SYS_FLASH_CFI
 215 #define CONFIG_SYS_FLASH_EMPTY_INFO
 216 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 217
 218 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 219 #define CONFIG_MISC_INIT_R
 220 #define CONFIG_HWCONFIG
 221
 222 #define CONFIG_SYS_INIT_RAM_LOCK        1
 223 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000        /* stack in RAM */
 224 #ifdef CONFIG_PHYS_64BIT
 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 227 /* The assembler doesn't like typecast */
 228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 229         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 230           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 231 #else
 232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 235 #endif
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 237
 238 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 239                                                 - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241
 242 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 243 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 244
 245 #ifndef CONFIG_NAND_SPL
 246 #define CONFIG_SYS_NAND_BASE            0xffa00000
 247 #ifdef CONFIG_PHYS_64BIT
 248 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 249 #else
 250 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 251 #endif
 252 #else
 253 #define CONFIG_SYS_NAND_BASE            0xfff00000
 254 #ifdef CONFIG_PHYS_64BIT
 255 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 256 #else
 257 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 258 #endif
 259 #endif
 260
 261 #define CONFIG_CMD_NAND
 262 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 263 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 264 #define CONFIG_MTD_NAND_VERIFY_WRITE
 265 #define CONFIG_NAND_FSL_ELBC            1
 266 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 267
 268 /* NAND boot: 4K NAND loader config */
 269 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 270 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 271 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 272 #define CONFIG_SYS_NAND_U_BOOT_START    (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 273 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 274 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 275 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP         ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 276
 277 /* NAND flash config */
 278 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 279                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 280                                 | BR_PS_8       /* Port Size = 8 bit */ \
 281                                 | BR_MS_FCM             /* MSEL = FCM */ \
 282                                 | BR_V)                 /* valid */
 283
 284 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFF80000     /* length 32K */ \
 285                                 | OR_FCM_CSCT \
 286                                 | OR_FCM_CST \
 287                                 | OR_FCM_CHT \
 288                                 | OR_FCM_SCY_1 \
 289                                 | OR_FCM_TRLX \
 290                                 | OR_FCM_EHTR)
 291
 292 #ifdef CONFIG_RAMBOOT_NAND
 293 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 294 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 295 #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 296 #define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 297 #else
 298 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 299 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 300 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 301 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 302 #endif
 303
 304 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 305
 306 #ifdef CONFIG_PHYS_64BIT
 307 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 308 #else
 309 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 310 #endif
 311
 312 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
 313                                                         | BR_PS_8 | BR_V)
 314 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 315                                 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 316                                 OR_GPCM_EHTR | OR_GPCM_EAD)
 317
 318 /* Serial Port - controlled on board with jumper J8
 319  * open - index 2
 320  * shorted - index 1
 321  */
 322 #define CONFIG_CONS_INDEX       1
 323 #define CONFIG_SYS_NS16550
 324 #define CONFIG_SYS_NS16550_SERIAL
 325 #define CONFIG_SYS_NS16550_REG_SIZE     1
 326 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 327 #ifdef CONFIG_NAND_SPL
 328 #define CONFIG_NS16550_MIN_FUNCTIONS
 329 #endif
 330
 331 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 332
 333 #define CONFIG_SYS_BAUDRATE_TABLE       \
 334         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 335
 336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 338
 339 /* Use the HUSH parser */
 340 #define CONFIG_SYS_HUSH_PARSER
 341
 342 /*
 343  * Pass open firmware flat tree
 344  */
 345 #define CONFIG_OF_LIBFDT                1
 346 #define CONFIG_OF_BOARD_SETUP           1
 347 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 348
 349 /* new uImage format support */
 350 #define CONFIG_FIT              1
 351 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 352
 353 /* I2C */
 354 #define CONFIG_SYS_I2C
 355 #define CONFIG_SYS_I2C_FSL
 356 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 357 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 358 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 359 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 360 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 361 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 362 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 363
 364 /*
 365  * I2C2 EEPROM
 366  */
 367 #define CONFIG_ID_EEPROM
 368 #ifdef CONFIG_ID_EEPROM
 369 #define CONFIG_SYS_I2C_EEPROM_NXID
 370 #endif
 371 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 372 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 373 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 374
 375 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 376
 377 #define CONFIG_RTC_DS1337
 378 #define CONFIG_SYS_RTC_DS1337_NOOSC
 379 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 380
 381 /* eSPI - Enhanced SPI */
 382 #define CONFIG_FSL_ESPI
 383 #define CONFIG_SPI_FLASH
 384 #define CONFIG_SPI_FLASH_SPANSION
 385 #define CONFIG_CMD_SF
 386 #define CONFIG_SF_DEFAULT_SPEED         10000000
 387 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 388
 389 /*
 390  * General PCI
 391  * Memory space is mapped 1-1, but I/O space must start from 0.
 392  */
 393
 394 #if defined(CONFIG_PCI)
 395 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 396 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 397 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 398 #ifdef CONFIG_PHYS_64BIT
 399 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 400 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 401 #else
 402 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 403 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 404 #endif
 405 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 406 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 407 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 408 #ifdef CONFIG_PHYS_64BIT
 409 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 410 #else
 411 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 412 #endif
 413 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 414
 415 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 416 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 417 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 418 #ifdef CONFIG_PHYS_64BIT
 419 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 420 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 421 #else
 422 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 423 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 424 #endif
 425 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 426 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 427 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 428 #ifdef CONFIG_PHYS_64BIT
 429 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 430 #else
 431 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 432 #endif
 433 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 434
 435 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 436
 437 #undef CONFIG_EEPRO100
 438 #undef CONFIG_TULIP
 439 #undef CONFIG_RTL8139
 440
 441 #ifdef CONFIG_RTL8139
 442 /* This macro is used by RTL8139 but not defined in PPC architecture */
 443 #define KSEG1ADDR(x)            (x)
 444 #define _IO_BASE        0x00000000
 445 #endif
 446
 447
 448 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 449 #define CONFIG_DOS_PARTITION
 450
 451 #endif  /* CONFIG_PCI */
 452
 453
 454 #if defined(CONFIG_TSEC_ENET)
 455 #define CONFIG_MII              1       /* MII PHY management */
 456 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 457 #define CONFIG_TSEC1    1
 458 #define CONFIG_TSEC1_NAME       "eTSEC1"
 459 #define CONFIG_TSEC2    1
 460 #define CONFIG_TSEC2_NAME       "eTSEC2"
 461 #define CONFIG_TSEC3    1
 462 #define CONFIG_TSEC3_NAME       "eTSEC3"
 463
 464 #define TSEC1_PHY_ADDR          2
 465 #define TSEC2_PHY_ADDR          0
 466 #define TSEC3_PHY_ADDR          1
 467
 468 #define CONFIG_VSC7385_ENET
 469
 470 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 471 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 472 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 473
 474 #define TSEC1_PHYIDX            0
 475 #define TSEC2_PHYIDX            0
 476 #define TSEC3_PHYIDX            0
 477
 478 /* Vitesse 7385 */
 479
 480 #ifdef CONFIG_VSC7385_ENET
 481 /* The size of the VSC7385 firmware image */
 482 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 483 #endif
 484
 485 #define CONFIG_ETHPRIME         "eTSEC1"
 486
 487 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 488
 489 #endif  /* CONFIG_TSEC_ENET */
 490
 491 /*
 492  * Environment
 493  */
 494 #if defined(CONFIG_SYS_RAMBOOT)
 495 #if defined(CONFIG_RAMBOOT_NAND)
 496         #define CONFIG_ENV_IS_IN_NAND   1
 497         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 498         #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 499 #elif defined(CONFIG_RAMBOOT_SDCARD)
 500 #define CONFIG_ENV_IS_IN_MMC
 501 #define CONFIG_FSL_FIXED_MMC_LOCATION
 502 #define CONFIG_ENV_SIZE                 0x2000
 503 #define CONFIG_SYS_MMC_ENV_DEV          0
 504 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 505         #define CONFIG_ENV_IS_IN_SPI_FLASH
 506         #define CONFIG_ENV_SPI_BUS      0
 507         #define CONFIG_ENV_SPI_CS       0
 508         #define CONFIG_ENV_SPI_MAX_HZ   10000000
 509         #define CONFIG_ENV_SPI_MODE     0
 510         #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 511         #define CONFIG_ENV_SECT_SIZE    0x10000
 512         #define CONFIG_ENV_SIZE         0x2000
 513 #endif
 514 #else
 515         #define CONFIG_ENV_IS_IN_FLASH  1
 516         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 517         #define CONFIG_ENV_ADDR         0xfff80000
 518         #else
 519         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 520         #endif
 521         #define CONFIG_ENV_SIZE         0x2000
 522         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 523 #endif
 524
 525 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 526 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 527
 528 /*
 529  * Command line configuration.
 530  */
 531 #include <config_cmd_default.h>
 532
 533 #define CONFIG_CMD_DATE
 534 #define CONFIG_CMD_ELF
 535 #define CONFIG_CMD_I2C
 536 #define CONFIG_CMD_IRQ
 537 #define CONFIG_CMD_MII
 538 #define CONFIG_CMD_PING
 539 #define CONFIG_CMD_SETEXPR
 540 #define CONFIG_CMD_REGINFO
 541
 542 #if defined(CONFIG_PCI)
 543 #define CONFIG_CMD_NET
 544 #define CONFIG_CMD_PCI
 545 #endif
 546
 547 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 548
 549 #define CONFIG_MMC      1
 550
 551 #ifdef CONFIG_MMC
 552 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 553 #define CONFIG_CMD_MMC
 554 #define CONFIG_DOS_PARTITION
 555 #define CONFIG_FSL_ESDHC
 556 #define CONFIG_GENERIC_MMC
 557 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 558 #ifdef CONFIG_P2020
 559 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
 560 #endif
 561 #endif
 562
 563 #define CONFIG_HAS_FSL_DR_USB
 564
 565 #if defined(CONFIG_HAS_FSL_DR_USB)
 566 #define CONFIG_USB_EHCI
 567
 568 #ifdef CONFIG_USB_EHCI
 569 #define CONFIG_CMD_USB
 570 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 571 #define CONFIG_USB_EHCI_FSL
 572 #define CONFIG_USB_STORAGE
 573 #endif
 574 #endif
 575
 576 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 577 #define CONFIG_CMD_EXT2
 578 #define CONFIG_CMD_FAT
 579 #define CONFIG_DOS_PARTITION
 580 #endif
 581
 582 /*
 583  * Miscellaneous configurable options
 584  */
 585 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 586 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 587 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 588 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 589 #if defined(CONFIG_CMD_KGDB)
 590 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 591 #else
 592 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 593 #endif
 594 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 595                                                 /* Print Buffer Size */
 596 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 597 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 598
 599 /*
 600  * For booting Linux, the board info and command line data
 601  * have to be in the first 64 MB of memory, since this is
 602  * the maximum mapped by the Linux kernel during initialization.
 603  */
 604 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)/* Initial Memory map for Linux*/
 605 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 606
 607 #if defined(CONFIG_CMD_KGDB)
 608 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 609 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 610 #endif
 611
 612 /*
 613  * Environment Configuration
 614  */
 615
 616 #if defined(CONFIG_TSEC_ENET)
 617 #define CONFIG_HAS_ETH0
 618 #define CONFIG_HAS_ETH1
 619 #define CONFIG_HAS_ETH2
 620 #endif
 621
 622 #define CONFIG_HOSTNAME         P2020RDB
 623 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 624 #define CONFIG_BOOTFILE         "uImage"
 625 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 626
 627 /* default location for tftp and bootm */
 628 #define CONFIG_LOADADDR         1000000
 629
 630 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 631 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 632
 633 #define CONFIG_BAUDRATE 115200
 634
 635 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 636         "netdev=eth0\0"                                         \
 637         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 638         "loadaddr=1000000\0"                                    \
 639         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 640                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 641                         " +$filesize; " \
 642                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 643                         " +$filesize; " \
 644                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 645                         " $filesize; "  \
 646                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 647                         " +$filesize; " \
 648                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 649                         " $filesize\0"  \
 650         "consoledev=ttyS0\0"                            \
 651         "ramdiskaddr=2000000\0"                 \
 652         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 653         "fdtaddr=c00000\0"                              \
 654         "fdtfile=p2020rdb.dtb\0"                \
 655         "bdev=sda1\0"   \
 656         "jffs2nor=mtdblock3\0"  \
 657         "norbootaddr=ef080000\0"        \
 658         "norfdtaddr=ef040000\0" \
 659         "jffs2nand=mtdblock9\0" \
 660         "nandbootaddr=100000\0" \
 661         "nandfdtaddr=80000\0"           \
 662         "nandimgsize=400000\0"          \
 663         "nandfdtsize=80000\0"           \
 664         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 665         "vscfw_addr=ef000000\0" \
 666         "othbootargs=ramdisk_size=600000\0" \
 667         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 668         "console=$consoledev,$baudrate $othbootargs; "  \
 669         "usb start;"                    \
 670         "fatload usb 0:2 $loadaddr $bootfile;"          \
 671         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 672         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 673         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 674         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 675         "console=$consoledev,$baudrate $othbootargs; "  \
 676         "usb start;"                    \
 677         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 678         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 679         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 680         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 681         "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
 682         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 683         "bootm $norbootaddr - $norfdtaddr\0"            \
 684         "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
 685         "console=$consoledev,$baudrate $othbootargs;"   \
 686         "nand read 2000000 $nandbootaddr $nandimgsize;" \
 687         "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
 688         "bootm 2000000 - 3000000;\0"
 689
 690 #define CONFIG_NFSBOOTCOMMAND           \
 691         "setenv bootargs root=/dev/nfs rw "     \
 692         "nfsroot=$serverip:$rootpath "          \
 693         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 694         "console=$consoledev,$baudrate $othbootargs;"   \
 695         "tftp $loadaddr $bootfile;"             \
 696         "tftp $fdtaddr $fdtfile;"               \
 697         "bootm $loadaddr - $fdtaddr"
 698
 699 #define CONFIG_HDBOOT                   \
 700         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 701         "console=$consoledev,$baudrate $othbootargs;"   \
 702         "usb start;"                    \
 703         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
 704         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 705         "bootm $loadaddr - $fdtaddr"
 706
 707 #define CONFIG_RAMBOOTCOMMAND           \
 708         "setenv bootargs root=/dev/ram rw "     \
 709         "console=$consoledev,$baudrate $othbootargs; "  \
 710         "tftp $ramdiskaddr $ramdiskfile;"       \
 711         "tftp $loadaddr $bootfile;"             \
 712         "tftp $fdtaddr $fdtfile;"               \
 713         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 714
 715 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 716
 717 #endif  /* __CONFIG_H */