include/configs/P1_P2_RDB.h

   1 /*
   2  * Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P1 P2 RDB board configuration file
  25  * This file is intended to address a set of Low End and Ultra Low End
  26  * Freescale SOCs of QorIQ series(RDB platforms).
  27  * Currently only P2020RDB
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #ifdef CONFIG_MK_P1011RDB
  34 #define CONFIG_P1011
  35 #endif
  36 #ifdef CONFIG_MK_P1020RDB
  37 #define CONFIG_P1020
  38 #endif
  39 #ifdef CONFIG_MK_P2010RDB
  40 #define CONFIG_P2010
  41 #endif
  42 #ifdef CONFIG_MK_P2020RDB
  43 #define CONFIG_P2020
  44 #endif
  45
  46 #ifdef CONFIG_MK_NAND
  47 #define CONFIG_NAND_U_BOOT              1
  48 #define CONFIG_RAMBOOT_NAND             1
  49 #define CONFIG_RAMBOOT_TEXT_BASE        0xf8f82000
  50 #endif
  51
  52 /* High Level Configuration Options */
  53 #define CONFIG_BOOKE            1       /* BOOKE */
  54 #define CONFIG_E500             1       /* BOOKE e500 family */
  55 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  56 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  57 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  58 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  59 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  60 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  61 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  62 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  63 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  64 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #ifndef __ASSEMBLY__
  68 extern unsigned long get_board_sys_clk(unsigned long dummy);
  69 #endif
  70 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1_P2 RDB */
  71 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
  72
  73 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
  74 #define CONFIG_MP
  75 #endif
  76
  77 /*
  78  * These can be toggled for performance analysis, otherwise use default.
  79  */
  80 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  81 #define CONFIG_BTB                      /* toggle branch predition */
  82
  83 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  84
  85 #define CONFIG_ENABLE_36BIT_PHYS        1
  86
  87 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  88 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
  89 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  90
  91  /*
  92   * Config the L2 Cache as L2 SRAM
  93   */
  94 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  95 #ifdef CONFIG_PHYS_64BIT
  96 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
  97 #else
  98 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  99 #endif
 100 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 101 #define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 102
 103 /*
 104  * Base addresses -- Note these are effective addresses where the
 105  * actual resources get mapped (not physical addresses)
 106  */
 107 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 108 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of */
 109                                                         /* CCSRBAR */
 110 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
 111                                                         /* CONFIG_SYS_IMMR */
 112
 113 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
 114 #define CONFIG_SYS_CCSRBAR_DEFAULT      CONFIG_SYS_CCSRBAR
 115 #else
 116 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 117 #endif
 118
 119 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
 120 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
 121
 122 /* DDR Setup */
 123 #define CONFIG_FSL_DDR2
 124 #undef CONFIG_FSL_DDR_INTERACTIVE
 125 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 126 #undef CONFIG_DDR_DLL
 127
 128 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 129
 130 #define CONFIG_SYS_SDRAM_SIZE   1024    /* DDR size on P1_P2 RDBs */
 131 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 132 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 133
 134 #define CONFIG_NUM_DDR_CONTROLLERS      1
 135 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 136 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 137
 138 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 139 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 140 #define CONFIG_SYS_DDR_SBE              0x00FF0000
 141
 142 #define CONFIG_SYS_DDR_TLB_START 9
 143
 144 /*
 145  * Memory map
 146  *
 147  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheablen
 148  * 0xa000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 149  * 0xffc2_0000  0xffc5_ffff     PCI IO range            256K non-cacheable
 150  *
 151  * Localbus cacheable (TBD)
 152  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 153  *
 154  * Localbus non-cacheable
 155  * 0xef00_0000  0xefff_ffff     FLASH                   16M non-cacheable
 156  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 157  * 0xffb0_0000  0xffbf_ffff     VSC7385 switch          1M non-cacheable
 158  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 159  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 160  */
 161
 162 /*
 163  * Local Bus Definitions
 164  */
 165 #define CONFIG_SYS_FLASH_BASE           0xef000000      /* start of FLASH 16M */
 166
 167 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 168
 169 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 170                                         BR_PS_16 | BR_V)
 171 #define CONFIG_FLASH_OR_PRELIM          0xff000ff7
 172
 173 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 174 #define CONFIG_SYS_FLASH_QUIET_TEST
 175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 176
 177 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 178 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 179 #undef  CONFIG_SYS_FLASH_CHECKSUM
 180 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 181 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 182
 183 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 184
 185 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
 186 #define CONFIG_SYS_RAMBOOT
 187 #else
 188 #undef CONFIG_SYS_RAMBOOT
 189 #endif
 190
 191 #define CONFIG_FLASH_CFI_DRIVER
 192 #define CONFIG_SYS_FLASH_CFI
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO
 194 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 195
 196 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 197
 198 #define CONFIG_SYS_INIT_RAM_LOCK        1
 199 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000        /* stack in RAM */
 200 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 201
 202 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END \
 204                                                 - CONFIG_SYS_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 208 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 209
 210 #ifndef CONFIG_NAND_SPL
 211 #define CONFIG_SYS_NAND_BASE            0xffa00000
 212 #else
 213 #define CONFIG_SYS_NAND_BASE            0xfff00000
 214 #endif
 215 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 216 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 217 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 218 #define NAND_MAX_CHIPS                  1
 219 #define CONFIG_MTD_NAND_VERIFY_WRITE
 220 #define CONFIG_CMD_NAND                 1
 221 #define CONFIG_NAND_FSL_ELBC            1
 222 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 223
 224 /* NAND boot: 4K NAND loader config */
 225 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 226 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 227 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 228 #define CONFIG_SYS_NAND_U_BOOT_START    (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 229 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 230 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 231 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP         ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 232
 233 /* NAND flash config */
 234 #define CONFIG_NAND_BR_PRELIM   (CONFIG_SYS_NAND_BASE_PHYS \
 235                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 236                                 | BR_PS_8       /* Port Size = 8 bit */ \
 237                                 | BR_MS_FCM             /* MSEL = FCM */ \
 238                                 | BR_V)                 /* valid */
 239
 240 #define CONFIG_NAND_OR_PRELIM   (0xFFF80000             /* length 32K */ \
 241                                 | OR_FCM_CSCT \
 242                                 | OR_FCM_CST \
 243                                 | OR_FCM_CHT \
 244                                 | OR_FCM_SCY_1 \
 245                                 | OR_FCM_TRLX \
 246                                 | OR_FCM_EHTR)
 247
 248 #ifdef CONFIG_RAMBOOT_NAND
 249 #define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 250 #define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 251 #define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 252 #define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 253 #else
 254 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 255 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 256 #define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 257 #define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 258 #endif
 259
 260 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 261
 262 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 263
 264 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
 265 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 266                                 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 267                                 OR_GPCM_EHTR | OR_GPCM_EAD)
 268
 269 /* Serial Port - controlled on board with jumper J8
 270  * open - index 2
 271  * shorted - index 1
 272  */
 273 #define CONFIG_CONS_INDEX       1
 274 //#define CONFIG_CONS_INDEX     2
 275 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 276 #define CONFIG_SYS_NS16550
 277 #define CONFIG_SYS_NS16550_SERIAL
 278 #define CONFIG_SYS_NS16550_REG_SIZE     1
 279 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 280
 281 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 282 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 283
 284 #define CONFIG_SYS_BAUDRATE_TABLE       \
 285         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 286
 287 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 288 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 289
 290 /* Use the HUSH parser */
 291 #define CONFIG_SYS_HUSH_PARSER
 292 #ifdef  CONFIG_SYS_HUSH_PARSER
 293 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 294 #endif
 295
 296 /*
 297  * Pass open firmware flat tree
 298  */
 299 #define CONFIG_OF_LIBFDT                1
 300 #define CONFIG_OF_BOARD_SETUP           1
 301 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 302
 303 #define CONFIG_SYS_64BIT_VSPRINTF       1
 304 #define CONFIG_SYS_64BIT_STRTOUL        1
 305
 306 /* new uImage format support */
 307 #define CONFIG_FIT              1
 308 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 309
 310 /* I2C */
 311 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 312 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 313 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 314 #define CONFIG_I2C_MULTI_BUS
 315 #define CONFIG_I2C_CMD_TREE
 316 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address*/
 317 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 318 #define CONFIG_SYS_I2C_SLAVE            0x7F
 319 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}      /* Don't probe these addrs */
 320 #define CONFIG_SYS_I2C_OFFSET           0x3000
 321 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 322
 323 /*
 324  * I2C2 EEPROM
 325  */
 326 #define CONFIG_ID_EEPROM
 327 #ifdef CONFIG_ID_EEPROM
 328 #define CONFIG_SYS_I2C_EEPROM_NXID
 329 #endif
 330 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 331 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 332 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 333
 334 #define CONFIG_RTC_DS1337
 335 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 336 /*
 337  * General PCI
 338  * Memory space is mapped 1-1, but I/O space must start from 0.
 339  */
 340
 341 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 342 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 343 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 344 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 345 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 346 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 347 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 348 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 349 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 350
 351 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 352 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 353 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 354 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 355 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 356 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc30000
 357 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 358 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc30000
 359 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 360
 361 #if defined(CONFIG_PCI)
 362 #define CONFIG_NET_MULTI
 363 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 364
 365 #undef CONFIG_EEPRO100
 366 #undef CONFIG_TULIP
 367 #undef CONFIG_RTL8139
 368
 369 #ifdef CONFIG_RTL8139
 370 /* This macro is used by RTL8139 but not defined in PPC architecture */
 371 #define KSEG1ADDR(x)            (x)
 372 #define _IO_BASE        0x00000000
 373 #endif
 374
 375
 376 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 377 #define CONFIG_DOS_PARTITION
 378
 379 #endif  /* CONFIG_PCI */
 380
 381 #if defined(CONFIG_TSEC_ENET)
 382 #ifndef CONFIG_NET_MULTI
 383 #define CONFIG_NET_MULTI        1
 384 #endif
 385
 386 #define CONFIG_MII              1       /* MII PHY management */
 387 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 388 #define CONFIG_TSEC1    1
 389 #define CONFIG_TSEC1_NAME       "eTSEC1"
 390 #define CONFIG_TSEC2    1
 391 #define CONFIG_TSEC2_NAME       "eTSEC2"
 392 #define CONFIG_TSEC3    1
 393 #define CONFIG_TSEC3_NAME       "eTSEC3"
 394
 395 #define TSEC1_PHY_ADDR          2
 396 #define TSEC2_PHY_ADDR          0
 397 #define TSEC3_PHY_ADDR          1
 398
 399 #define CONFIG_VSC7385_ENET
 400
 401 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 402 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 403 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 404
 405 #define TSEC1_PHYIDX            0
 406 #define TSEC2_PHYIDX            0
 407 #define TSEC3_PHYIDX            0
 408
 409 /* Vitesse 7385 */
 410
 411 #ifdef CONFIG_VSC7385_ENET
 412 /* The size of the VSC7385 firmware image */
 413 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 414 #endif
 415
 416 #define CONFIG_ETHPRIME         "eTSEC1"
 417
 418 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 419 #endif  /* CONFIG_TSEC_ENET */
 420
 421 /*
 422  * Environment
 423  */
 424 #if defined(CONFIG_SYS_RAMBOOT)
 425 #if defined(CONFIG_RAMBOOT_NAND)
 426         #define CONFIG_ENV_IS_IN_NAND   1
 427         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 428         #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 429 #endif
 430 #else
 431         #define CONFIG_ENV_IS_IN_FLASH  1
 432         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 433         #define CONFIG_ENV_ADDR         0xfff80000
 434         #else
 435         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 436         #endif
 437         #define CONFIG_ENV_SIZE         0x2000
 438         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 439 #endif
 440
 441 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 442 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 443
 444 /*
 445  * Command line configuration.
 446  */
 447 #include <config_cmd_default.h>
 448
 449 #define CONFIG_CMD_DATE
 450 #define CONFIG_CMD_ELF
 451 #define CONFIG_CMD_I2C
 452 #define CONFIG_CMD_IRQ
 453 #define CONFIG_CMD_MII
 454 #define CONFIG_CMD_PING
 455 #define CONFIG_CMD_SETEXPR
 456
 457 #if defined(CONFIG_PCI)
 458 #define CONFIG_CMD_NET
 459 #define CONFIG_CMD_PCI
 460 #endif
 461
 462 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 463
 464 #define CONFIG_MMC      1
 465
 466 #ifdef CONFIG_MMC
 467 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 468 #define CONFIG_CMD_MMC
 469 #define CONFIG_DOS_PARTITION
 470 #define CONFIG_FSL_ESDHC
 471 #define CONFIG_GENERIC_MMC
 472 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 473 #ifdef CONFIG_P2020
 474 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
 475 #endif
 476 #endif
 477
 478 #define CONFIG_USB_EHCI
 479
 480 #ifdef CONFIG_USB_EHCI
 481 #define CONFIG_CMD_USB
 482 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 483 #define CONFIG_USB_EHCI_FSL
 484 #define CONFIG_USB_STORAGE
 485 #endif
 486
 487 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 488 #define CONFIG_CMD_EXT2
 489 #define CONFIG_CMD_FAT
 490 #define CONFIG_DOS_PARTITION
 491 #endif
 492
 493 /*
 494  * Miscellaneous configurable options
 495  */
 496 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 497 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 498 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 499 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 500 #if defined(CONFIG_CMD_KGDB)
 501 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 502 #else
 503 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 504 #endif
 505 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 506                                                 /* Print Buffer Size */
 507 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 508 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 509 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 510
 511 /*
 512  * For booting Linux, the board info and command line data
 513  * have to be in the first 16 MB of memory, since this is
 514  * the maximum mapped by the Linux kernel during initialization.
 515  */
 516 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)/* Initial Memory map for Linux*/
 517
 518 /*
 519  * Internal Definitions
 520  *
 521  * Boot Flags
 522  */
 523 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 524 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 525
 526 #if defined(CONFIG_CMD_KGDB)
 527 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 528 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 529 #endif
 530
 531 /*
 532  * Environment Configuration
 533  */
 534
 535 #if defined(CONFIG_TSEC_ENET)
 536 #define CONFIG_HAS_ETH0
 537 #define CONFIG_HAS_ETH1
 538 #define CONFIG_HAS_ETH2
 539 #endif
 540
 541 #define CONFIG_HOSTNAME         P2020RDB
 542 #define CONFIG_ROOTPATH         /opt/nfsroot
 543 #define CONFIG_BOOTFILE         uImage
 544 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 545
 546 /* default location for tftp and bootm */
 547 #define CONFIG_LOADADDR         1000000
 548
 549 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 550 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 551
 552 #define CONFIG_BAUDRATE 115200
 553
 554 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 555         "netdev=eth0\0"                                         \
 556         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 557         "loadaddr=1000000\0"                    \
 558         "bootfile=uImage\0"     \
 559         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 560                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 561                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 562                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 563                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 564                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 565         "consoledev=ttyS0\0"                            \
 566         "ramdiskaddr=2000000\0"                 \
 567         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 568         "fdtaddr=c00000\0"                              \
 569         "fdtfile=p2020rdb.dtb\0"                \
 570         "bdev=sda1\0"   \
 571         "jffs2nor=mtdblock3\0"  \
 572         "norbootaddr=ef080000\0"        \
 573         "norfdtaddr=ef040000\0" \
 574         "jffs2nand=mtdblock9\0" \
 575         "nandbootaddr=100000\0" \
 576         "nandfdtaddr=80000\0"           \
 577         "nandimgsize=400000\0"          \
 578         "nandfdtsize=80000\0"           \
 579         "usb_phy_type=ulpi\0"           \
 580         "vscfw_addr=ef000000\0" \
 581         "othbootargs=ramdisk_size=600000\0" \
 582         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 583         "console=$consoledev,$baudrate $othbootargs; "  \
 584         "usb start;"                    \
 585         "fatload usb 0:2 $loadaddr $bootfile;"          \
 586         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 587         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 588         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 589         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 590         "console=$consoledev,$baudrate $othbootargs; "  \
 591         "usb start;"                    \
 592         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 593         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 594         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 595         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 596         "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
 597         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 598         "bootm $norbootaddr - $norfdtaddr\0"            \
 599         "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
 600         "console=$consoledev,$baudrate $othbootargs;"   \
 601         "nand read 2000000 $nandbootaddr $nandimgsize;" \
 602         "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
 603         "bootm 2000000 - 3000000;\0"
 604
 605 #define CONFIG_NFSBOOTCOMMAND           \
 606         "setenv bootargs root=/dev/nfs rw "     \
 607         "nfsroot=$serverip:$rootpath "          \
 608         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 609         "console=$consoledev,$baudrate $othbootargs;"   \
 610         "tftp $loadaddr $bootfile;"             \
 611         "tftp $fdtaddr $fdtfile;"               \
 612         "bootm $loadaddr - $fdtaddr"
 613
 614 #define CONFIG_HDBOOT                   \
 615         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 616         "console=$consoledev,$baudrate $othbootargs;"   \
 617         "usb start;"                    \
 618         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
 619         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 620         "bootm $loadaddr - $fdtaddr"
 621
 622 #define CONFIG_RAMBOOTCOMMAND           \
 623         "setenv bootargs root=/dev/ram rw "     \
 624         "console=$consoledev,$baudrate $othbootargs; "  \
 625         "tftp $ramdiskaddr $ramdiskfile;"       \
 626         "tftp $loadaddr $bootfile;"             \
 627         "tftp $fdtaddr $fdtfile;"               \
 628         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 629
 630 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 631
 632 #endif  /* __CONFIG_H */