include/configs/P2020DS.h

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * p2020ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_36BIT
  33 #define CONFIG_PHYS_64BIT
  34 #endif
  35
  36 #ifdef CONFIG_SDCARD
  37 #define CONFIG_SYS_RAMBOOT
  38 #define CONFIG_SYS_EXTRA_ENV_RELOC
  39 #define CONFIG_SYS_TEXT_BASE            0xf8f80000
  40 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  41 #endif
  42
  43 /* High Level Configuration Options */
  44 #define CONFIG_BOOKE            1       /* BOOKE */
  45 #define CONFIG_E500             1       /* BOOKE e500 family */
  46 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  47 #define CONFIG_P2020            1
  48 #define CONFIG_P2020DS          1
  49 #define CONFIG_MP               1       /* support multiple processors */
  50
  51 #ifndef CONFIG_SYS_TEXT_BASE
  52 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  53 #endif
  54
  55 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  57 #endif
  58
  59 #define CONFIG_SYS_SRIO
  60 #define CONFIG_SRIO1                    /* SRIO port 1 */
  61 #define CONFIG_SRIO2                    /* SRIO port 2 */
  62
  63 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  64 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  65 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  66 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  67 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  68 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  69 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  70 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  71
  72 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  73 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  74
  75 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  76 #define CONFIG_ENV_OVERWRITE
  77
  78 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  79 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
  80 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  81
  82 /*
  83  * These can be toggled for performance analysis, otherwise use default.
  84  */
  85 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  86 #define CONFIG_BTB                      /* toggle branch predition */
  87
  88 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
  89
  90 #define CONFIG_ENABLE_36BIT_PHYS        1
  91
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CONFIG_ADDR_MAP                 1
  94 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  95 #endif
  96
  97 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  98 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  99 #define CONFIG_SYS_MEMTEST_END          0x00400000
 100 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 101
 102 /*
 103  * Config the L2 Cache
 104  */
 105 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 106 #ifdef CONFIG_PHYS_64BIT
 107 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 108 #else
 109 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 110 #endif
 111 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 112 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 113
 114 /*
 115  * Base addresses -- Note these are effective addresses where the
 116  * actual resources get mapped (not physical addresses)
 117  */
 118 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 119 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 120 #ifdef CONFIG_PHYS_64BIT
 121 #define CONFIG_SYS_CCSRBAR_PHYS         0xfffe00000ull  /* physical addr of CCSRBAR */
 122 #else
 123 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 124 #endif
 125 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 126
 127 /* DDR Setup */
 128 #define CONFIG_VERY_BIG_RAM
 129 #ifdef CONFIG_DDR2
 130 #define CONFIG_FSL_DDR2
 131 #else
 132 #define CONFIG_FSL_DDR3         1
 133 #endif
 134 #undef CONFIG_FSL_DDR_INTERACTIVE
 135
 136 /* ECC will be enabled based on perf_mode environment variable */
 137 /* #define      CONFIG_DDR_ECC */
 138
 139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 140 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 141
 142 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 143 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 144
 145 #define CONFIG_NUM_DDR_CONTROLLERS      1
 146 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 147 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 148
 149 /* I2C addresses of SPD EEPROMs */
 150 #define CONFIG_DDR_SPD
 151 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD EEPROM located on I2C bus 0 */
 152 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 153
 154 /* These are used when DDR doesn't use SPD.  */
 155 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1GB */
 156
 157 /* Default settings for "stable" mode */
 158 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 159 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
 160 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 161 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
 162 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 163 #define CONFIG_SYS_DDR_TIMING_0         0x00330804
 164 #define CONFIG_SYS_DDR_TIMING_1         0x6f6b4846
 165 #define CONFIG_SYS_DDR_TIMING_2         0x0fa890d4
 166 #define CONFIG_SYS_DDR_MODE_1           0x00421422
 167 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 168 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
 169 #define CONFIG_SYS_DDR_INTERVAL         0x61800100
 170 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 171 #define CONFIG_SYS_DDR_CLK_CTRL         0x02000000
 172 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 173 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 174 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 175 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8655A608
 176 #define CONFIG_SYS_DDR_CONTROL          0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
 177 #define CONFIG_SYS_DDR_CONTROL2         0x24400011
 178 #define CONFIG_SYS_DDR_CDR1             0x00040000
 179 #define CONFIG_SYS_DDR_CDR2             0x00000000
 180
 181 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 182 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 183 #define CONFIG_SYS_DDR_SBE              0x00010000
 184
 185 /* Settings that differ for "performance" mode */
 186 #define CONFIG_SYS_DDR_CS0_BNDS_PERF            0x0000007F /* Interleaving Enabled */
 187 #define CONFIG_SYS_DDR_CS1_BNDS_PERF            0x00000000 /* Interleaving Enabled */
 188 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014202
 189 #define CONFIG_SYS_DDR_TIMING_1_PERF            0x5d5b4543
 190 #define CONFIG_SYS_DDR_TIMING_2_PERF            0x0fa890ce
 191 #define CONFIG_SYS_DDR_CONTROL_PERF             0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
 192
 193 /*
 194  * The following set of values were tested for DDR2
 195  * with a DDR3 to DDR2 interposer
 196  *
 197 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 198 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 199 #define CONFIG_SYS_DDR_TIMING_1         0x3935d322
 200 #define CONFIG_SYS_DDR_TIMING_2         0x14904cc8
 201 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 202 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 203 #define CONFIG_SYS_DDR_INTERVAL         0x06180100
 204 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 205 #define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
 206 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 207 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 208 #define CONFIG_SYS_DDR_CONTROL          0xC3008000
 209 #define CONFIG_SYS_DDR_CONTROL2         0x04400010
 210  *
 211  */
 212
 213 #undef CONFIG_CLOCKS_IN_MHZ
 214
 215 /*
 216  * Memory map
 217  *
 218  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 219  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 220  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 221  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 222  *
 223  * Localbus cacheable (TBD)
 224  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 225  *
 226  * Localbus non-cacheable
 227  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 228  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 229  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 230  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 231  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 232  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 233  */
 234
 235 /*
 236  * Local Bus Definitions
 237  */
 238 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 241 #else
 242 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 243 #endif
 244
 245 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 246 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 247
 248 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 249 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 250
 251 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 252 #define CONFIG_SYS_FLASH_QUIET_TEST
 253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 254
 255 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 256 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 257 #undef  CONFIG_SYS_FLASH_CHECKSUM
 258 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 259 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 260
 261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 262
 263 #define CONFIG_FLASH_CFI_DRIVER
 264 #define CONFIG_SYS_FLASH_CFI
 265 #define CONFIG_SYS_FLASH_EMPTY_INFO
 266 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 267
 268 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 269
 270 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 271 #define CONFIG_FSL_NGPIXIS              /* use common ngPIXIS code */
 272
 273 #ifdef CONFIG_FSL_NGPIXIS
 274 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 275 #ifdef CONFIG_PHYS_64BIT
 276 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 277 #else
 278 #define PIXIS_BASE_PHYS PIXIS_BASE
 279 #endif
 280
 281 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 282 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 283
 284 #define PIXIS_LBMAP_SWITCH      7
 285 #define PIXIS_LBMAP_MASK        0xf0
 286 #define PIXIS_LBMAP_SHIFT       4
 287 #define PIXIS_LBMAP_ALTBANK     0x20
 288 #endif
 289
 290 #define CONFIG_SYS_INIT_RAM_LOCK        1
 291 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 295 /* The assembler doesn't like typecast */
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 297         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 298           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 299 #else
 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 303 #endif
 304 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 305
 306 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 307 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 308
 309 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 310 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 311
 312 #define CONFIG_SYS_NAND_BASE            0xffa00000
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 315 #else
 316 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 317 #endif
 318 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE,\
 319                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 320                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 321                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 322 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 323 #define CONFIG_MTD_NAND_VERIFY_WRITE
 324 #define CONFIG_CMD_NAND                 1
 325 #define CONFIG_NAND_FSL_ELBC            1
 326 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 327
 328 /* NAND flash config */
 329 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 330                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 331                                 | BR_PS_8               /* Port Size = 8bit */ \
 332                                 | BR_MS_FCM             /* MSEL = FCM */ \
 333                                 | BR_V)                 /* valid */
 334 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000          /* length 256K */ \
 335                                 | OR_FCM_PGS            /* Large Page*/ \
 336                                 | OR_FCM_CSCT \
 337                                 | OR_FCM_CST \
 338                                 | OR_FCM_CHT \
 339                                 | OR_FCM_SCY_1 \
 340                                 | OR_FCM_TRLX \
 341                                 | OR_FCM_EHTR)
 342
 343 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 344 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 345 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM  /* NAND Base Address */
 346 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM  /* NAND Options */
 347
 348 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 349                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 350                                 | BR_PS_8               /* Port Size = 8bit */ \
 351                                 | BR_MS_FCM             /* MSEL = FCM */ \
 352                                 | BR_V)                 /* valid */
 353 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
 354 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 355                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 356                                 | BR_PS_8               /* Port Size = 8bit */ \
 357                                 | BR_MS_FCM             /* MSEL = FCM */ \
 358                                 | BR_V)                 /* valid */
 359 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
 360
 361 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 362                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 363                                 | BR_PS_8               /* Port Size = 8bit */ \
 364                                 | BR_MS_FCM             /* MSEL = FCM */ \
 365                                 | BR_V)                 /* valid */
 366 #define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
 367
 368 /* Serial Port - controlled on board with jumper J8
 369  * open - index 2
 370  * shorted - index 1
 371  */
 372 #define CONFIG_CONS_INDEX       1
 373 #define CONFIG_SYS_NS16550
 374 #define CONFIG_SYS_NS16550_SERIAL
 375 #define CONFIG_SYS_NS16550_REG_SIZE     1
 376 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 377
 378 #define CONFIG_SYS_BAUDRATE_TABLE       \
 379         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 380
 381 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 382 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 383
 384 /* Use the HUSH parser */
 385 #define CONFIG_SYS_HUSH_PARSER
 386 #ifdef  CONFIG_SYS_HUSH_PARSER
 387 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 388 #endif
 389
 390 /*
 391  * Pass open firmware flat tree
 392  */
 393 #define CONFIG_OF_LIBFDT                1
 394 #define CONFIG_OF_BOARD_SETUP           1
 395 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 396
 397 /* I2C */
 398 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 399 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 400 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 401 #define CONFIG_I2C_MULTI_BUS
 402 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 403 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 404 #define CONFIG_SYS_I2C_SLAVE            0x7F
 405 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
 406 #define CONFIG_SYS_I2C_OFFSET           0x3000
 407 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 408
 409 /*
 410  * I2C2 EEPROM
 411  */
 412 #define CONFIG_ID_EEPROM
 413 #ifdef CONFIG_ID_EEPROM
 414 #define CONFIG_SYS_I2C_EEPROM_NXID
 415 #endif
 416 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 417 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 418 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 419
 420 /*
 421  * General PCI
 422  * Memory space is mapped 1-1, but I/O space must start from 0.
 423  */
 424
 425 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 426 #define CONFIG_SYS_PCIE3_NAME           "Slot 1"
 427 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 428 #ifdef CONFIG_PHYS_64BIT
 429 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 430 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 431 #else
 432 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 433 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 434 #endif
 435 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 436 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 437 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 438 #ifdef CONFIG_PHYS_64BIT
 439 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 440 #else
 441 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 442 #endif
 443 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 444
 445 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 446 #define CONFIG_SYS_PCIE2_NAME           "ULI"
 447 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 448 #ifdef CONFIG_PHYS_64BIT
 449 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 450 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 451 #else
 452 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 453 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 454 #endif
 455 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 456 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 457 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 458 #ifdef CONFIG_PHYS_64BIT
 459 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 460 #else
 461 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 462 #endif
 463 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 464
 465 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 466 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 467 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 468 #ifdef CONFIG_PHYS_64BIT
 469 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 470 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 471 #else
 472 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 473 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 474 #endif
 475 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 476 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 477 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 478 #ifdef CONFIG_PHYS_64BIT
 479 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 480 #else
 481 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 482 #endif
 483 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 484
 485 #if defined(CONFIG_PCI)
 486
 487 /*PCIE video card used*/
 488 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 489
 490 /* video */
 491 #define CONFIG_VIDEO
 492
 493 #if defined(CONFIG_VIDEO)
 494 #define CONFIG_BIOSEMU
 495 #define CONFIG_CFB_CONSOLE
 496 #define CONFIG_VIDEO_SW_CURSOR
 497 #define CONFIG_VGA_AS_SINGLE_DEVICE
 498 #define CONFIG_ATI_RADEON_FB
 499 #define CONFIG_VIDEO_LOGO
 500 /*#define CONFIG_CONSOLE_CURSOR*/
 501 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 502 #endif
 503
 504 /* SRIO1 uses the same window as PCIE2 mem window */
 505 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 506 #ifdef CONFIG_PHYS_64BIT
 507 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 508 #else
 509 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 510 #endif
 511 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 512
 513 /* SRIO2 uses the same window as PCIE1 mem window */
 514 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xc0000000
 515 #ifdef CONFIG_PHYS_64BIT
 516 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc40000000ull
 517 #else
 518 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc0000000
 519 #endif
 520 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x20000000      /* 512M */
 521
 522 #define CONFIG_NET_MULTI
 523 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 524
 525 #undef CONFIG_EEPRO100
 526 #undef CONFIG_TULIP
 527 #define CONFIG_RTL8139
 528
 529 #ifndef CONFIG_PCI_PNP
 530         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
 531         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
 532         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 533 #endif
 534
 535 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 536 #define CONFIG_DOS_PARTITION
 537 #define CONFIG_SCSI_AHCI
 538
 539 #ifdef CONFIG_SCSI_AHCI
 540 #define CONFIG_SATA_ULI5288
 541 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 542 #define CONFIG_SYS_SCSI_MAX_LUN 1
 543 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 544 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 545 #endif /* SCSI */
 546
 547 #endif  /* CONFIG_PCI */
 548
 549
 550 #if defined(CONFIG_TSEC_ENET)
 551
 552 #ifndef CONFIG_NET_MULTI
 553 #define CONFIG_NET_MULTI        1
 554 #endif
 555
 556 #define CONFIG_MII              1       /* MII PHY management */
 557 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 558 #define CONFIG_TSEC1    1
 559 #define CONFIG_TSEC1_NAME       "eTSEC1"
 560 #define CONFIG_TSEC2    1
 561 #define CONFIG_TSEC2_NAME       "eTSEC2"
 562 #define CONFIG_TSEC3    1
 563 #define CONFIG_TSEC3_NAME       "eTSEC3"
 564
 565 #define CONFIG_PIXIS_SGMII_CMD
 566 #define CONFIG_FSL_SGMII_RISER  1
 567 #define SGMII_RISER_PHY_OFFSET  0x1b
 568
 569 #ifdef CONFIG_FSL_SGMII_RISER
 570 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 571 #endif
 572
 573 #define TSEC1_PHY_ADDR          0
 574 #define TSEC2_PHY_ADDR          1
 575 #define TSEC3_PHY_ADDR          2
 576
 577 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 578 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 579 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 580
 581 #define TSEC1_PHYIDX            0
 582 #define TSEC2_PHYIDX            0
 583 #define TSEC3_PHYIDX            0
 584
 585 #define CONFIG_ETHPRIME         "eTSEC1"
 586
 587 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 588 #endif  /* CONFIG_TSEC_ENET */
 589
 590 /*
 591  * Environment
 592  */
 593 #if defined(CONFIG_SDCARD)
 594 #define CONFIG_ENV_IS_IN_MMC
 595 #define CONFIG_ENV_SIZE                 0x2000
 596 #define CONFIG_SYS_MMC_ENV_DEV          0
 597 #else
 598 #define CONFIG_ENV_IS_IN_FLASH  1
 599 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 600 #define CONFIG_ENV_ADDR         0xfff80000
 601 #else
 602 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 603 #endif
 604 #define CONFIG_ENV_SIZE         0x2000
 605 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 606 #endif
 607
 608 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 609 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 610
 611 /*
 612  * Command line configuration.
 613  */
 614 #include <config_cmd_default.h>
 615
 616 #define CONFIG_CMD_IRQ
 617 #define CONFIG_CMD_PING
 618 #define CONFIG_CMD_I2C
 619 #define CONFIG_CMD_MII
 620 #define CONFIG_CMD_ELF
 621 #define CONFIG_CMD_IRQ
 622 #define CONFIG_CMD_SETEXPR
 623 #define CONFIG_CMD_REGINFO
 624
 625 #if defined(CONFIG_PCI)
 626 #define CONFIG_CMD_PCI
 627 #define CONFIG_CMD_NET
 628 #define CONFIG_CMD_SCSI
 629 #define CONFIG_CMD_EXT2
 630 #endif
 631
 632 /*
 633  * USB
 634  */
 635 #define CONFIG_USB_EHCI
 636
 637 #ifdef CONFIG_USB_EHCI
 638 #define CONFIG_CMD_USB
 639 #define CONFIG_USB_STORAGE
 640 #define CONFIG_USB_EHCI_FSL
 641 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 642 #endif
 643
 644 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 645
 646 /*
 647  * SDHC/MMC
 648  */
 649 #define CONFIG_MMC
 650
 651 #ifdef CONFIG_MMC
 652 #define CONFIG_FSL_ESDHC
 653 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 654 #define CONFIG_CMD_MMC
 655 #define CONFIG_GENERIC_MMC
 656 #endif
 657
 658 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 659 #define CONFIG_CMD_EXT2
 660 #define CONFIG_CMD_FAT
 661 #define CONFIG_DOS_PARTITION
 662 #endif
 663
 664 /*
 665  * Miscellaneous configurable options
 666  */
 667 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 668 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 669 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 670 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 671 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 672 #if defined(CONFIG_CMD_KGDB)
 673 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 674 #else
 675 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 676 #endif
 677 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 678 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 679 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 680 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 681
 682 /*
 683  * For booting Linux, the board info and command line data
 684  * have to be in the first 16 MB of memory, since this is
 685  * the maximum mapped by the Linux kernel during initialization.
 686  */
 687 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 688 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 689
 690 #if defined(CONFIG_CMD_KGDB)
 691 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 692 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 693 #endif
 694
 695 /*
 696  * Environment Configuration
 697  */
 698
 699 /* The mac addresses for all ethernet interface */
 700 #if defined(CONFIG_TSEC_ENET)
 701 #define CONFIG_HAS_ETH0
 702 #define CONFIG_HAS_ETH1
 703 #define CONFIG_HAS_ETH2
 704 #endif
 705
 706 #define CONFIG_IPADDR           192.168.1.254
 707
 708 #define CONFIG_HOSTNAME         unknown
 709 #define CONFIG_ROOTPATH         /opt/nfsroot
 710 #define CONFIG_BOOTFILE         uImage
 711 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 712
 713 #define CONFIG_SERVERIP         192.168.1.1
 714 #define CONFIG_GATEWAYIP        192.168.1.1
 715 #define CONFIG_NETMASK          255.255.255.0
 716
 717 /* default location for tftp and bootm */
 718 #define CONFIG_LOADADDR         1000000
 719
 720 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 721 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 722
 723 #define CONFIG_BAUDRATE 115200
 724
 725 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 726  "perf_mode=performance\0"                      \
 727  "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1\0"        \
 728  "netdev=eth0\0"                                                \
 729  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 730  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 731         "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 732         "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 733         "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 734         "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 735         "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 736  "satabootcmd=setenv bootargs root=/dev/$bdev rw "      \
 737         "console=$consoledev,$baudrate $othbootargs;"   \
 738         "tftp $loadaddr $bootfile;"                     \
 739         "tftp $fdtaddr $fdtfile;"                       \
 740         "bootm $loadaddr - $fdtaddr"                    \
 741  "consoledev=ttyS0\0"                           \
 742  "ramdiskaddr=2000000\0"                        \
 743  "ramdiskfile=p2020ds/ramdisk.uboot\0"          \
 744  "fdtaddr=c00000\0"                             \
 745  "othbootargs=cache-sram-size=0x10000\0"        \
 746  "fdtfile=p2020ds/p2020ds.dtb\0"                \
 747  "bdev=sda3\0"                                  \
 748  "partition=scsi 0:0\0"
 749
 750 #define CONFIG_HDBOOT                           \
 751  "setenv bootargs root=/dev/$bdev rw "          \
 752  "console=$consoledev,$baudrate $othbootargs;"  \
 753  "ext2load $partition $loadaddr $bootfile;"     \
 754  "ext2load $partition $fdtaddr $fdtfile;"       \
 755  "bootm $loadaddr - $fdtaddr"
 756
 757 #define CONFIG_NFSBOOTCOMMAND           \
 758  "setenv bootargs root=/dev/nfs rw "    \
 759  "nfsroot=$serverip:$rootpath "         \
 760  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 761  "console=$consoledev,$baudrate $othbootargs;"  \
 762  "tftp $loadaddr $bootfile;"            \
 763  "tftp $fdtaddr $fdtfile;"              \
 764  "bootm $loadaddr - $fdtaddr"
 765
 766 #define CONFIG_RAMBOOTCOMMAND           \
 767  "setenv bootargs root=/dev/ram rw "    \
 768  "console=$consoledev,$baudrate $othbootargs;"  \
 769  "tftp $ramdiskaddr $ramdiskfile;"      \
 770  "tftp $loadaddr $bootfile;"            \
 771  "tftp $fdtaddr $fdtfile;"              \
 772  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 773
 774 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 775
 776 #endif  /* __CONFIG_H */