include/configs/P2020DS.h

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * p2020ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_MK_36BIT
  33 #define CONFIG_PHYS_64BIT
  34 #endif
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_BOOKE            1       /* BOOKE */
  38 #define CONFIG_E500             1       /* BOOKE e500 family */
  39 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  40 #define CONFIG_P2020            1
  41 #define CONFIG_P2020DS          1
  42 #define CONFIG_MP               1       /* support multiple processors */
  43
  44 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  45 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  46 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  47 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  48 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  49 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  50 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  51 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  52
  53 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  54 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  55
  56 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  57 #define CONFIG_ENV_OVERWRITE
  58
  59 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  60 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
  61 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  67 #define CONFIG_BTB                      /* toggle branch predition */
  68
  69 #define CONFIG_ENABLE_36BIT_PHYS        1
  70
  71 #ifdef CONFIG_PHYS_64BIT
  72 #define CONFIG_ADDR_MAP                 1
  73 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  74 #endif
  75
  76 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  77 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  78 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  79
  80 /*
  81  * Base addresses -- Note these are effective addresses where the
  82  * actual resources get mapped (not physical addresses)
  83  */
  84 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  85 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_SYS_CCSRBAR_PHYS         0xfffe00000ull  /* physical addr of CCSRBAR */
  88 #else
  89 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  90 #endif
  91 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  92
  93 #define CONFIG_SYS_PCIE3_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
  94 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
  95 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
  96
  97 /* DDR Setup */
  98 #define CONFIG_VERY_BIG_RAM
  99 #define CONFIG_FSL_DDR3         1
 100 #undef CONFIG_FSL_DDR_INTERACTIVE
 101
 102 /* ECC will be enabled based on perf_mode environment variable */
 103 /* #define      CONFIG_DDR_ECC */
 104
 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 106 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 107
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 109 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 110
 111 #define CONFIG_NUM_DDR_CONTROLLERS      1
 112 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 113 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 114
 115 /* I2C addresses of SPD EEPROMs */
 116 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD EEPROM located on I2C bus 0 */
 117 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 118
 119 /* These are used when DDR doesn't use SPD.  */
 120 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1GB */
 121
 122 /* Default settings for "stable" mode */
 123 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 124 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
 125 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 126 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
 127 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 128 #define CONFIG_SYS_DDR_TIMING_0         0x00330804
 129 #define CONFIG_SYS_DDR_TIMING_1         0x6f6b4846
 130 #define CONFIG_SYS_DDR_TIMING_2         0x0fa890d4
 131 #define CONFIG_SYS_DDR_MODE_1           0x00421422
 132 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 133 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
 134 #define CONFIG_SYS_DDR_INTERVAL         0x61800100
 135 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 136 #define CONFIG_SYS_DDR_CLK_CTRL         0x02000000
 137 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 138 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 139 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 140 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8655A608
 141 #define CONFIG_SYS_DDR_CONTROL          0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
 142 #define CONFIG_SYS_DDR_CONTROL2         0x24400011
 143 #define CONFIG_SYS_DDR_CDR1             0x00040000
 144 #define CONFIG_SYS_DDR_CDR2             0x00000000
 145
 146 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 147 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 148 #define CONFIG_SYS_DDR_SBE              0x00010000
 149
 150 /* Settings that differ for "performance" mode */
 151 #define CONFIG_SYS_DDR_CS0_BNDS_PERF            0x0000007F /* Interleaving Enabled */
 152 #define CONFIG_SYS_DDR_CS1_BNDS_PERF            0x00000000 /* Interleaving Enabled */
 153 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014202
 154 #define CONFIG_SYS_DDR_TIMING_1_PERF            0x5d5b4543
 155 #define CONFIG_SYS_DDR_TIMING_2_PERF            0x0fa890ce
 156 #define CONFIG_SYS_DDR_CONTROL_PERF             0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
 157
 158 /*
 159  * The following set of values were tested for DDR2
 160  * with a DDR3 to DDR2 interposer
 161  *
 162 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 163 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 164 #define CONFIG_SYS_DDR_TIMING_1         0x3935d322
 165 #define CONFIG_SYS_DDR_TIMING_2         0x14904cc8
 166 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 167 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 168 #define CONFIG_SYS_DDR_INTERVAL         0x06180100
 169 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 170 #define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
 171 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 172 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 173 #define CONFIG_SYS_DDR_CONTROL          0xC3008000
 174 #define CONFIG_SYS_DDR_CONTROL2         0x04400010
 175  *
 176  */
 177
 178 #undef CONFIG_CLOCKS_IN_MHZ
 179
 180 /*
 181  * Memory map
 182  *
 183  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 184  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 185  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 186  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 187  *
 188  * Localbus cacheable (TBD)
 189  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 190  *
 191  * Localbus non-cacheable
 192  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 193  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 194  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 195  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 196  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 197  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 198  */
 199
 200 /*
 201  * Local Bus Definitions
 202  */
 203 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 204 #ifdef CONFIG_PHYS_64BIT
 205 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 206 #else
 207 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 208 #endif
 209
 210 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 211 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 212
 213 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 214 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 215
 216 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 217 #define CONFIG_SYS_FLASH_QUIET_TEST
 218 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 219
 220 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 221 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 222 #undef  CONFIG_SYS_FLASH_CHECKSUM
 223 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 224 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 225
 226 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 227
 228 #define CONFIG_FLASH_CFI_DRIVER
 229 #define CONFIG_SYS_FLASH_CFI
 230 #define CONFIG_SYS_FLASH_EMPTY_INFO
 231 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 232
 233 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 234
 235 #define CONFIG_FSL_NGPIXIS              /* use common ngPIXIS code */
 236
 237 #ifdef CONFIG_FSL_NGPIXIS
 238 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 241 #else
 242 #define PIXIS_BASE_PHYS PIXIS_BASE
 243 #endif
 244
 245 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 246 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 247
 248 #define PIXIS_LBMAP_SWITCH      7
 249 #define PIXIS_LBMAP_MASK        0xf0
 250 #define PIXIS_LBMAP_SHIFT       4
 251 #define PIXIS_LBMAP_ALTBANK     0x20
 252 #endif
 253
 254 #define CONFIG_SYS_INIT_RAM_LOCK        1
 255 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 256 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 257
 258 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 259 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 260 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 261
 262 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 263 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 264
 265 #define CONFIG_SYS_NAND_BASE            0xffa00000
 266 #ifdef CONFIG_PHYS_64BIT
 267 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 268 #else
 269 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 270 #endif
 271 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE,\
 272                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 273                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 274                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 275 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 276 #define CONFIG_MTD_NAND_VERIFY_WRITE
 277 #define CONFIG_CMD_NAND                 1
 278 #define CONFIG_NAND_FSL_ELBC            1
 279 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 280
 281 /* NAND flash config */
 282 #define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 283                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 284                                 | BR_PS_8               /* Port Size = 8bit */ \
 285                                 | BR_MS_FCM             /* MSEL = FCM */ \
 286                                 | BR_V)                 /* valid */
 287 #define CONFIG_NAND_OR_PRELIM  (0xFFFC0000              /* length 256K */ \
 288                                 | OR_FCM_PGS            /* Large Page*/ \
 289                                 | OR_FCM_CSCT \
 290                                 | OR_FCM_CST \
 291                                 | OR_FCM_CHT \
 292                                 | OR_FCM_SCY_1 \
 293                                 | OR_FCM_TRLX \
 294                                 | OR_FCM_EHTR)
 295
 296 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 297 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 298 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 299 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 300
 301 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 302                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 303                                 | BR_PS_8               /* Port Size = 8bit */ \
 304                                 | BR_MS_FCM             /* MSEL = FCM */ \
 305                                 | BR_V)                 /* valid */
 306 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 307 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 308                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 309                                 | BR_PS_8               /* Port Size = 8bit */ \
 310                                 | BR_MS_FCM             /* MSEL = FCM */ \
 311                                 | BR_V)                 /* valid */
 312 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 313
 314 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 315                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 316                                 | BR_PS_8               /* Port Size = 8bit */ \
 317                                 | BR_MS_FCM             /* MSEL = FCM */ \
 318                                 | BR_V)                 /* valid */
 319 #define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 320
 321 /* Serial Port - controlled on board with jumper J8
 322  * open - index 2
 323  * shorted - index 1
 324  */
 325 #define CONFIG_CONS_INDEX       1
 326 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 327 #define CONFIG_SYS_NS16550
 328 #define CONFIG_SYS_NS16550_SERIAL
 329 #define CONFIG_SYS_NS16550_REG_SIZE     1
 330 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 331
 332 #define CONFIG_SYS_BAUDRATE_TABLE       \
 333         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 334
 335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 337
 338 /* Use the HUSH parser */
 339 #define CONFIG_SYS_HUSH_PARSER
 340 #ifdef  CONFIG_SYS_HUSH_PARSER
 341 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 342 #endif
 343
 344 /*
 345  * Pass open firmware flat tree
 346  */
 347 #define CONFIG_OF_LIBFDT                1
 348 #define CONFIG_OF_BOARD_SETUP           1
 349 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 350
 351 /* I2C */
 352 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 353 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 354 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 355 #define CONFIG_I2C_MULTI_BUS
 356 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 357 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 358 #define CONFIG_SYS_I2C_SLAVE            0x7F
 359 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
 360 #define CONFIG_SYS_I2C_OFFSET           0x3000
 361 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 362
 363 /*
 364  * I2C2 EEPROM
 365  */
 366 #define CONFIG_ID_EEPROM
 367 #ifdef CONFIG_ID_EEPROM
 368 #define CONFIG_SYS_I2C_EEPROM_NXID
 369 #endif
 370 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 371 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 372 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 373
 374 /*
 375  * General PCI
 376  * Memory space is mapped 1-1, but I/O space must start from 0.
 377  */
 378
 379 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 380 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 381 #ifdef CONFIG_PHYS_64BIT
 382 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 383 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 384 #else
 385 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 386 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 387 #endif
 388 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 389 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 390 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 391 #ifdef CONFIG_PHYS_64BIT
 392 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 393 #else
 394 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 395 #endif
 396 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 397
 398 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 399 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 400 #ifdef CONFIG_PHYS_64BIT
 401 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 402 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 403 #else
 404 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 405 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 406 #endif
 407 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 408 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 409 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 410 #ifdef CONFIG_PHYS_64BIT
 411 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 412 #else
 413 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 414 #endif
 415 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 416
 417 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 418 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 419 #ifdef CONFIG_PHYS_64BIT
 420 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 421 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 422 #else
 423 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 424 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 425 #endif
 426 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 427 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 428 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 429 #ifdef CONFIG_PHYS_64BIT
 430 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 431 #else
 432 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 433 #endif
 434 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 435
 436 #if defined(CONFIG_PCI)
 437
 438 /*PCIE video card used*/
 439 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 440
 441 /* video */
 442 #define CONFIG_VIDEO
 443
 444 #if defined(CONFIG_VIDEO)
 445 #define CONFIG_BIOSEMU
 446 #define CONFIG_CFB_CONSOLE
 447 #define CONFIG_VIDEO_SW_CURSOR
 448 #define CONFIG_VGA_AS_SINGLE_DEVICE
 449 #define CONFIG_ATI_RADEON_FB
 450 #define CONFIG_VIDEO_LOGO
 451 /*#define CONFIG_CONSOLE_CURSOR*/
 452 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 453 #endif
 454
 455 #define CONFIG_NET_MULTI
 456 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 457
 458 #undef CONFIG_EEPRO100
 459 #undef CONFIG_TULIP
 460 #define CONFIG_RTL8139
 461
 462 #ifndef CONFIG_PCI_PNP
 463         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
 464         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
 465         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 466 #endif
 467
 468 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 469 #define CONFIG_DOS_PARTITION
 470 #define CONFIG_SCSI_AHCI
 471
 472 #ifdef CONFIG_SCSI_AHCI
 473 #define CONFIG_SATA_ULI5288
 474 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 475 #define CONFIG_SYS_SCSI_MAX_LUN 1
 476 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 477 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 478 #endif /* SCSI */
 479
 480 #endif  /* CONFIG_PCI */
 481
 482
 483 #if defined(CONFIG_TSEC_ENET)
 484
 485 #ifndef CONFIG_NET_MULTI
 486 #define CONFIG_NET_MULTI        1
 487 #endif
 488
 489 #define CONFIG_MII              1       /* MII PHY management */
 490 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 491 #define CONFIG_TSEC1    1
 492 #define CONFIG_TSEC1_NAME       "eTSEC1"
 493 #define CONFIG_TSEC2    1
 494 #define CONFIG_TSEC2_NAME       "eTSEC2"
 495 #define CONFIG_TSEC3    1
 496 #define CONFIG_TSEC3_NAME       "eTSEC3"
 497
 498 #define CONFIG_PIXIS_SGMII_CMD
 499 #define CONFIG_FSL_SGMII_RISER  1
 500 #define SGMII_RISER_PHY_OFFSET  0x1b
 501
 502 #ifdef CONFIG_FSL_SGMII_RISER
 503 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 504 #endif
 505
 506 #define TSEC1_PHY_ADDR          0
 507 #define TSEC2_PHY_ADDR          1
 508 #define TSEC3_PHY_ADDR          2
 509
 510 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 511 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 512 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 513
 514 #define TSEC1_PHYIDX            0
 515 #define TSEC2_PHYIDX            0
 516 #define TSEC3_PHYIDX            0
 517
 518 #define CONFIG_ETHPRIME         "eTSEC1"
 519
 520 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 521 #endif  /* CONFIG_TSEC_ENET */
 522
 523 /*
 524  * Environment
 525  */
 526 #define CONFIG_ENV_IS_IN_FLASH  1
 527 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 528 #define CONFIG_ENV_ADDR         0xfff80000
 529 #else
 530 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 531 #endif
 532 #define CONFIG_ENV_SIZE         0x2000
 533 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 534
 535 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 536 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 537
 538 /*
 539  * Command line configuration.
 540  */
 541 #include <config_cmd_default.h>
 542
 543 #define CONFIG_CMD_IRQ
 544 #define CONFIG_CMD_PING
 545 #define CONFIG_CMD_I2C
 546 #define CONFIG_CMD_MII
 547 #define CONFIG_CMD_ELF
 548 #define CONFIG_CMD_IRQ
 549 #define CONFIG_CMD_SETEXPR
 550 #define CONFIG_CMD_REGINFO
 551
 552 #if defined(CONFIG_PCI)
 553 #define CONFIG_CMD_PCI
 554 #define CONFIG_CMD_NET
 555 #define CONFIG_CMD_SCSI
 556 #define CONFIG_CMD_EXT2
 557 #endif
 558
 559 /*
 560  * USB
 561  */
 562 #define CONFIG_CMD_USB
 563 #define CONFIG_USB_STORAGE
 564 #define CONFIG_USB_EHCI
 565 #define CONFIG_USB_EHCI_FSL
 566 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 567
 568 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 569
 570 /*
 571  * Miscellaneous configurable options
 572  */
 573 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 574 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 575 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 576 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 577 #if defined(CONFIG_CMD_KGDB)
 578 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 579 #else
 580 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 581 #endif
 582 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 583 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 584 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 585 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 586
 587 /*
 588  * For booting Linux, the board info and command line data
 589  * have to be in the first 16 MB of memory, since this is
 590  * the maximum mapped by the Linux kernel during initialization.
 591  */
 592 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 593
 594 /*
 595  * Internal Definitions
 596  *
 597  * Boot Flags
 598  */
 599 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 600 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 601
 602 #if defined(CONFIG_CMD_KGDB)
 603 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 604 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 605 #endif
 606
 607 /*
 608  * Environment Configuration
 609  */
 610
 611 /* The mac addresses for all ethernet interface */
 612 #if defined(CONFIG_TSEC_ENET)
 613 #define CONFIG_HAS_ETH0
 614 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 615 #define CONFIG_HAS_ETH1
 616 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 617 #define CONFIG_HAS_ETH2
 618 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 619 #define CONFIG_HAS_ETH3
 620 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 621 #endif
 622
 623 #define CONFIG_IPADDR           192.168.1.254
 624
 625 #define CONFIG_HOSTNAME         unknown
 626 #define CONFIG_ROOTPATH         /opt/nfsroot
 627 #define CONFIG_BOOTFILE         uImage
 628 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 629
 630 #define CONFIG_SERVERIP         192.168.1.1
 631 #define CONFIG_GATEWAYIP        192.168.1.1
 632 #define CONFIG_NETMASK          255.255.255.0
 633
 634 /* default location for tftp and bootm */
 635 #define CONFIG_LOADADDR         1000000
 636
 637 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 638 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 639
 640 #define CONFIG_BAUDRATE 115200
 641
 642 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 643  "perf_mode=stable\0"                   \
 644  "memctl_intlv_ctl=2\0"                                         \
 645  "netdev=eth0\0"                                                \
 646  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 647  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 648         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 649         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 650         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 651         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 652         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 653  "consoledev=ttyS0\0"                           \
 654  "ramdiskaddr=2000000\0"                        \
 655  "ramdiskfile=p2020ds/ramdisk.uboot\0"          \
 656  "fdtaddr=c00000\0"                             \
 657  "fdtfile=p2020ds/p2020ds.dtb\0"                \
 658  "bdev=sda3\0"
 659
 660 #define CONFIG_HDBOOT                           \
 661  "setenv bootargs root=/dev/$bdev rw "          \
 662  "console=$consoledev,$baudrate $othbootargs;"  \
 663  "tftp $loadaddr $bootfile;"                    \
 664  "tftp $fdtaddr $fdtfile;"                      \
 665  "bootm $loadaddr - $fdtaddr"
 666
 667 #define CONFIG_NFSBOOTCOMMAND           \
 668  "setenv bootargs root=/dev/nfs rw "    \
 669  "nfsroot=$serverip:$rootpath "         \
 670  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 671  "console=$consoledev,$baudrate $othbootargs;"  \
 672  "tftp $loadaddr $bootfile;"            \
 673  "tftp $fdtaddr $fdtfile;"              \
 674  "bootm $loadaddr - $fdtaddr"
 675
 676 #define CONFIG_RAMBOOTCOMMAND           \
 677  "setenv bootargs root=/dev/ram rw "    \
 678  "console=$consoledev,$baudrate $othbootargs;"  \
 679  "tftp $ramdiskaddr $ramdiskfile;"      \
 680  "tftp $loadaddr $bootfile;"            \
 681  "tftp $fdtaddr $fdtfile;"              \
 682  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 683
 684 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 685
 686 #endif  /* __CONFIG_H */