include/configs/P2020DS.h

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * p2020ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_MK_36BIT
  33 #define CONFIG_PHYS_64BIT
  34 #endif
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_BOOKE            1       /* BOOKE */
  38 #define CONFIG_E500             1       /* BOOKE e500 family */
  39 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  40 #define CONFIG_P2020            1
  41 #define CONFIG_P2020DS          1
  42 #define CONFIG_MP               1       /* support multiple processors */
  43
  44 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  45 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  46 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  47 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  48 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  49 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  50 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  51 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  52
  53 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  54 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  55
  56 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  57 #define CONFIG_ENV_OVERWRITE
  58
  59 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  60 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
  61 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  67 #define CONFIG_BTB                      /* toggle branch predition */
  68
  69 #define CONFIG_ENABLE_36BIT_PHYS        1
  70
  71 #ifdef CONFIG_PHYS_64BIT
  72 #define CONFIG_ADDR_MAP                 1
  73 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  74 #endif
  75
  76 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  77 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  78 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  79
  80 /*
  81  * Base addresses -- Note these are effective addresses where the
  82  * actual resources get mapped (not physical addresses)
  83  */
  84 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  85 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_SYS_CCSRBAR_PHYS         0xfffe00000ull  /* physical addr of CCSRBAR */
  88 #else
  89 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  90 #endif
  91 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  92
  93 /* DDR Setup */
  94 #define CONFIG_VERY_BIG_RAM
  95 #ifdef CONFIG_MK_DDR2
  96 #define CONFIG_FSL_DDR2
  97 #else
  98 #define CONFIG_FSL_DDR3         1
  99 #endif
 100 #undef CONFIG_FSL_DDR_INTERACTIVE
 101
 102 /* ECC will be enabled based on perf_mode environment variable */
 103 /* #define      CONFIG_DDR_ECC */
 104
 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 106 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 107
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 109 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 110
 111 #define CONFIG_NUM_DDR_CONTROLLERS      1
 112 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 113 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 114
 115 /* I2C addresses of SPD EEPROMs */
 116 #define CONFIG_DDR_SPD
 117 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD EEPROM located on I2C bus 0 */
 118 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 119
 120 /* These are used when DDR doesn't use SPD.  */
 121 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1GB */
 122
 123 /* Default settings for "stable" mode */
 124 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 125 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
 126 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 127 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
 128 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 129 #define CONFIG_SYS_DDR_TIMING_0         0x00330804
 130 #define CONFIG_SYS_DDR_TIMING_1         0x6f6b4846
 131 #define CONFIG_SYS_DDR_TIMING_2         0x0fa890d4
 132 #define CONFIG_SYS_DDR_MODE_1           0x00421422
 133 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 134 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
 135 #define CONFIG_SYS_DDR_INTERVAL         0x61800100
 136 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 137 #define CONFIG_SYS_DDR_CLK_CTRL         0x02000000
 138 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 139 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 140 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 141 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8655A608
 142 #define CONFIG_SYS_DDR_CONTROL          0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
 143 #define CONFIG_SYS_DDR_CONTROL2         0x24400011
 144 #define CONFIG_SYS_DDR_CDR1             0x00040000
 145 #define CONFIG_SYS_DDR_CDR2             0x00000000
 146
 147 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 148 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 149 #define CONFIG_SYS_DDR_SBE              0x00010000
 150
 151 /* Settings that differ for "performance" mode */
 152 #define CONFIG_SYS_DDR_CS0_BNDS_PERF            0x0000007F /* Interleaving Enabled */
 153 #define CONFIG_SYS_DDR_CS1_BNDS_PERF            0x00000000 /* Interleaving Enabled */
 154 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014202
 155 #define CONFIG_SYS_DDR_TIMING_1_PERF            0x5d5b4543
 156 #define CONFIG_SYS_DDR_TIMING_2_PERF            0x0fa890ce
 157 #define CONFIG_SYS_DDR_CONTROL_PERF             0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
 158
 159 /*
 160  * The following set of values were tested for DDR2
 161  * with a DDR3 to DDR2 interposer
 162  *
 163 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 164 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 165 #define CONFIG_SYS_DDR_TIMING_1         0x3935d322
 166 #define CONFIG_SYS_DDR_TIMING_2         0x14904cc8
 167 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 168 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 169 #define CONFIG_SYS_DDR_INTERVAL         0x06180100
 170 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 171 #define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
 172 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 173 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 174 #define CONFIG_SYS_DDR_CONTROL          0xC3008000
 175 #define CONFIG_SYS_DDR_CONTROL2         0x04400010
 176  *
 177  */
 178
 179 #undef CONFIG_CLOCKS_IN_MHZ
 180
 181 /*
 182  * Memory map
 183  *
 184  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 185  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 186  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 187  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 188  *
 189  * Localbus cacheable (TBD)
 190  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 191  *
 192  * Localbus non-cacheable
 193  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 194  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 195  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 196  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 197  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 198  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 199  */
 200
 201 /*
 202  * Local Bus Definitions
 203  */
 204 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 205 #ifdef CONFIG_PHYS_64BIT
 206 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 207 #else
 208 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 209 #endif
 210
 211 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 212 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 213
 214 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 215 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 216
 217 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 218 #define CONFIG_SYS_FLASH_QUIET_TEST
 219 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 220
 221 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 222 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 223 #undef  CONFIG_SYS_FLASH_CHECKSUM
 224 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 225 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 226
 227 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 228
 229 #define CONFIG_FLASH_CFI_DRIVER
 230 #define CONFIG_SYS_FLASH_CFI
 231 #define CONFIG_SYS_FLASH_EMPTY_INFO
 232 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 233
 234 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 235
 236 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 237 #define CONFIG_FSL_NGPIXIS              /* use common ngPIXIS code */
 238
 239 #ifdef CONFIG_FSL_NGPIXIS
 240 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 243 #else
 244 #define PIXIS_BASE_PHYS PIXIS_BASE
 245 #endif
 246
 247 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 248 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 249
 250 #define PIXIS_LBMAP_SWITCH      7
 251 #define PIXIS_LBMAP_MASK        0xf0
 252 #define PIXIS_LBMAP_SHIFT       4
 253 #define PIXIS_LBMAP_ALTBANK     0x20
 254 #endif
 255
 256 #define CONFIG_SYS_INIT_RAM_LOCK        1
 257 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 258 #ifdef CONFIG_PHYS_64BIT
 259 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 260 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 261 /* The assembler doesn't like typecast */
 262 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 263         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 264           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 265 #else
 266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 267 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 269 #endif
 270 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 271
 272 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 273 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 274 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 275
 276 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 277 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 278
 279 #define CONFIG_SYS_NAND_BASE            0xffa00000
 280 #ifdef CONFIG_PHYS_64BIT
 281 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 282 #else
 283 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 284 #endif
 285 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE,\
 286                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 287                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 288                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 289 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 290 #define CONFIG_MTD_NAND_VERIFY_WRITE
 291 #define CONFIG_CMD_NAND                 1
 292 #define CONFIG_NAND_FSL_ELBC            1
 293 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 294
 295 /* NAND flash config */
 296 #define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 297                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 298                                 | BR_PS_8               /* Port Size = 8bit */ \
 299                                 | BR_MS_FCM             /* MSEL = FCM */ \
 300                                 | BR_V)                 /* valid */
 301 #define CONFIG_NAND_OR_PRELIM  (0xFFFC0000              /* length 256K */ \
 302                                 | OR_FCM_PGS            /* Large Page*/ \
 303                                 | OR_FCM_CSCT \
 304                                 | OR_FCM_CST \
 305                                 | OR_FCM_CHT \
 306                                 | OR_FCM_SCY_1 \
 307                                 | OR_FCM_TRLX \
 308                                 | OR_FCM_EHTR)
 309
 310 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 311 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 312 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 313 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 314
 315 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 316                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 317                                 | BR_PS_8               /* Port Size = 8bit */ \
 318                                 | BR_MS_FCM             /* MSEL = FCM */ \
 319                                 | BR_V)                 /* valid */
 320 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 321 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 322                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 323                                 | BR_PS_8               /* Port Size = 8bit */ \
 324                                 | BR_MS_FCM             /* MSEL = FCM */ \
 325                                 | BR_V)                 /* valid */
 326 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 327
 328 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 329                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 330                                 | BR_PS_8               /* Port Size = 8bit */ \
 331                                 | BR_MS_FCM             /* MSEL = FCM */ \
 332                                 | BR_V)                 /* valid */
 333 #define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 334
 335 /* Serial Port - controlled on board with jumper J8
 336  * open - index 2
 337  * shorted - index 1
 338  */
 339 #define CONFIG_CONS_INDEX       1
 340 #define CONFIG_SYS_NS16550
 341 #define CONFIG_SYS_NS16550_SERIAL
 342 #define CONFIG_SYS_NS16550_REG_SIZE     1
 343 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 344
 345 #define CONFIG_SYS_BAUDRATE_TABLE       \
 346         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 347
 348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 349 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 350
 351 /* Use the HUSH parser */
 352 #define CONFIG_SYS_HUSH_PARSER
 353 #ifdef  CONFIG_SYS_HUSH_PARSER
 354 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 355 #endif
 356
 357 /*
 358  * Pass open firmware flat tree
 359  */
 360 #define CONFIG_OF_LIBFDT                1
 361 #define CONFIG_OF_BOARD_SETUP           1
 362 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 363
 364 /* I2C */
 365 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 366 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 367 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 368 #define CONFIG_I2C_MULTI_BUS
 369 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 370 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 371 #define CONFIG_SYS_I2C_SLAVE            0x7F
 372 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
 373 #define CONFIG_SYS_I2C_OFFSET           0x3000
 374 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 375
 376 /*
 377  * I2C2 EEPROM
 378  */
 379 #define CONFIG_ID_EEPROM
 380 #ifdef CONFIG_ID_EEPROM
 381 #define CONFIG_SYS_I2C_EEPROM_NXID
 382 #endif
 383 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 384 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 385 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 386
 387 /*
 388  * General PCI
 389  * Memory space is mapped 1-1, but I/O space must start from 0.
 390  */
 391
 392 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 393 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 394 #ifdef CONFIG_PHYS_64BIT
 395 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 396 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 397 #else
 398 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 399 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 400 #endif
 401 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 402 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 403 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 406 #else
 407 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 408 #endif
 409 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 410
 411 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 412 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 413 #ifdef CONFIG_PHYS_64BIT
 414 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 415 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 416 #else
 417 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 418 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 419 #endif
 420 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 421 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 422 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 423 #ifdef CONFIG_PHYS_64BIT
 424 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 425 #else
 426 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 427 #endif
 428 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 429
 430 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 431 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 432 #ifdef CONFIG_PHYS_64BIT
 433 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 434 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 435 #else
 436 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 437 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 438 #endif
 439 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 440 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 441 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 442 #ifdef CONFIG_PHYS_64BIT
 443 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 444 #else
 445 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 446 #endif
 447 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 448
 449 #if defined(CONFIG_PCI)
 450
 451 /*PCIE video card used*/
 452 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 453
 454 /* video */
 455 #define CONFIG_VIDEO
 456
 457 #if defined(CONFIG_VIDEO)
 458 #define CONFIG_BIOSEMU
 459 #define CONFIG_CFB_CONSOLE
 460 #define CONFIG_VIDEO_SW_CURSOR
 461 #define CONFIG_VGA_AS_SINGLE_DEVICE
 462 #define CONFIG_ATI_RADEON_FB
 463 #define CONFIG_VIDEO_LOGO
 464 /*#define CONFIG_CONSOLE_CURSOR*/
 465 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 466 #endif
 467
 468 #define CONFIG_NET_MULTI
 469 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 470
 471 #undef CONFIG_EEPRO100
 472 #undef CONFIG_TULIP
 473 #define CONFIG_RTL8139
 474
 475 #ifndef CONFIG_PCI_PNP
 476         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
 477         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
 478         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 479 #endif
 480
 481 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 482 #define CONFIG_DOS_PARTITION
 483 #define CONFIG_SCSI_AHCI
 484
 485 #ifdef CONFIG_SCSI_AHCI
 486 #define CONFIG_SATA_ULI5288
 487 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 488 #define CONFIG_SYS_SCSI_MAX_LUN 1
 489 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 490 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 491 #endif /* SCSI */
 492
 493 #endif  /* CONFIG_PCI */
 494
 495
 496 #if defined(CONFIG_TSEC_ENET)
 497
 498 #ifndef CONFIG_NET_MULTI
 499 #define CONFIG_NET_MULTI        1
 500 #endif
 501
 502 #define CONFIG_MII              1       /* MII PHY management */
 503 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 504 #define CONFIG_TSEC1    1
 505 #define CONFIG_TSEC1_NAME       "eTSEC1"
 506 #define CONFIG_TSEC2    1
 507 #define CONFIG_TSEC2_NAME       "eTSEC2"
 508 #define CONFIG_TSEC3    1
 509 #define CONFIG_TSEC3_NAME       "eTSEC3"
 510
 511 #define CONFIG_PIXIS_SGMII_CMD
 512 #define CONFIG_FSL_SGMII_RISER  1
 513 #define SGMII_RISER_PHY_OFFSET  0x1b
 514
 515 #ifdef CONFIG_FSL_SGMII_RISER
 516 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 517 #endif
 518
 519 #define TSEC1_PHY_ADDR          0
 520 #define TSEC2_PHY_ADDR          1
 521 #define TSEC3_PHY_ADDR          2
 522
 523 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 524 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 525 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 526
 527 #define TSEC1_PHYIDX            0
 528 #define TSEC2_PHYIDX            0
 529 #define TSEC3_PHYIDX            0
 530
 531 #define CONFIG_ETHPRIME         "eTSEC1"
 532
 533 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 534 #endif  /* CONFIG_TSEC_ENET */
 535
 536 /*
 537  * Environment
 538  */
 539 #define CONFIG_ENV_IS_IN_FLASH  1
 540 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 541 #define CONFIG_ENV_ADDR         0xfff80000
 542 #else
 543 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 544 #endif
 545 #define CONFIG_ENV_SIZE         0x2000
 546 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 547
 548 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 549 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 550
 551 /*
 552  * Command line configuration.
 553  */
 554 #include <config_cmd_default.h>
 555
 556 #define CONFIG_CMD_IRQ
 557 #define CONFIG_CMD_PING
 558 #define CONFIG_CMD_I2C
 559 #define CONFIG_CMD_MII
 560 #define CONFIG_CMD_ELF
 561 #define CONFIG_CMD_IRQ
 562 #define CONFIG_CMD_SETEXPR
 563 #define CONFIG_CMD_REGINFO
 564
 565 #if defined(CONFIG_PCI)
 566 #define CONFIG_CMD_PCI
 567 #define CONFIG_CMD_NET
 568 #define CONFIG_CMD_SCSI
 569 #define CONFIG_CMD_EXT2
 570 #endif
 571
 572 /*
 573  * USB
 574  */
 575 #define CONFIG_CMD_USB
 576 #define CONFIG_USB_STORAGE
 577 #define CONFIG_USB_EHCI
 578 #define CONFIG_USB_EHCI_FSL
 579 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 580
 581 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 582
 583 /*
 584  * Miscellaneous configurable options
 585  */
 586 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 587 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 588 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 589 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 590 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 591 #if defined(CONFIG_CMD_KGDB)
 592 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 593 #else
 594 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 595 #endif
 596 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 597 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 598 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 599 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 600
 601 /*
 602  * For booting Linux, the board info and command line data
 603  * have to be in the first 16 MB of memory, since this is
 604  * the maximum mapped by the Linux kernel during initialization.
 605  */
 606 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 607
 608 /*
 609  * Internal Definitions
 610  *
 611  * Boot Flags
 612  */
 613 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 614 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 615
 616 #if defined(CONFIG_CMD_KGDB)
 617 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 618 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 619 #endif
 620
 621 /*
 622  * Environment Configuration
 623  */
 624
 625 /* The mac addresses for all ethernet interface */
 626 #if defined(CONFIG_TSEC_ENET)
 627 #define CONFIG_HAS_ETH0
 628 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 629 #define CONFIG_HAS_ETH1
 630 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 631 #define CONFIG_HAS_ETH2
 632 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 633 #define CONFIG_HAS_ETH3
 634 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 635 #endif
 636
 637 #define CONFIG_IPADDR           192.168.1.254
 638
 639 #define CONFIG_HOSTNAME         unknown
 640 #define CONFIG_ROOTPATH         /opt/nfsroot
 641 #define CONFIG_BOOTFILE         uImage
 642 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 643
 644 #define CONFIG_SERVERIP         192.168.1.1
 645 #define CONFIG_GATEWAYIP        192.168.1.1
 646 #define CONFIG_NETMASK          255.255.255.0
 647
 648 /* default location for tftp and bootm */
 649 #define CONFIG_LOADADDR         1000000
 650
 651 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 652 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 653
 654 #define CONFIG_BAUDRATE 115200
 655
 656 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 657  "perf_mode=stable\0"                   \
 658  "memctl_intlv_ctl=2\0"                                         \
 659  "netdev=eth0\0"                                                \
 660  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 661  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 662         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 663         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 664         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 665         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 666         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 667  "consoledev=ttyS0\0"                           \
 668  "ramdiskaddr=2000000\0"                        \
 669  "ramdiskfile=p2020ds/ramdisk.uboot\0"          \
 670  "fdtaddr=c00000\0"                             \
 671  "fdtfile=p2020ds/p2020ds.dtb\0"                \
 672  "bdev=sda3\0"
 673
 674 #define CONFIG_HDBOOT                           \
 675  "setenv bootargs root=/dev/$bdev rw "          \
 676  "console=$consoledev,$baudrate $othbootargs;"  \
 677  "tftp $loadaddr $bootfile;"                    \
 678  "tftp $fdtaddr $fdtfile;"                      \
 679  "bootm $loadaddr - $fdtaddr"
 680
 681 #define CONFIG_NFSBOOTCOMMAND           \
 682  "setenv bootargs root=/dev/nfs rw "    \
 683  "nfsroot=$serverip:$rootpath "         \
 684  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 685  "console=$consoledev,$baudrate $othbootargs;"  \
 686  "tftp $loadaddr $bootfile;"            \
 687  "tftp $fdtaddr $fdtfile;"              \
 688  "bootm $loadaddr - $fdtaddr"
 689
 690 #define CONFIG_RAMBOOTCOMMAND           \
 691  "setenv bootargs root=/dev/ram rw "    \
 692  "console=$consoledev,$baudrate $othbootargs;"  \
 693  "tftp $ramdiskaddr $ramdiskfile;"      \
 694  "tftp $loadaddr $bootfile;"            \
 695  "tftp $fdtaddr $fdtfile;"              \
 696  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 697
 698 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 699
 700 #endif  /* __CONFIG_H */