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[people/ms/u-boot.git] / include / configs / P2041RDB.h
1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_P2041RDB
15 #define CONFIG_PHYS_64BIT
16 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_PPC_P2041
18
19 #ifdef CONFIG_RAMBOOT_PBL
20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
24 #endif
25
26 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
27 /* Set 1M boot space */
28 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
29 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
30 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
32 #define CONFIG_SYS_NO_FLASH
33 #endif
34
35 /* High Level Configuration Options */
36 #define CONFIG_BOOKE
37 #define CONFIG_E500 /* BOOKE e500 family */
38 #define CONFIG_E500MC /* BOOKE e500mc family */
39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
40 #define CONFIG_MP /* support multiple processors */
41
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE 0xeff40000
44 #endif
45
46 #ifndef CONFIG_RESET_VECTOR_ADDRESS
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48 #endif
49
50 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
51 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
52 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
53 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
54 #define CONFIG_PCI /* Enable PCI/PCIE */
55 #define CONFIG_PCIE1 /* PCIE controler 1 */
56 #define CONFIG_PCIE2 /* PCIE controler 2 */
57 #define CONFIG_PCIE3 /* PCIE controler 3 */
58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
59 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
60
61 #define CONFIG_SYS_SRIO
62 #define CONFIG_SRIO1 /* SRIO port 1 */
63 #define CONFIG_SRIO2 /* SRIO port 2 */
64 #define CONFIG_SRIO_PCIE_BOOT_MASTER
65 #define CONFIG_SYS_DPAA_RMAN /* RMan */
66
67 #define CONFIG_FSL_LAW /* Use common FSL init code */
68
69 #define CONFIG_ENV_OVERWRITE
70
71 #ifdef CONFIG_SYS_NO_FLASH
72 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
73 #define CONFIG_ENV_IS_NOWHERE
74 #endif
75 #else
76 #define CONFIG_FLASH_CFI_DRIVER
77 #define CONFIG_SYS_FLASH_CFI
78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
79 #endif
80
81 #if defined(CONFIG_SPIFLASH)
82 #define CONFIG_SYS_EXTRA_ENV_RELOC
83 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 #define CONFIG_ENV_SPI_BUS 0
85 #define CONFIG_ENV_SPI_CS 0
86 #define CONFIG_ENV_SPI_MAX_HZ 10000000
87 #define CONFIG_ENV_SPI_MODE 0
88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
90 #define CONFIG_ENV_SECT_SIZE 0x10000
91 #elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_MMC
94 #define CONFIG_FSL_FIXED_MMC_LOCATION
95 #define CONFIG_SYS_MMC_ENV_DEV 0
96 #define CONFIG_ENV_SIZE 0x2000
97 #define CONFIG_ENV_OFFSET (512 * 1658)
98 #elif defined(CONFIG_NAND)
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_ENV_IS_IN_NAND
101 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
102 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
104 #define CONFIG_ENV_IS_IN_REMOTE
105 #define CONFIG_ENV_ADDR 0xffe20000
106 #define CONFIG_ENV_SIZE 0x2000
107 #elif defined(CONFIG_ENV_IS_NOWHERE)
108 #define CONFIG_ENV_SIZE 0x2000
109 #else
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
112 - CONFIG_ENV_SECT_SIZE)
113 #define CONFIG_ENV_SIZE 0x2000
114 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
115 #endif
116
117 #ifndef __ASSEMBLY__
118 unsigned long get_board_sys_clk(unsigned long dummy);
119 #endif
120 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
121
122 /*
123 * These can be toggled for performance analysis, otherwise use default.
124 */
125 #define CONFIG_SYS_CACHE_STASHING
126 #define CONFIG_BACKSIDE_L2_CACHE
127 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
128 #define CONFIG_BTB /* toggle branch predition */
129
130 #define CONFIG_ENABLE_36BIT_PHYS
131
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_ADDR_MAP
134 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
135 #endif
136
137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END 0x00400000
140 #define CONFIG_SYS_ALT_MEMTEST
141 #define CONFIG_PANIC_HANG /* do not reset board on panic */
142
143 /*
144 * Config the L3 Cache as L3 SRAM
145 */
146 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
149 CONFIG_RAMBOOT_TEXT_BASE)
150 #else
151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
152 #endif
153 #define CONFIG_SYS_L3_SIZE (1024 << 10)
154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
155
156 #ifdef CONFIG_PHYS_64BIT
157 #define CONFIG_SYS_DCSRBAR 0xf0000000
158 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
159 #endif
160
161 /* EEPROM */
162 #define CONFIG_ID_EEPROM
163 #define CONFIG_SYS_I2C_EEPROM_NXID
164 #define CONFIG_SYS_EEPROM_BUS_NUM 0
165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167
168 /*
169 * DDR Setup
170 */
171 #define CONFIG_VERY_BIG_RAM
172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
174
175 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
176 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
177
178 #define CONFIG_DDR_SPD
179 #define CONFIG_SYS_FSL_DDR3
180
181 #define CONFIG_SYS_SPD_BUS_NUM 0
182 #define SPD_EEPROM_ADDRESS 0x52
183 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
184
185 /*
186 * Local Bus Definitions
187 */
188
189 /* Set the local bus clock 1/8 of platform clock */
190 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
191
192 /*
193 * This board doesn't have a promjet connector.
194 * However, it uses commone corenet board LAW and TLB.
195 * It is necessary to use the same start address with proper offset.
196 */
197 #define CONFIG_SYS_FLASH_BASE 0xe0000000
198 #ifdef CONFIG_PHYS_64BIT
199 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
200 #else
201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
202 #endif
203
204 #define CONFIG_SYS_FLASH_BR_PRELIM \
205 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
206 BR_PS_16 | BR_V)
207 #define CONFIG_SYS_FLASH_OR_PRELIM \
208 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
209 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
210
211 #define CONFIG_FSL_CPLD
212 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
213 #ifdef CONFIG_PHYS_64BIT
214 #define CPLD_BASE_PHYS 0xfffdf0000ull
215 #else
216 #define CPLD_BASE_PHYS CPLD_BASE
217 #endif
218
219 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
220 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
221
222 #define PIXIS_LBMAP_SWITCH 7
223 #define PIXIS_LBMAP_MASK 0xf0
224 #define PIXIS_LBMAP_SHIFT 4
225 #define PIXIS_LBMAP_ALTBANK 0x40
226
227 #define CONFIG_SYS_FLASH_QUIET_TEST
228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
229
230 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
232 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
233 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
234
235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
236
237 #if defined(CONFIG_RAMBOOT_PBL)
238 #define CONFIG_SYS_RAMBOOT
239 #endif
240
241 #define CONFIG_NAND_FSL_ELBC
242 /* Nand Flash */
243 #ifdef CONFIG_NAND_FSL_ELBC
244 #define CONFIG_SYS_NAND_BASE 0xffa00000
245 #ifdef CONFIG_PHYS_64BIT
246 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
247 #else
248 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
249 #endif
250
251 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
252 #define CONFIG_SYS_MAX_NAND_DEVICE 1
253 #define CONFIG_CMD_NAND
254 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
255
256 /* NAND flash config */
257 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
258 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
259 | BR_PS_8 /* Port Size = 8 bit */ \
260 | BR_MS_FCM /* MSEL = FCM */ \
261 | BR_V) /* valid */
262 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
263 | OR_FCM_PGS /* Large Page*/ \
264 | OR_FCM_CSCT \
265 | OR_FCM_CST \
266 | OR_FCM_CHT \
267 | OR_FCM_SCY_1 \
268 | OR_FCM_TRLX \
269 | OR_FCM_EHTR)
270
271 #ifdef CONFIG_NAND
272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
274 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
275 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
276 #else
277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
279 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
280 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
281 #endif
282 #else
283 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
284 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
285 #endif /* CONFIG_NAND_FSL_ELBC */
286
287 #define CONFIG_SYS_FLASH_EMPTY_INFO
288 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
289 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
290
291 #define CONFIG_BOARD_EARLY_INIT_F
292 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
293 #define CONFIG_MISC_INIT_R
294
295 #define CONFIG_HWCONFIG
296
297 /* define to use L1 as initial stack */
298 #define CONFIG_L1_INIT_RAM
299 #define CONFIG_SYS_INIT_RAM_LOCK
300 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
301 #ifdef CONFIG_PHYS_64BIT
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
304 /* The assembler doesn't like typecast */
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
306 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
307 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
308 #else
309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
312 #endif
313 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
314
315 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
316 GENERATED_GBL_DATA_SIZE)
317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
318
319 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
320 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
321
322 /* Serial Port - controlled on board with jumper J8
323 * open - index 2
324 * shorted - index 1
325 */
326 #define CONFIG_CONS_INDEX 1
327 #define CONFIG_SYS_NS16550
328 #define CONFIG_SYS_NS16550_SERIAL
329 #define CONFIG_SYS_NS16550_REG_SIZE 1
330 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
331
332 #define CONFIG_SYS_BAUDRATE_TABLE \
333 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
334
335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
337 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
338 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
339
340 /* Use the HUSH parser */
341 #define CONFIG_SYS_HUSH_PARSER
342
343 /* pass open firmware flat tree */
344 #define CONFIG_OF_LIBFDT
345 #define CONFIG_OF_BOARD_SETUP
346 #define CONFIG_OF_STDOUT_VIA_ALIAS
347
348 /* new uImage format support */
349 #define CONFIG_FIT
350 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
351
352 /* I2C */
353 #define CONFIG_SYS_I2C
354 #define CONFIG_SYS_I2C_FSL
355 #define CONFIG_SYS_FSL_I2C_SPEED 400000
356 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
357 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
358 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
359 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
360 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
361
362 /*
363 * RapidIO
364 */
365 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
366 #ifdef CONFIG_PHYS_64BIT
367 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
368 #else
369 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
370 #endif
371 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
372
373 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
374 #ifdef CONFIG_PHYS_64BIT
375 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
376 #else
377 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
378 #endif
379 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
380
381 /*
382 * for slave u-boot IMAGE instored in master memory space,
383 * PHYS must be aligned based on the SIZE
384 */
385 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
389 /*
390 * for slave UCODE and ENV instored in master memory space,
391 * PHYS must be aligned based on the SIZE
392 */
393 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
394 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
395 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
396
397 /* slave core release by master*/
398 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
399 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
400
401 /*
402 * SRIO_PCIE_BOOT - SLAVE
403 */
404 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
405 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
406 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
407 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
408 #endif
409
410 /*
411 * eSPI - Enhanced SPI
412 */
413 #define CONFIG_FSL_ESPI
414 #define CONFIG_SPI_FLASH_SPANSION
415 #define CONFIG_CMD_SF
416 #define CONFIG_SF_DEFAULT_SPEED 10000000
417 #define CONFIG_SF_DEFAULT_MODE 0
418
419 /*
420 * General PCI
421 * Memory space is mapped 1-1, but I/O space must start from 0.
422 */
423
424 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
426 #ifdef CONFIG_PHYS_64BIT
427 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
429 #else
430 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
432 #endif
433 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
434 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
435 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
438 #else
439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
440 #endif
441 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
442
443 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
444 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
445 #ifdef CONFIG_PHYS_64BIT
446 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
447 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
448 #else
449 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
450 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
451 #endif
452 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
453 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
454 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455 #ifdef CONFIG_PHYS_64BIT
456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
457 #else
458 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
459 #endif
460 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
461
462 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
463 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
464 #ifdef CONFIG_PHYS_64BIT
465 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
466 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
467 #else
468 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
469 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
470 #endif
471 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
472 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
473 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
474 #ifdef CONFIG_PHYS_64BIT
475 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
476 #else
477 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
478 #endif
479 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
480
481 /* Qman/Bman */
482 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
483 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
484 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
485 #ifdef CONFIG_PHYS_64BIT
486 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
487 #else
488 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
489 #endif
490 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
491 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
492 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
493 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
494 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
495 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
496 CONFIG_SYS_BMAN_CENA_SIZE)
497 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
498 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
499 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
500 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
501 #ifdef CONFIG_PHYS_64BIT
502 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
503 #else
504 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
505 #endif
506 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
507 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
508 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
509 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
510 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
511 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
512 CONFIG_SYS_QMAN_CENA_SIZE)
513 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
514 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
515
516 #define CONFIG_SYS_DPAA_FMAN
517 #define CONFIG_SYS_DPAA_PME
518 /* Default address of microcode for the Linux Fman driver */
519 #if defined(CONFIG_SPIFLASH)
520 /*
521 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
522 * env, so we got 0x110000.
523 */
524 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
525 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
526 #elif defined(CONFIG_SDCARD)
527 /*
528 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
529 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
530 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
531 */
532 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
533 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
534 #elif defined(CONFIG_NAND)
535 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
536 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
537 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
538 /*
539 * Slave has no ucode locally, it can fetch this from remote. When implementing
540 * in two corenet boards, slave's ucode could be stored in master's memory
541 * space, the address can be mapped from slave TLB->slave LAW->
542 * slave SRIO or PCIE outbound window->master inbound window->
543 * master LAW->the ucode address in master's memory space.
544 */
545 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
546 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
547 #else
548 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
549 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
550 #endif
551 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
552 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
553
554 #ifdef CONFIG_SYS_DPAA_FMAN
555 #define CONFIG_FMAN_ENET
556 #define CONFIG_PHYLIB_10G
557 #define CONFIG_PHY_VITESSE
558 #define CONFIG_PHY_TERANETICS
559 #endif
560
561 #ifdef CONFIG_PCI
562 #define CONFIG_PCI_INDIRECT_BRIDGE
563 #define CONFIG_PCI_PNP /* do pci plug-and-play */
564
565 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
566 #define CONFIG_DOS_PARTITION
567 #endif /* CONFIG_PCI */
568
569 /* SATA */
570 #define CONFIG_FSL_SATA_V2
571
572 #ifdef CONFIG_FSL_SATA_V2
573 #define CONFIG_FSL_SATA
574 #define CONFIG_LIBATA
575
576 #define CONFIG_SYS_SATA_MAX_DEVICE 2
577 #define CONFIG_SATA1
578 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
579 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
580 #define CONFIG_SATA2
581 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
582 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
583
584 #define CONFIG_LBA48
585 #define CONFIG_CMD_SATA
586 #define CONFIG_DOS_PARTITION
587 #define CONFIG_CMD_EXT2
588 #endif
589
590 #ifdef CONFIG_FMAN_ENET
591 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
592 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
593 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
594 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
595 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
596
597 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
598 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
599 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
600 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
601
602 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
603
604 #define CONFIG_SYS_TBIPA_VALUE 8
605 #define CONFIG_MII /* MII PHY management */
606 #define CONFIG_ETHPRIME "FM1@DTSEC1"
607 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
608 #endif
609
610 /*
611 * Environment
612 */
613 #define CONFIG_LOADS_ECHO /* echo on for serial download */
614 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
615
616 /*
617 * Command line configuration.
618 */
619 #define CONFIG_CMD_DHCP
620 #define CONFIG_CMD_ERRATA
621 #define CONFIG_CMD_GREPENV
622 #define CONFIG_CMD_IRQ
623 #define CONFIG_CMD_I2C
624 #define CONFIG_CMD_MII
625 #define CONFIG_CMD_PING
626
627 #ifdef CONFIG_PCI
628 #define CONFIG_CMD_PCI
629 #endif
630
631 /*
632 * USB
633 */
634 #define CONFIG_HAS_FSL_DR_USB
635 #define CONFIG_HAS_FSL_MPH_USB
636
637 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
638 #define CONFIG_CMD_USB
639 #define CONFIG_USB_STORAGE
640 #define CONFIG_USB_EHCI
641 #define CONFIG_USB_EHCI_FSL
642 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
643 #endif
644
645 #define CONFIG_CMD_EXT2
646
647 #define CONFIG_MMC
648
649 #ifdef CONFIG_MMC
650 #define CONFIG_FSL_ESDHC
651 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
652 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
653 #define CONFIG_CMD_MMC
654 #define CONFIG_GENERIC_MMC
655 #define CONFIG_CMD_EXT2
656 #define CONFIG_CMD_FAT
657 #define CONFIG_DOS_PARTITION
658 #endif
659
660 /* Hash command with SHA acceleration supported in hardware */
661 #ifdef CONFIG_FSL_CAAM
662 #define CONFIG_CMD_HASH
663 #define CONFIG_SHA_HW_ACCEL
664 #endif
665
666 /*
667 * Miscellaneous configurable options
668 */
669 #define CONFIG_SYS_LONGHELP /* undef to save memory */
670 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
671 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
672 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
673 #ifdef CONFIG_CMD_KGDB
674 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
675 #else
676 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
677 #endif
678 /* Print Buffer Size */
679 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
680 sizeof(CONFIG_SYS_PROMPT)+16)
681 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
682 /* Boot Argument Buffer Size */
683 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
684
685 /*
686 * For booting Linux, the board info and command line data
687 * have to be in the first 64 MB of memory, since this is
688 * the maximum mapped by the Linux kernel during initialization.
689 */
690 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
691 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
692
693 #ifdef CONFIG_CMD_KGDB
694 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
695 #endif
696
697 /*
698 * Environment Configuration
699 */
700 #define CONFIG_ROOTPATH "/opt/nfsroot"
701 #define CONFIG_BOOTFILE "uImage"
702 #define CONFIG_UBOOTPATH u-boot.bin
703
704 /* default location for tftp and bootm */
705 #define CONFIG_LOADADDR 1000000
706
707 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
708
709 #define CONFIG_BAUDRATE 115200
710
711 #define __USB_PHY_TYPE utmi
712
713 #define CONFIG_EXTRA_ENV_SETTINGS \
714 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
715 "bank_intlv=cs0_cs1\0" \
716 "netdev=eth0\0" \
717 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
718 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
719 "tftpflash=tftpboot $loadaddr $uboot && " \
720 "protect off $ubootaddr +$filesize && " \
721 "erase $ubootaddr +$filesize && " \
722 "cp.b $loadaddr $ubootaddr $filesize && " \
723 "protect on $ubootaddr +$filesize && " \
724 "cmp.b $loadaddr $ubootaddr $filesize\0" \
725 "consoledev=ttyS0\0" \
726 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
727 "usb_dr_mode=host\0" \
728 "ramdiskaddr=2000000\0" \
729 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
730 "fdtaddr=c00000\0" \
731 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
732 "bdev=sda3\0"
733
734 #define CONFIG_HDBOOT \
735 "setenv bootargs root=/dev/$bdev rw " \
736 "console=$consoledev,$baudrate $othbootargs;" \
737 "tftp $loadaddr $bootfile;" \
738 "tftp $fdtaddr $fdtfile;" \
739 "bootm $loadaddr - $fdtaddr"
740
741 #define CONFIG_NFSBOOTCOMMAND \
742 "setenv bootargs root=/dev/nfs rw " \
743 "nfsroot=$serverip:$rootpath " \
744 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
745 "console=$consoledev,$baudrate $othbootargs;" \
746 "tftp $loadaddr $bootfile;" \
747 "tftp $fdtaddr $fdtfile;" \
748 "bootm $loadaddr - $fdtaddr"
749
750 #define CONFIG_RAMBOOTCOMMAND \
751 "setenv bootargs root=/dev/ram rw " \
752 "console=$consoledev,$baudrate $othbootargs;" \
753 "tftp $ramdiskaddr $ramdiskfile;" \
754 "tftp $loadaddr $bootfile;" \
755 "tftp $fdtaddr $fdtfile;" \
756 "bootm $loadaddr $ramdiskaddr $fdtaddr"
757
758 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
759
760 #include <asm/fsl_secure_boot.h>
761
762 #ifdef CONFIG_SECURE_BOOT
763 #define CONFIG_CMD_BLOB
764 #endif
765
766 #endif /* __CONFIG_H */