include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #endif
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  31 #define CONFIG_MP                       /* support multiple processors */
  32
  33 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  35 #endif
  36
  37 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  38 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  39 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  40 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  41 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  42 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  43 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  44
  45 #define CONFIG_SYS_SRIO
  46 #define CONFIG_SRIO1                    /* SRIO port 1 */
  47 #define CONFIG_SRIO2                    /* SRIO port 2 */
  48 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  49 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  50
  51 #define CONFIG_ENV_OVERWRITE
  52
  53 #ifndef CONFIG_MTD_NOR_FLASH
  54 #else
  55 #define CONFIG_FLASH_CFI_DRIVER
  56 #define CONFIG_SYS_FLASH_CFI
  57 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  58 #endif
  59
  60 #if defined(CONFIG_SPIFLASH)
  61         #define CONFIG_SYS_EXTRA_ENV_RELOC
  62         #define CONFIG_ENV_SPI_BUS              0
  63         #define CONFIG_ENV_SPI_CS               0
  64         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  65         #define CONFIG_ENV_SPI_MODE             0
  66         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  67         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  68         #define CONFIG_ENV_SECT_SIZE            0x10000
  69 #elif defined(CONFIG_SDCARD)
  70         #define CONFIG_SYS_EXTRA_ENV_RELOC
  71         #define CONFIG_FSL_FIXED_MMC_LOCATION
  72         #define CONFIG_SYS_MMC_ENV_DEV          0
  73         #define CONFIG_ENV_SIZE                 0x2000
  74         #define CONFIG_ENV_OFFSET               (512 * 1658)
  75 #elif defined(CONFIG_NAND)
  76 #define CONFIG_SYS_EXTRA_ENV_RELOC
  77 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  78 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  79 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  80 #define CONFIG_ENV_ADDR         0xffe20000
  81 #define CONFIG_ENV_SIZE         0x2000
  82 #elif defined(CONFIG_ENV_IS_NOWHERE)
  83 #define CONFIG_ENV_SIZE         0x2000
  84 #else
  85         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
  86                         - CONFIG_ENV_SECT_SIZE)
  87         #define CONFIG_ENV_SIZE         0x2000
  88         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  89 #endif
  90
  91 #ifndef __ASSEMBLY__
  92 unsigned long get_board_sys_clk(unsigned long dummy);
  93 #endif
  94 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  95
  96 /*
  97  * These can be toggled for performance analysis, otherwise use default.
  98  */
  99 #define CONFIG_SYS_CACHE_STASHING
 100 #define CONFIG_BACKSIDE_L2_CACHE
 101 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 102 #define CONFIG_BTB                      /* toggle branch predition */
 103
 104 #define CONFIG_ENABLE_36BIT_PHYS
 105
 106 #ifdef CONFIG_PHYS_64BIT
 107 #define CONFIG_ADDR_MAP
 108 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 109 #endif
 110
 111 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 112 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 113 #define CONFIG_SYS_MEMTEST_END          0x00400000
 114
 115 /*
 116  *  Config the L3 Cache as L3 SRAM
 117  */
 118 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 119 #ifdef CONFIG_PHYS_64BIT
 120 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 121                 CONFIG_RAMBOOT_TEXT_BASE)
 122 #else
 123 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 124 #endif
 125 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 126 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 127
 128 #ifdef CONFIG_PHYS_64BIT
 129 #define CONFIG_SYS_DCSRBAR              0xf0000000
 130 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 131 #endif
 132
 133 /* EEPROM */
 134 #define CONFIG_ID_EEPROM
 135 #define CONFIG_SYS_I2C_EEPROM_NXID
 136 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 137 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 139
 140 /*
 141  * DDR Setup
 142  */
 143 #define CONFIG_VERY_BIG_RAM
 144 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 145 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 146
 147 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 148 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 149
 150 #define CONFIG_DDR_SPD
 151
 152 #define CONFIG_SYS_SPD_BUS_NUM  0
 153 #define SPD_EEPROM_ADDRESS      0x52
 154 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 155
 156 /*
 157  * Local Bus Definitions
 158  */
 159
 160 /* Set the local bus clock 1/8 of platform clock */
 161 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 162
 163 /*
 164  * This board doesn't have a promjet connector.
 165  * However, it uses commone corenet board LAW and TLB.
 166  * It is necessary to use the same start address with proper offset.
 167  */
 168 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 169 #ifdef CONFIG_PHYS_64BIT
 170 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 171 #else
 172 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 173 #endif
 174
 175 #define CONFIG_SYS_FLASH_BR_PRELIM \
 176                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 177                 BR_PS_16 | BR_V)
 178 #define CONFIG_SYS_FLASH_OR_PRELIM \
 179                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 180                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 181
 182 #define CONFIG_FSL_CPLD
 183 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 184 #ifdef CONFIG_PHYS_64BIT
 185 #define CPLD_BASE_PHYS          0xfffdf0000ull
 186 #else
 187 #define CPLD_BASE_PHYS          CPLD_BASE
 188 #endif
 189
 190 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 191 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 192
 193 #define PIXIS_LBMAP_SWITCH      7
 194 #define PIXIS_LBMAP_MASK        0xf0
 195 #define PIXIS_LBMAP_SHIFT       4
 196 #define PIXIS_LBMAP_ALTBANK     0x40
 197
 198 #define CONFIG_SYS_FLASH_QUIET_TEST
 199 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 200
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 202 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 205
 206 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 207
 208 #if defined(CONFIG_RAMBOOT_PBL)
 209 #define CONFIG_SYS_RAMBOOT
 210 #endif
 211
 212 #define CONFIG_NAND_FSL_ELBC
 213 /* Nand Flash */
 214 #ifdef CONFIG_NAND_FSL_ELBC
 215 #define CONFIG_SYS_NAND_BASE            0xffa00000
 216 #ifdef CONFIG_PHYS_64BIT
 217 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 218 #else
 219 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 220 #endif
 221
 222 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 223 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 224 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 225
 226 /* NAND flash config */
 227 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 228                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 229                                | BR_PS_8               /* Port Size = 8 bit */ \
 230                                | BR_MS_FCM             /* MSEL = FCM */ \
 231                                | BR_V)                 /* valid */
 232 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 233                                | OR_FCM_PGS            /* Large Page*/ \
 234                                | OR_FCM_CSCT \
 235                                | OR_FCM_CST \
 236                                | OR_FCM_CHT \
 237                                | OR_FCM_SCY_1 \
 238                                | OR_FCM_TRLX \
 239                                | OR_FCM_EHTR)
 240
 241 #ifdef CONFIG_NAND
 242 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 243 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 244 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 245 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 246 #else
 247 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 248 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 249 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 250 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 251 #endif
 252 #else
 253 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 254 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 255 #endif /* CONFIG_NAND_FSL_ELBC */
 256
 257 #define CONFIG_SYS_FLASH_EMPTY_INFO
 258 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 259 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 260
 261 #define CONFIG_MISC_INIT_R
 262
 263 #define CONFIG_HWCONFIG
 264
 265 /* define to use L1 as initial stack */
 266 #define CONFIG_L1_INIT_RAM
 267 #define CONFIG_SYS_INIT_RAM_LOCK
 268 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 269 #ifdef CONFIG_PHYS_64BIT
 270 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 271 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 272 /* The assembler doesn't like typecast */
 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 274         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 275           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 276 #else
 277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 280 #endif
 281 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 282
 283 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 284                                         GENERATED_GBL_DATA_SIZE)
 285 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 286
 287 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 288 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 289
 290 /* Serial Port - controlled on board with jumper J8
 291  * open - index 2
 292  * shorted - index 1
 293  */
 294 #define CONFIG_SYS_NS16550_SERIAL
 295 #define CONFIG_SYS_NS16550_REG_SIZE     1
 296 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 297
 298 #define CONFIG_SYS_BAUDRATE_TABLE       \
 299         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 300
 301 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 302 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 303 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 304 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 305
 306 /* I2C */
 307 #define CONFIG_SYS_I2C
 308 #define CONFIG_SYS_I2C_FSL
 309 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 310 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 311 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 312 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 313 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 314 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 315
 316 /*
 317  * RapidIO
 318  */
 319 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 320 #ifdef CONFIG_PHYS_64BIT
 321 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 322 #else
 323 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 324 #endif
 325 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 326
 327 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 328 #ifdef CONFIG_PHYS_64BIT
 329 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 330 #else
 331 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 332 #endif
 333 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 334
 335 /*
 336  * for slave u-boot IMAGE instored in master memory space,
 337  * PHYS must be aligned based on the SIZE
 338  */
 339 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 343 /*
 344  * for slave UCODE and ENV instored in master memory space,
 345  * PHYS must be aligned based on the SIZE
 346  */
 347 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 348 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 349 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 350
 351 /* slave core release by master*/
 352 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 353 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 354
 355 /*
 356  * SRIO_PCIE_BOOT - SLAVE
 357  */
 358 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 359 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 360 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 361                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 362 #endif
 363
 364 /*
 365  * eSPI - Enhanced SPI
 366  */
 367 #define CONFIG_SF_DEFAULT_SPEED         10000000
 368 #define CONFIG_SF_DEFAULT_MODE          0
 369
 370 /*
 371  * General PCI
 372  * Memory space is mapped 1-1, but I/O space must start from 0.
 373  */
 374
 375 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 376 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 377 #ifdef CONFIG_PHYS_64BIT
 378 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 379 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 380 #else
 381 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 382 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 383 #endif
 384 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 385 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 386 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 387 #ifdef CONFIG_PHYS_64BIT
 388 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 389 #else
 390 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 391 #endif
 392 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 393
 394 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 395 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 396 #ifdef CONFIG_PHYS_64BIT
 397 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 398 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 399 #else
 400 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 401 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 402 #endif
 403 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 404 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 405 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 406 #ifdef CONFIG_PHYS_64BIT
 407 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 408 #else
 409 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 410 #endif
 411 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 412
 413 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 414 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 415 #ifdef CONFIG_PHYS_64BIT
 416 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 417 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 418 #else
 419 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 420 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 421 #endif
 422 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 423 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 424 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 425 #ifdef CONFIG_PHYS_64BIT
 426 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 427 #else
 428 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 429 #endif
 430 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 431
 432 /* Qman/Bman */
 433 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 434 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 435 #ifdef CONFIG_PHYS_64BIT
 436 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 437 #else
 438 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 439 #endif
 440 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 441 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 442 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 443 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 444 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 445 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 446                                         CONFIG_SYS_BMAN_CENA_SIZE)
 447 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 448 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 449 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 450 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 451 #ifdef CONFIG_PHYS_64BIT
 452 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 453 #else
 454 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 455 #endif
 456 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 457 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 458 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 459 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 460 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 461 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 462                                         CONFIG_SYS_QMAN_CENA_SIZE)
 463 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 464 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 465
 466 #define CONFIG_SYS_DPAA_FMAN
 467 #define CONFIG_SYS_DPAA_PME
 468 /* Default address of microcode for the Linux Fman driver */
 469 #if defined(CONFIG_SPIFLASH)
 470 /*
 471  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 472  * env, so we got 0x110000.
 473  */
 474 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 475 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 476 #elif defined(CONFIG_SDCARD)
 477 /*
 478  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 479  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 480  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 481  */
 482 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 483 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 484 #elif defined(CONFIG_NAND)
 485 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 486 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 487 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 488 /*
 489  * Slave has no ucode locally, it can fetch this from remote. When implementing
 490  * in two corenet boards, slave's ucode could be stored in master's memory
 491  * space, the address can be mapped from slave TLB->slave LAW->
 492  * slave SRIO or PCIE outbound window->master inbound window->
 493  * master LAW->the ucode address in master's memory space.
 494  */
 495 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 496 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 497 #else
 498 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 499 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 500 #endif
 501 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 502 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 503
 504 #ifdef CONFIG_SYS_DPAA_FMAN
 505 #define CONFIG_FMAN_ENET
 506 #define CONFIG_PHYLIB_10G
 507 #define CONFIG_PHY_VITESSE
 508 #define CONFIG_PHY_TERANETICS
 509 #endif
 510
 511 #ifdef CONFIG_PCI
 512 #define CONFIG_PCI_INDIRECT_BRIDGE
 513
 514 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 515 #endif  /* CONFIG_PCI */
 516
 517 /* SATA */
 518 #define CONFIG_FSL_SATA_V2
 519
 520 #ifdef CONFIG_FSL_SATA_V2
 521 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 522 #define CONFIG_SATA1
 523 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 524 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 525 #define CONFIG_SATA2
 526 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 527 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 528
 529 #define CONFIG_LBA48
 530 #endif
 531
 532 #ifdef CONFIG_FMAN_ENET
 533 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 534 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 535 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 536 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 537 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 538
 539 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 540 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 541 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 542 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 543
 544 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 545
 546 #define CONFIG_SYS_TBIPA_VALUE  8
 547 #define CONFIG_MII              /* MII PHY management */
 548 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 549 #endif
 550
 551 /*
 552  * Environment
 553  */
 554 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 555 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 556
 557 /*
 558  * Command line configuration.
 559  */
 560
 561 /*
 562 * USB
 563 */
 564 #define CONFIG_HAS_FSL_DR_USB
 565 #define CONFIG_HAS_FSL_MPH_USB
 566
 567 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 568 #define CONFIG_USB_EHCI_FSL
 569 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 570 #endif
 571
 572 #ifdef CONFIG_MMC
 573 #define CONFIG_FSL_ESDHC
 574 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 575 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 576 #endif
 577
 578 /*
 579  * Miscellaneous configurable options
 580  */
 581 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 582
 583 /*
 584  * For booting Linux, the board info and command line data
 585  * have to be in the first 64 MB of memory, since this is
 586  * the maximum mapped by the Linux kernel during initialization.
 587  */
 588 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 589 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 590
 591 #ifdef CONFIG_CMD_KGDB
 592 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 593 #endif
 594
 595 /*
 596  * Environment Configuration
 597  */
 598 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 599 #define CONFIG_BOOTFILE         "uImage"
 600 #define CONFIG_UBOOTPATH        u-boot.bin
 601
 602 /* default location for tftp and bootm */
 603 #define CONFIG_LOADADDR         1000000
 604
 605 #define __USB_PHY_TYPE  utmi
 606
 607 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 608         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 609         "bank_intlv=cs0_cs1\0"                                  \
 610         "netdev=eth0\0"                                         \
 611         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 612         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 613         "tftpflash=tftpboot $loadaddr $uboot && "               \
 614         "protect off $ubootaddr +$filesize && "                 \
 615         "erase $ubootaddr +$filesize && "                       \
 616         "cp.b $loadaddr $ubootaddr $filesize && "               \
 617         "protect on $ubootaddr +$filesize && "                  \
 618         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 619         "consoledev=ttyS0\0"                                    \
 620         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 621         "usb_dr_mode=host\0"                                    \
 622         "ramdiskaddr=2000000\0"                                 \
 623         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 624         "fdtaddr=1e00000\0"                                     \
 625         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 626         "bdev=sda3\0"
 627
 628 #define CONFIG_HDBOOT                                   \
 629         "setenv bootargs root=/dev/$bdev rw "           \
 630         "console=$consoledev,$baudrate $othbootargs;"   \
 631         "tftp $loadaddr $bootfile;"                     \
 632         "tftp $fdtaddr $fdtfile;"                       \
 633         "bootm $loadaddr - $fdtaddr"
 634
 635 #define CONFIG_NFSBOOTCOMMAND                   \
 636         "setenv bootargs root=/dev/nfs rw "     \
 637         "nfsroot=$serverip:$rootpath "          \
 638         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 639         "console=$consoledev,$baudrate $othbootargs;"   \
 640         "tftp $loadaddr $bootfile;"             \
 641         "tftp $fdtaddr $fdtfile;"               \
 642         "bootm $loadaddr - $fdtaddr"
 643
 644 #define CONFIG_RAMBOOTCOMMAND                           \
 645         "setenv bootargs root=/dev/ram rw "             \
 646         "console=$consoledev,$baudrate $othbootargs;"   \
 647         "tftp $ramdiskaddr $ramdiskfile;"               \
 648         "tftp $loadaddr $bootfile;"                     \
 649         "tftp $fdtaddr $fdtfile;"                       \
 650         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 651
 652 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 653
 654 #include <asm/fsl_secure_boot.h>
 655
 656 #endif  /* __CONFIG_H */