include/configs/P3G4.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #ifndef __ASSEMBLY__
  32 #include <galileo/core.h>
  33 #endif
  34
  35 #include "../board/evb64260/local.h"
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #define CONFIG_P3G4             1       /* this is a P3G4  board        */
  43 #define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
  44
  45 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  46
  47 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115200    */
  48
  49 #undef  CONFIG_ECC                      /* enable ECC support */
  50 /* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
  51
  52 /* which initialization functions to call for this board */
  53 #define CONFIG_MISC_INIT_R      1
  54 #define CONFIG_BOARD_EARLY_INIT_F 1
  55
  56 #define CONFIG_SYS_BOARD_NAME           "P3G4"
  57
  58 #undef CONFIG_SYS_HUSH_PARSER
  59 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
  60
  61 /*
  62  * The following defines let you select what serial you want to use
  63  * for your console driver.
  64  *
  65  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  66  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  67  */
  68 #define CONFIG_MPSC
  69 #define CONFIG_MPSC_PORT        0
  70
  71 #define CONFIG_NET_MULTI        /* attempt all available adapters */
  72
  73 /* define this if you want to enable GT MAC filtering */
  74 #define CONFIG_GT_USE_MAC_HASH_TABLE
  75
  76 #undef CONFIG_ETHER_PORT_MII    /* use RMII */
  77
  78 #if 0
  79 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  80 #else
  81 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  82 #endif
  83 #define CONFIG_ZERO_BOOTDELAY_CHECK
  84
  85 #define CONFIG_PREBOOT  "echo;" \
  86         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  87         "echo"
  88
  89 #undef  CONFIG_BOOTARGS
  90
  91 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  92         "netdev=eth0\0"                                                 \
  93         "hostname=p3g4\0"                                               \
  94         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  95                 "nfsroot=${serverip}:${rootpath}\0"                     \
  96         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  97         "addip=setenv bootargs ${bootargs} "                            \
  98                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  99                 ":${hostname}:${netdev}:off panic=1\0"                  \
 100         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 101         "flash_nfs=run nfsargs addip addtty;"                           \
 102                 "bootm ${kernel_addr}\0"                                \
 103         "flash_self=run ramargs addip addtty;"                          \
 104                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 105         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 106                 "bootm\0"                                               \
 107         "rootpath=/opt/eldk/ppc_74xx\0"                                 \
 108         "bootfile=/tftpboot/p3g4/uImage\0"                              \
 109         "kernel_addr=ff000000\0"                                        \
 110         "ramdisk_addr=ff010000\0"                                       \
 111         "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"                  \
 112         "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"   \
 113                 "cp.b 100000 fff00000 ${filesize};"                     \
 114                 "setenv filesize;saveenv\0"                             \
 115         "upd=run load update\0"                                         \
 116         ""
 117 #define CONFIG_BOOTCOMMAND      "run flash_self"
 118
 119 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 120 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate changes       */
 121
 122 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 123 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 124
 125 /*
 126  * BOOTP options
 127  */
 128 #define CONFIG_BOOTP_SUBNETMASK
 129 #define CONFIG_BOOTP_GATEWAY
 130 #define CONFIG_BOOTP_HOSTNAME
 131 #define CONFIG_BOOTP_BOOTPATH
 132 #define CONFIG_BOOTP_BOOTFILESIZE
 133
 134
 135 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 136
 137
 138 /*
 139  * Command line configuration.
 140  */
 141 #include <config_cmd_default.h>
 142
 143 #define CONFIG_CMD_ASKENV
 144 #define CONFIG_CMD_DHCP
 145 #define CONFIG_CMD_PCI
 146 #define CONFIG_CMD_ELF
 147 #define CONFIG_CMD_MII
 148 #define CONFIG_CMD_PING
 149 #define CONFIG_CMD_UNIVERSE
 150 #define CONFIG_CMD_BSP
 151
 152
 153 /*
 154  * Miscellaneous configurable options
 155  */
 156 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 157 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 158 #if defined(CONFIG_CMD_KGDB)
 159 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 160 #else
 161 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 162 #endif
 163 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 164 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 165 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 166
 167 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 168 #define CONFIG_SYS_MEMTEST_END          0x00C00000      /* 4 ... 12 MB in DRAM  */
 169
 170 #define CONFIG_SYS_LOAD_ADDR            0x00300000      /* default load address */
 171
 172 #define CONFIG_SYS_HZ                   1000            /* decr freq: 1ms ticks */
 173 #define CONFIG_SYS_BUS_CLK              133000000       /* 133 MHz              */
 174
 175 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 176
 177
 178 /*
 179  * Low Level Configuration Settings
 180  * (address mappings, register initial values, etc.)
 181  * You should know what you are doing if you make changes here.
 182  */
 183
 184 /*-----------------------------------------------------------------------
 185  * Definitions for initial stack pointer and data area
 186  */
 187 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 188 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 189 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 190 #define CONFIG_SYS_INIT_RAM_LOCK
 191
 192
 193 /*-----------------------------------------------------------------------
 194  * Start addresses for the final memory configuration
 195  * (Set up by the startup code)
 196  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 197  */
 198 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 199 #define CONFIG_SYS_FLASH_BASE           0xff000000
 200 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 201 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 203 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc */
 204
 205 /* areas to map different things with the GT in physical space */
 206 #define CONFIG_SYS_DRAM_BANKS           1
 207 #define CONFIG_SYS_DFL_GT_REGS          0x14000000      /* boot time GT_REGS */
 208
 209 /* What to put in the bats. */
 210 #define CONFIG_SYS_MISC_REGION_BASE     0xf0000000
 211
 212 /* Peripheral Device section */
 213 #define CONFIG_SYS_GT_REGS              0xf8000000
 214 #define CONFIG_SYS_DEV_BASE             0xff000000
 215
 216 #define CONFIG_SYS_DEV0_SPACE           CONFIG_SYS_DEV_BASE
 217 #define CONFIG_SYS_DEV1_SPACE           (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
 218 #define CONFIG_SYS_DEV2_SPACE           (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
 219 #define CONFIG_SYS_DEV3_SPACE           (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
 220
 221 #define CONFIG_SYS_DEV0_SIZE             _8M /* Flash bank */
 222 #define CONFIG_SYS_DEV1_SIZE             0   /* unused */
 223 #define CONFIG_SYS_DEV2_SIZE             0   /* unused */
 224 #define CONFIG_SYS_DEV3_SIZE             0   /* unused */
 225
 226 #define CONFIG_SYS_16BIT_BOOT_PAR       0xc01b5e7c
 227 #define CONFIG_SYS_DEV0_PAR             CONFIG_SYS_16BIT_BOOT_PAR
 228
 229 #if 0 /* Wrong?? NTL */
 230 #define CONFIG_SYS_MPP_CONTROL_0        0x53541717      /* InitAct EOT[4] DBurst TCEn[1] */
 231                                                 /* DMAAck[1:0] GNT0[1:0] */
 232 #else
 233 #define CONFIG_SYS_MPP_CONTROL_0        0x53547777      /* InitAct EOT[4] DBurst TCEn[1] */
 234                                                 /* REQ0[1:0] GNT0[1:0] */
 235 #endif
 236 #define CONFIG_SYS_MPP_CONTROL_1        0x44009911      /* TCEn[4] TCTcnt[4] GPP[13:12] */
 237                                                 /* DMAReq[4] DMAAck[4] WDNMI WDE */
 238 #if 0 /* Wrong?? NTL */
 239 #define CONFIG_SYS_MPP_CONTROL_2        0x40091818      /* TCTcnt[0] GPP[22:21] BClkIn */
 240                                                 /* DMAAck[1:0] GNT1[1:0] */
 241 #else
 242 #define CONFIG_SYS_MPP_CONTROL_2        0x40098888      /* TCTcnt[0] */
 243                                                 /* GPP[22] (RS232IntB or PCI1Int) */
 244                                                 /* GPP[21] (RS323IntA) */
 245                                                 /* BClkIn */
 246                                                 /* REQ1[1:0] GNT1[1:0] */
 247 #endif
 248
 249 #if 0 /* Wrong?? NTL */
 250 # define CONFIG_SYS_MPP_CONTROL_3       0x00090066      /* GPP[31:29] BClkOut0 */
 251                                                 /* GPP[27:26] Int[1:0] */
 252 #else
 253 # define CONFIG_SYS_MPP_CONTROL_3       0x22090066      /* MREQ MGNT */
 254                                                 /* GPP[29]    (PCI1Int) */
 255                                                 /* BClkOut0 */
 256                                                 /* GPP[27]    (PCI0Int) */
 257                                                 /* GPP[26]    (RtcInt or PCI1Int) */
 258                                                 /* CPUInt[25:24] */
 259 #endif
 260
 261 #define CONFIG_SYS_SERIAL_PORT_MUX      0x00001102      /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
 262
 263 #if 0 /* Wrong?? - NTL */
 264 # define CONFIG_SYS_GPP_LEVEL_CONTROL   0x000002c6
 265 #else
 266 # define CONFIG_SYS_GPP_LEVEL_CONTROL   0x2c600000      /* 0010 1100 0110 0000 */
 267                                                 /* gpp[29] */
 268                                                 /* gpp[27:26] */
 269                                                 /* gpp[22:21] */
 270
 271 # define CONFIG_SYS_SDRAM_CONFIG        0xd8e18200      /* 0x448 */
 272                                 /* idmas use buffer 1,1
 273                                    comm use buffer 0
 274                                    pci use buffer 1,1
 275                                    cpu use buffer 0
 276                                    normal load (see also ifdef HVL)
 277                                    standard SDRAM (see also ifdef REG)
 278                                    non staggered refresh */
 279                                 /* 31:26  25 23  20 19 18 16 */
 280                                 /* 110110 00 111 0  0  00 1 */
 281                                 /* refresh_count=0x200
 282                                    phisical interleaving disable
 283                                    virtual interleaving enable */
 284                                 /* 15 14 13:0 */
 285                                 /* 1  0  0x200 */
 286 #endif
 287
 288 #if 0
 289 #define CONFIG_SYS_DUART_IO             CONFIG_SYS_DEV2_SPACE
 290 #define CONFIG_SYS_DUART_CHAN           1               /* channel to use for console */
 291 #endif
 292 #undef CONFIG_SYS_INIT_CHAN1
 293 #undef CONFIG_SYS_INIT_CHAN2
 294 #if 0
 295 #define SRAM_BASE               CONFIG_SYS_DEV0_SPACE
 296 #define SRAM_SIZE               0x00100000              /* 1 MB of sram */
 297 #endif
 298
 299
 300 /*-----------------------------------------------------------------------
 301  * PCI stuff
 302  *-----------------------------------------------------------------------
 303  */
 304
 305 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 306 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 307 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 308
 309 #define CONFIG_PCI                      /* include pci support          */
 310 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 311 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 312
 313 /* PCI MEMORY MAP section */
 314 #define CONFIG_SYS_PCI0_MEM_BASE        0x80000000
 315 #define CONFIG_SYS_PCI0_MEM_SIZE        _128M
 316 #define CONFIG_SYS_PCI0_0_MEM_SPACE     (CONFIG_SYS_PCI0_MEM_BASE)
 317
 318 #define CONFIG_SYS_PCI1_MEM_BASE        0x88000000
 319 #define CONFIG_SYS_PCI1_MEM_SIZE        _128M
 320 #define CONFIG_SYS_PCI1_0_MEM_SPACE     (CONFIG_SYS_PCI1_MEM_BASE)
 321
 322 /* PCI I/O MAP section */
 323 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
 324 #define CONFIG_SYS_PCI0_IO_SIZE _16M
 325 #define CONFIG_SYS_PCI0_IO_SPACE        (CONFIG_SYS_PCI0_IO_BASE)
 326 #define CONFIG_SYS_PCI0_IO_SPACE_PCI    0x00000000
 327
 328 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
 329 #define CONFIG_SYS_PCI1_IO_SIZE _16M
 330 #define CONFIG_SYS_PCI1_IO_SPACE        (CONFIG_SYS_PCI1_IO_BASE)
 331 #define CONFIG_SYS_PCI1_IO_SPACE_PCI    0x00000000
 332
 333 /*----------------------------------------------------------------------
 334  * Initial BAT mappings
 335  */
 336
 337 /* NOTES:
 338  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 339  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 340  */
 341
 342 /* SDRAM */
 343 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 344 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 345 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 346 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 347
 348 /* init ram */
 349 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 350 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 351 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 352 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 353
 354 /* PCI0, PCI1 in one BAT */
 355 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
 356 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
 357 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 358 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 359
 360 /* GT regs, bootrom, all the devices, PCI I/O */
 361 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 362 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 363 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 364 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 365
 366 /* I2C speed and slave address (for compatability) defaults */
 367 #define CONFIG_SYS_I2C_SPEED    400000
 368 #define CONFIG_SYS_I2C_SLAVE    0x7F
 369
 370 /* I2C addresses for the two DIMM SPD chips */
 371 #ifndef CONFIG_EVB64260_750CX
 372 #define DIMM0_I2C_ADDR  0x56
 373 #define DIMM1_I2C_ADDR  0x54
 374 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
 375 #define DIMM0_I2C_ADDR  0x54
 376 #define DIMM1_I2C_ADDR  0x54
 377 #endif
 378
 379 /*
 380  * For booting Linux, the board info and command line data
 381  * have to be in the first 8 MB of memory, since this is
 382  * the maximum mapped by the Linux kernel during initialization.
 383  */
 384 #define CONFIG_SYS_BOOTMAPSZ            (8<<20) /* Initial Memory map for Linux */
 385
 386 /*-----------------------------------------------------------------------
 387  * FLASH organization
 388  */
 389 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks   */
 390 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip */
 391
 392 #define CONFIG_SYS_EXTRA_FLASH_DEVICE   BOOT_DEVICE
 393 #define CONFIG_SYS_EXTRA_FLASH_WIDTH    2       /* 16 bit */
 394 #define CONFIG_SYS_BOOT_FLASH_WIDTH     2       /* 16 bit */
 395
 396 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 397 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 398 #define CONFIG_SYS_FLASH_CFI            1
 399
 400 #define CONFIG_ENV_IS_IN_FLASH  1
 401 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector */
 402 #define CONFIG_ENV_SECT_SIZE    0x20000
 403 #define CONFIG_ENV_ADDR         0xFFFE0000
 404
 405 /*-----------------------------------------------------------------------
 406  * Cache Configuration
 407  */
 408 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For all MPC74xx CPUs          */
 409 #if defined(CONFIG_CMD_KGDB)
 410 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 411 #endif
 412
 413 /*-----------------------------------------------------------------------
 414  * L2CR setup -- make sure this is right for your board!
 415  * look in include/74xx_7xx.h for the defines used here
 416  */
 417
 418 #define CONFIG_SYS_L2
 419
 420 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 421                          L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 422
 423 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 424
 425 #define CONFIG_SYS_BOARD_ASM_INIT      1
 426
 427
 428 #endif  /* __CONFIG_H */