include/configs/PCI405.h

   1 /*
   2  * (C) Copyright 2007
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2004
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * board/config.h - configuration options, board specific
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  * (easy to change)
  21  */
  22 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  23 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  24 #define CONFIG_PCI405           1       /* ...on a PCI405 board         */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFFFD0000
  27
  28 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  29 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r() on init   */
  30
  31 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  32
  33 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  34
  35 #define CONFIG_BAUDRATE         115200
  36 #define CONFIG_BOOTDELAY        0       /* autoboot after 0 seconds     */
  37
  38 #undef  CONFIG_BOOTARGS
  39 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  40         "mem_linux=14336k\0"                                            \
  41         "optargs=panic=0\0"                                             \
  42         "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"     \
  43         "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
  44         ""
  45 #define CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"
  46
  47 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  48
  49 /*
  50  * Command line configuration.
  51  */
  52 #include <config_cmd_default.h>
  53
  54 #undef CONFIG_CMD_IMLS
  55 #undef CONFIG_CMD_ITEST
  56 #undef CONFIG_CMD_LOADB
  57 #undef CONFIG_CMD_LOADS
  58 #undef CONFIG_CMD_NET
  59 #undef CONFIG_CMD_NFS
  60
  61 #define CONFIG_CMD_PCI
  62 #define CONFIG_CMD_ELF
  63 #define CONFIG_CMD_I2C
  64 #define CONFIG_CMD_BSP
  65 #define CONFIG_CMD_EEPROM
  66
  67 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  68
  69 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  70
  71 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
  72
  73 /*
  74  * Miscellaneous configurable options
  75  */
  76
  77 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  78
  79 #if defined(CONFIG_CMD_KGDB)
  80 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  81 #else
  82 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  83 #endif
  84 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  85 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  86 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  87
  88 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  89
  90 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  91
  92 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  93 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  94
  95 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  96 #define CONFIG_SYS_NS16550
  97 #define CONFIG_SYS_NS16550_SERIAL
  98 #define CONFIG_SYS_NS16550_REG_SIZE     1
  99 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 100
 101 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 102 #define CONFIG_SYS_BASE_BAUD        691200
 103
 104 /* The following table includes the supported baudrates */
 105 #define CONFIG_SYS_BAUDRATE_TABLE       \
 106         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 107          57600, 115200, 230400, 460800, 921600 }
 108
 109 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 110 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 111
 112 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* check for keypress on bootdelay==0 */
 113
 114 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 115
 116 /*-----------------------------------------------------------------------
 117  * PCI stuff
 118  *-----------------------------------------------------------------------
 119  */
 120 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 121 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 122 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 123
 124 #define CONFIG_PCI                      /* include pci support          */
 125 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 126 #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function    */
 127 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
 128                                         /* resource configuration       */
 129
 130 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 131
 132 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 133 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407   /* PCI Device ID: PCI-405       */
 134 #define CONFIG_SYS_PCI_CLASSCODE        0x0280  /* PCI Class Code: Network/Other*/
 135 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 136 #define CONFIG_SYS_PCI_PTM1MS   0xff000001      /* 16MB, enable hard-wired to 1 */
 137 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 138
 139 #define CONFIG_SYS_PCI_PTM2LA   0xef600000      /* point to internal regs       */
 140 #define CONFIG_SYS_PCI_PTM2MS   0xffe00001      /* 2MB, enable                  */
 141 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000       /* Host: use this pci address   */
 142
 143 /*-----------------------------------------------------------------------
 144  * Start addresses for the final memory configuration
 145  * (Set up by the startup code)
 146  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 147  */
 148 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 149 #define CONFIG_SYS_FLASH_BASE           0xFFFD0000
 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 151 #define CONFIG_SYS_MONITOR_LEN          (192 * 1024)    /* Reserve 196 kB for Monitor   */
 152 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 153
 154 /*
 155  * For booting Linux, the board info and command line data
 156  * have to be in the first 8 MB of memory, since this is
 157  * the maximum mapped by the Linux kernel during initialization.
 158  */
 159 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 160 /*-----------------------------------------------------------------------
 161  * FLASH organization
 162  */
 163 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 164 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 165
 166 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 167 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 168
 169 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 170 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 171 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 172 /*
 173  * The following defines are added for buggy IOP480 byte interface.
 174  * All other boards should use the standard values (CPCI405 etc.)
 175  */
 176 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 177 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 178 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 179
 180 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 181
 182 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 183 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 184 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars*/
 185                                    /* total size of a CAT24WC08 is 1024 bytes */
 186
 187 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0200000              /* NVRAM base address   */
 188 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 189
 190 /*-----------------------------------------------------------------------
 191  * I2C EEPROM (CAT24WC16) for environment
 192  */
 193 #define CONFIG_SYS_I2C
 194 #define CONFIG_SYS_I2C_PPC4XX
 195 #define CONFIG_SYS_I2C_PPC4XX_CH0
 196 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 197 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 198
 199 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 200 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 201 /* mask of address bits that overflow into the "EEPROM chip address"    */
 202 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 203 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 204                                         /* 16 byte page write mode using*/
 205                                         /* last 4 bits of the address   */
 206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 207
 208 /*
 209  * Init Memory Controller:
 210  *
 211  * BR0/1 and OR0/1 (FLASH)
 212  */
 213
 214 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 215
 216 /*-----------------------------------------------------------------------
 217  * External Bus Controller (EBC) Setup
 218  */
 219
 220 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 221 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 222 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 223
 224 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 225 #define CONFIG_SYS_EBC_PB1AP            0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
 226 #define CONFIG_SYS_EBC_PB1CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 227
 228 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 229 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 230 /*#define CONFIG_SYS_EBC_PB2AP            0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 231 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 232
 233 /* Memory Bank 3 (FPGA internal) initialization                                 */
 234 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 235 #define CONFIG_SYS_EBC_PB3CR            0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 236 #define CONFIG_SYS_FPGA_BASE_ADDR       0xF0400000
 237
 238 /*-----------------------------------------------------------------------
 239  * FPGA stuff
 240  */
 241 /* FPGA internal regs */
 242 #define CONFIG_SYS_FPGA_MODE            0x00
 243 #define CONFIG_SYS_FPGA_STATUS          0x02
 244 #define CONFIG_SYS_FPGA_TS              0x04
 245 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 246 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 247 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 248 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 249 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 250 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 251 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 252 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 253 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 254
 255 /* FPGA Mode Reg */
 256 #define CONFIG_SYS_FPGA_MODE_CF_RESET   0x0001
 257 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 258 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 259 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR   0x2000
 260
 261 /* FPGA Status Reg */
 262 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 263 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 264 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 265 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 266 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 267
 268 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 269 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024     /* 32kByte is enough for XC2S15  */
 270
 271 /* FPGA program pin configuration */
 272 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 273 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 274 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 275 #define CONFIG_SYS_FPGA_INIT            0x00400000  /* FPGA init pin (ppc input)     */
 276 #define CONFIG_SYS_FPGA_DONE            0x00800000  /* FPGA done pin (ppc input)     */
 277 /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
 278 #define CONFIG_SYS_FPGA_INIT_V12        0x00008000  /* FPGA init pin (ppc input)     */
 279 #define CONFIG_SYS_FPGA_DONE_V12        0x00010000  /* FPGA done pin (ppc input)     */
 280
 281 /*-----------------------------------------------------------------------
 282  * Definitions for initial stack pointer and data area (in data cache)
 283  */
 284 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 285 #define CONFIG_SYS_TEMP_STACK_OCM         1
 286 /* On Chip Memory location */
 287 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 288 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 289 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 290 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 291
 292 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 293 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 294
 295 #endif  /* __CONFIG_H */