include/configs/PCI405.h

   1 /*
   2  * (C) Copyright 2007
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2004
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  39 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  40 #define CONFIG_PCI405           1       /* ...on a PCI405 board         */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r() on init   */
  44
  45 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  46
  47 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  48
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_BOOTDELAY        0       /* autoboot after 0 seconds     */
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  54         "mem_linux=14336k\0"                                            \
  55         "optargs=panic=0\0"                                             \
  56         "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"     \
  57         "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
  58         ""
  59 #define CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"
  60
  61 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67
  68 #undef CONFIG_CMD_IMLS
  69 #undef CONFIG_CMD_ITEST
  70 #undef CONFIG_CMD_LOADB
  71 #undef CONFIG_CMD_LOADS
  72 #undef CONFIG_CMD_NET
  73 #undef CONFIG_CMD_NFS
  74
  75 #define CONFIG_CMD_PCI
  76 #define CONFIG_CMD_ELF
  77 #define CONFIG_CMD_I2C
  78 #define CONFIG_CMD_BSP
  79 #define CONFIG_CMD_EEPROM
  80
  81 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  82
  83 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  84
  85 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
  86
  87 /*
  88  * Miscellaneous configurable options
  89  */
  90 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  91
  92 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  93 #ifdef  CONFIG_SYS_HUSH_PARSER
  94 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
  95 #endif
  96
  97 #if defined(CONFIG_CMD_KGDB)
  98 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  99 #else
 100 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 101 #endif
 102 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 103 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 104 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 105
 106 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 107
 108 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 109
 110 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 111 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 112
 113 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 114 #define CONFIG_SYS_BASE_BAUD        691200
 115
 116 /* The following table includes the supported baudrates */
 117 #define CONFIG_SYS_BAUDRATE_TABLE       \
 118         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 119          57600, 115200, 230400, 460800, 921600 }
 120
 121 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 122 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 123
 124 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 125
 126 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* check for keypress on bootdelay==0 */
 127
 128 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 129
 130 /*-----------------------------------------------------------------------
 131  * PCI stuff
 132  *-----------------------------------------------------------------------
 133  */
 134 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 135 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 136 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 137
 138 #define CONFIG_PCI                      /* include pci support          */
 139 #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function    */
 140 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
 141                                         /* resource configuration       */
 142
 143 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 144
 145 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 146 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407   /* PCI Device ID: PCI-405       */
 147 #define CONFIG_SYS_PCI_CLASSCODE        0x0280  /* PCI Class Code: Network/Other*/
 148 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 149 #define CONFIG_SYS_PCI_PTM1MS   0xff000001      /* 16MB, enable hard-wired to 1 */
 150 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 151
 152 #define CONFIG_SYS_PCI_PTM2LA   0xef600000      /* point to internal regs       */
 153 #define CONFIG_SYS_PCI_PTM2MS   0xffe00001      /* 2MB, enable                  */
 154 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000       /* Host: use this pci address   */
 155
 156 /*-----------------------------------------------------------------------
 157  * Start addresses for the final memory configuration
 158  * (Set up by the startup code)
 159  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 160  */
 161 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 162 #define CONFIG_SYS_FLASH_BASE           0xFFFD0000
 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 164 #define CONFIG_SYS_MONITOR_LEN          (192 * 1024)    /* Reserve 196 kB for Monitor   */
 165 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 166
 167 /*
 168  * For booting Linux, the board info and command line data
 169  * have to be in the first 8 MB of memory, since this is
 170  * the maximum mapped by the Linux kernel during initialization.
 171  */
 172 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 173 /*-----------------------------------------------------------------------
 174  * FLASH organization
 175  */
 176 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 177 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 178
 179 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 180 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 181
 182 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 183 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 184 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 185 /*
 186  * The following defines are added for buggy IOP480 byte interface.
 187  * All other boards should use the standard values (CPCI405 etc.)
 188  */
 189 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 190 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 191 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 192
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 194
 195 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 196 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 197 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars*/
 198                                    /* total size of a CAT24WC08 is 1024 bytes */
 199
 200 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0200000              /* NVRAM base address   */
 201 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 202
 203 /*-----------------------------------------------------------------------
 204  * I2C EEPROM (CAT24WC16) for environment
 205  */
 206 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 207 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 208 #define CONFIG_SYS_I2C_SLAVE            0x7F
 209
 210 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 212 /* mask of address bits that overflow into the "EEPROM chip address"    */
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 215                                         /* 16 byte page write mode using*/
 216                                         /* last 4 bits of the address   */
 217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 218
 219 /*
 220  * Init Memory Controller:
 221  *
 222  * BR0/1 and OR0/1 (FLASH)
 223  */
 224
 225 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 226
 227 /*-----------------------------------------------------------------------
 228  * External Bus Controller (EBC) Setup
 229  */
 230
 231 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 232 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 233 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 234
 235 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 236 #define CONFIG_SYS_EBC_PB1AP            0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
 237 #define CONFIG_SYS_EBC_PB1CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 238
 239 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 240 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 241 /*#define CONFIG_SYS_EBC_PB2AP            0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 242 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 243
 244 /* Memory Bank 3 (FPGA internal) initialization                                 */
 245 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 246 #define CONFIG_SYS_EBC_PB3CR            0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 247 #define CONFIG_SYS_FPGA_BASE_ADDR       0xF0400000
 248
 249 /*-----------------------------------------------------------------------
 250  * FPGA stuff
 251  */
 252 /* FPGA internal regs */
 253 #define CONFIG_SYS_FPGA_MODE            0x00
 254 #define CONFIG_SYS_FPGA_STATUS          0x02
 255 #define CONFIG_SYS_FPGA_TS              0x04
 256 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 257 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 258 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 259 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 260 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 261 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 262 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 263 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 264 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 265
 266 /* FPGA Mode Reg */
 267 #define CONFIG_SYS_FPGA_MODE_CF_RESET   0x0001
 268 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 269 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 270 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR   0x2000
 271
 272 /* FPGA Status Reg */
 273 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 274 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 275 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 276 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 277 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 278
 279 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 280 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024     /* 32kByte is enough for XC2S15  */
 281
 282 /* FPGA program pin configuration */
 283 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 284 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 285 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 286 #define CONFIG_SYS_FPGA_INIT            0x00400000  /* FPGA init pin (ppc input)     */
 287 #define CONFIG_SYS_FPGA_DONE            0x00800000  /* FPGA done pin (ppc input)     */
 288 /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
 289 #define CONFIG_SYS_FPGA_INIT_V12        0x00008000  /* FPGA init pin (ppc input)     */
 290 #define CONFIG_SYS_FPGA_DONE_V12        0x00010000  /* FPGA done pin (ppc input)     */
 291
 292 /*-----------------------------------------------------------------------
 293  * Definitions for initial stack pointer and data area (in data cache)
 294  */
 295 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 296 #define CONFIG_SYS_TEMP_STACK_OCM         1
 297 /* On Chip Memory location */
 298 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 299 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 300 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 301 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 302
 303 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 304 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 305 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 306
 307 /*
 308  * Internal Definitions
 309  *
 310  * Boot Flags
 311  */
 312 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 313 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 314
 315 #endif  /* __CONFIG_H */