include/configs/PCI405.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_PCI405           1       /* ...on a PCI405 board         */
  39
  40 #define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r() on init   */
  42
  43 #if 1 /* test-only */
  44 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  45 #else
  46 #define CONFIG_SYS_CLK_FREQ     16000000 /* external frequency to pll   */
  47 #endif
  48
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  51
  52 #if 0
  53 #define CONFIG_PREBOOT                                                          \
  54         "crc32 f0207004 ffc 0;"                                                 \
  55         "if cmp 0 f0207000 1;"                                                  \
  56         "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
  57         "else;echo Old CRC is bad;fi"
  58 #endif
  59
  60 #undef  CONFIG_BOOTARGS
  61 #if 1
  62 #define CONFIG_BOOTCOMMAND                                                      \
  63         "bootm fffc0000"
  64 #else
  65 #define CONFIG_BOOTCOMMAND                                                      \
  66         "mw.l 0 ffffffff; mw.l 4 ffffffff;"                                     \
  67         "while cmp 0 4 1; do echo Waiting for Host...;done;"                    \
  68         "bootm 400000"
  69 #endif
  70
  71 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  72 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  73
  74 #define CONFIG_MII              1       /* MII PHY management           */
  75 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  76
  77 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  78
  79 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  80                                 CFG_CMD_PCI     | \
  81                                 CFG_CMD_IRQ     | \
  82                                 CFG_CMD_ELF     | \
  83                                 CFG_CMD_DATE    | \
  84                                 CFG_CMD_I2C     | \
  85                                 CFG_CMD_BSP     | \
  86                                 CFG_CMD_EEPROM  )
  87
  88 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  89 #include <cmd_confdefs.h>
  90
  91 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  92
  93 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  94
  95 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
  96
  97 /*
  98  * Miscellaneous configurable options
  99  */
 100 #define CFG_LONGHELP                    /* undef to save memory         */
 101 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 102
 103 #define CFG_HUSH_PARSER                 /* use "hush" command parser    */
 104 #ifdef  CFG_HUSH_PARSER
 105 #define CFG_PROMPT_HUSH_PS2     "> "
 106 #endif
 107
 108 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 109 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 110 #else
 111 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 112 #endif
 113 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 114 #define CFG_MAXARGS     16              /* max number of command args   */
 115 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 116
 117 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 118
 119 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 120
 121 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 122 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 123
 124 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 125 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 126 #define CFG_BASE_BAUD       691200
 127
 128 /* The following table includes the supported baudrates */
 129 #define CFG_BAUDRATE_TABLE      \
 130         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 131          57600, 115200, 230400, 460800, 921600 }
 132
 133 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 134 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 135
 136 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 137
 138 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* check for keypress on bootdelay==0 */
 139
 140 /*-----------------------------------------------------------------------
 141  * PCI stuff
 142  *-----------------------------------------------------------------------
 143  */
 144 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 145 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 146 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 147
 148 #define CONFIG_PCI                      /* include pci support          */
 149 #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function    */
 150 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
 151                                         /* resource configuration       */
 152
 153 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 154
 155 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 156 #define CFG_PCI_SUBSYS_DEVICEID 0x0407  /* PCI Device ID: PCI-405       */
 157 #define CFG_PCI_CLASSCODE       0x0280  /* PCI Class Code: Network/Other*/
 158 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 159 #define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
 160 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 161
 162 #if 0 /* test-only */
 163 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 164 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 165 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 166 #else
 167 #define CFG_PCI_PTM2LA  0xef600000      /* point to internal regs       */
 168 #define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
 169 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 170 #endif
 171
 172 /*-----------------------------------------------------------------------
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CFG_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CFG_SDRAM_BASE          0x00000000
 178 #define CFG_FLASH_BASE          0xFFFD0000
 179 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 180 #define CFG_MONITOR_LEN         (192 * 1024)    /* Reserve 196 kB for Monitor   */
 181 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 182
 183 /*
 184  * For booting Linux, the board info and command line data
 185  * have to be in the first 8 MB of memory, since this is
 186  * the maximum mapped by the Linux kernel during initialization.
 187  */
 188 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 189 /*-----------------------------------------------------------------------
 190  * FLASH organization
 191  */
 192 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 193 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 194
 195 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 196 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 197
 198 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 199 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 200 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 201 /*
 202  * The following defines are added for buggy IOP480 byte interface.
 203  * All other boards should use the standard values (CPCI405 etc.)
 204  */
 205 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 206 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 207 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 208
 209 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 210
 211 #if 0 /* Use NVRAM for environment variables */
 212 /*-----------------------------------------------------------------------
 213  * NVRAM organization
 214  */
 215 #define CFG_ENV_IS_IN_NVRAM     1       /* use NVRAM for environment vars       */
 216 #define CFG_ENV_SIZE            0x0ff8          /* Size of Environment vars     */
 217 #define CFG_ENV_ADDR            \
 218         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))   /* Env  */
 219
 220 #else /* Use EEPROM for environment variables */
 221
 222 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 223 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 224 #define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
 225                                    /* total size of a CAT24WC08 is 1024 bytes */
 226 #endif
 227
 228 #define CFG_NVRAM_BASE_ADDR     0xf0200000              /* NVRAM base address   */
 229 #define CFG_NVRAM_SIZE          (32*1024)               /* NVRAM size           */
 230
 231 /*-----------------------------------------------------------------------
 232  * I2C EEPROM (CAT24WC16) for environment
 233  */
 234 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 235 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 236 #define CFG_I2C_SLAVE           0x7F
 237
 238 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 239 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 240 /* mask of address bits that overflow into the "EEPROM chip address"    */
 241 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 242 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 243                                         /* 16 byte page write mode using*/
 244                                         /* last 4 bits of the address   */
 245 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 246 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 247
 248 /*-----------------------------------------------------------------------
 249  * Cache Configuration
 250  */
 251 #define CFG_DCACHE_SIZE         8192    /* For IBM 405 CPUs                     */
 252 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 253 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 254 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 255 #endif
 256
 257 /*
 258  * Init Memory Controller:
 259  *
 260  * BR0/1 and OR0/1 (FLASH)
 261  */
 262
 263 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 264
 265 /*-----------------------------------------------------------------------
 266  * External Bus Controller (EBC) Setup
 267  */
 268
 269 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 270 #define CFG_EBC_PB0AP           0x92015480
 271 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 272
 273 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 274 #define CFG_EBC_PB1AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
 275 #define CFG_EBC_PB1CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 276
 277 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 278 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 279 //#define CFG_EBC_PB2AP           0x038056C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 280 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 281
 282 /* Memory Bank 3 (FPGA internal) initialization                                 */
 283 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 284 #define CFG_EBC_PB3CR           0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 285 #define CFG_FPGA_BASE_ADDR      0xF0400000
 286
 287 /*-----------------------------------------------------------------------
 288  * FPGA stuff
 289  */
 290 /* FPGA internal regs */
 291 #define CFG_FPGA_MODE           0x00
 292 #define CFG_FPGA_STATUS         0x02
 293 #define CFG_FPGA_TS             0x04
 294 #define CFG_FPGA_TS_LOW         0x06
 295 #define CFG_FPGA_TS_CAP0        0x10
 296 #define CFG_FPGA_TS_CAP0_LOW    0x12
 297 #define CFG_FPGA_TS_CAP1        0x14
 298 #define CFG_FPGA_TS_CAP1_LOW    0x16
 299 #define CFG_FPGA_TS_CAP2        0x18
 300 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 301 #define CFG_FPGA_TS_CAP3        0x1c
 302 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 303
 304 /* FPGA Mode Reg */
 305 #define CFG_FPGA_MODE_CF_RESET  0x0001
 306 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 307 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 308 #define CFG_FPGA_MODE_TS_CLEAR  0x2000
 309
 310 /* FPGA Status Reg */
 311 #define CFG_FPGA_STATUS_DIP0    0x0001
 312 #define CFG_FPGA_STATUS_DIP1    0x0002
 313 #define CFG_FPGA_STATUS_DIP2    0x0004
 314 #define CFG_FPGA_STATUS_FLASH   0x0008
 315 #define CFG_FPGA_STATUS_TS_IRQ  0x1000
 316
 317 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 318 #define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
 319
 320 /* FPGA program pin configuration */
 321 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 322 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 323 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 324 #define CFG_FPGA_INIT           0x00400000  /* FPGA init pin (ppc input)     */
 325 #define CFG_FPGA_DONE           0x00800000  /* FPGA done pin (ppc input)     */
 326
 327 /*-----------------------------------------------------------------------
 328  * Definitions for initial stack pointer and data area (in data cache)
 329  */
 330 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
 331 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
 332 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 333 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 334 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 335 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 336
 337 /*
 338  * Internal Definitions
 339  *
 340  * Boot Flags
 341  */
 342 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 343 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 344
 345 #endif  /* __CONFIG_H */